JPH04326281A - Inter-frame predictive encoder/decoder - Google Patents

Abstract

PURPOSE:To miniaturize the entire device by mounting memories for frame memory and smoothing at a single LSI memory and reading a variable length code word, which is inputted/outputted to the memory for smoothing, through a memory with small capacity. CONSTITUTION:When using an LSI memory 41 as the frame memory, the address terminal of the LSI memory 41 is connected through an address changeover switch 42 to an address generating circuit 4 for frame memory. The address generating circuit 4 for frame memory is stepped by activation from a variable length encoding circuit 7 and reads out a reference frame signal at a prescribed position. The variable length code word generated at the variable length encoding circuit 7 is stored in a small capacity memory 44 and when the stored amount is higher than a threshold value, the interruption of variable length encoding is requested from the small capacity memory 44 to the variable length encoding circuit 7. Thus, the address changeover switch 42 is changed over, and the address terminal of the LSI memory 4 is connected to a memory write address generating circuit 10 for smoothing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding device for TV signals and the like, and in particular to miniaturization of an inter-frame predictive coding device that has a high redundancy compression rate for TV signals.

0002

2. Description of the Related Art As is well known, in order to directly transmit a TV signal as a digital signal, approximately 100 Mbit/s is required.
Requires EC transmission speed. Various high-efficiency encoding methods have been proposed to reduce the transmission speed and transmission cost. Among them, in order to achieve a high compression rate, a method that combines "interframe prediction" and "variable length coding" is often adopted.

"Interframe prediction" refers to predicting the TV signal of the currently encoded screen using the transmitted previous screen (reference frame) signal, and calculating the difference (predicted) between the predicted value and the signal to be encoded. error). In a normal TV signal, there is a large proportion of the screen that is stationary, so
Most prediction errors are 0 or have absolute values close to 0. Therefore, it is known that the frequency of occurrence of prediction errors is extremely biased around 0.

[0004] Therefore, using "variable length coding", short code words are assigned to prediction errors that occur frequently, and long code words are assigned to prediction errors that occur less frequently. As a result, the average code word length sent to the transmission path can be significantly reduced compared to fixed-length encoding, and transmission efficiency can be improved.

[0005] Therefore, since coding efficiency can be improved by combining interframe prediction and variable length coding, this combination is often employed.

[0006]

SUMMARY OF THE INVENTION In order to realize interframe prediction, a frame memory is required to store reference frame signals. Furthermore, when variable-length coding is adopted, the codeword length fluctuates due to prediction errors, but the transmission speed of the codeword on the transmission path needs to be constant, so the variable-length codeword is stored once, A smoothing memory is required for reading at a constant speed. These frame memories and smoothing memories each have a large capacity, which has been an obstacle to making the image encoding/decoding device more compact and economical.

Since the storage capacity of conventional LSI memories was small, it was necessary to separately implement an LSI memory for frame memory and an LSI memory for smoothing. However, with the increase in storage capacity of LSI memories in recent years, it has become possible to store both frame memory and smoothing memory with a single LSI memory. Nevertheless, in the past, the frame memory and smoothing memory were implemented using different general-purpose LSI memories, or the frame memory was a general-purpose LSI memory, and the smoothing memory was implemented in an LSI dedicated to encoding and decoding. The company adopted methods such as implementation.

Therefore, in response to the recent increase in the storage capacity of LSI memories, it has become an issue to realize a memory control system that allows a single LSI memory to serve as both a frame memory and a smoothing memory. That is, the challenge is to realize a memory control system that allows two types of reading and writing operations, one for frame memory and one for smoothing, to be performed independently on a single LSI memory.

[0009]

[Means for Solving the Problems] In order to solve the above problems, the encoding device includes a frame memory address generation circuit, a smoothing write address generation circuit, a smoothing read address generation circuit, and the above three address generation circuits. An address switching circuit that switches the address generated by the generation circuit, a write signal switching circuit that switches between the frame memory write signal and the smoothing memory write signal, a read signal holding circuit that takes in the read signals from the frame memory and the smoothing memory, and variable length. A first small capacity memory that stores the encoded signal before writing it into the smoothing memory, a second small capacity memory that stores the signal read from the smoothing memory before sending it out to the transmission path, and the second small capacity memory described above. a memory control circuit that prohibits reading and writing to the frame memory according to the accumulated amount of signals in the small-capacity memory, and reads and writes signals between the small-capacity memory and the smoothing memory after the prohibited state is reached. .

Similarly, the decoding device includes a frame memory address generation circuit, a smoothing write address generation circuit, a smoothing read address generation circuit, and the above three.
an address switching circuit that switches addresses generated by the standard address generation circuit, a write signal switching circuit that switches between a frame memory write signal and a smoothing memory write signal, and a read signal holding circuit that takes in read signals from the frame memory and smoothing memory, respectively. , a third small-capacity memory for storing the variable-length coded signal received from the transmission path before writing it into the smoothing memory, and a fourth memory for storing the variable-length coded signal read from the smoothing memory before variable-length decoding.
A memory that prohibits reading and writing to the frame memory according to the accumulated amount of signals in the two small-capacity memories, and reads and writes signals between the small-capacity memory and the smoothing memory after the inhibited state has been reached. A control circuit.

[0011]

[Operation] Normally, by connecting the address terminal of the LSI memory to the frame memory address generation circuit, no problem occurs when using the LSI memory as a frame memory. Also, after prohibiting reading and writing as frame memory,
By connecting the address terminal of the LSI memory to the read/write address generation circuit of the smoothing memory, it also operates as a smoothing memory.

However, when an LSI memory is used as a frame memory and then used as a smoothing memory, the following problems generally occur. That is, some waiting time may be required when switching from frame memory use to smoothing use. This is because reading and writing from the frame memory is usually done in units of a fixed number of signals, such as scanning lines, so once reading and writing of signals from the frame memory is started, the smoothing memory is used until the reading and writing of signals from the frame memory is completed. This is because there are cases where switching to is not possible.

Therefore, in the present invention, as described above, variable length encoding results are stored in the LSI memory via the small capacity memory, and signals stored in the LSI memory via the small capacity memory are processed at a constant speed. Send it to the transmission path. This results in
The switching time from the frame memory to the smoothing memory can be compensated for.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS To facilitate the explanation of the present invention, the configuration of conventional interframe predictive coding will be briefly described using FIG.

(1) TV imaged by TV camera 1
The signal is converted to analog/digital by analog/digital converter 2.
It is digitally converted and becomes an encoded frame signal.

(2) A reference frame signal is read from the frame memory 3. The address of the frame memory 3 is generated by a frame memory address generation circuit 4. The frame memory address generation circuit 4 advances upon activation from the variable length encoding circuit 7 and reads out a reference frame signal at a predetermined position. A subtraction circuit 5 calculates the difference between the read reference frame signal and the encoded frame signal. This is called interframe prediction error.

(3) The above interframe prediction error is
After being quantized by the quantization circuit 6, the variable length encoding circuit 7
The data is variable-length coded at , passed through a smoothing memory 8 , read out at a constant speed, and sent to a transmission path 9 . The write address of the smoothing memory 8 is generated by a smoothing memory write address generation circuit 10. The write address generation circuit 10 is incremented each time a variable length code word is sent from the variable length encoding circuit 7. The smoothing memory read address is generated by the smoothing memory read address generation circuit 11. The read address generation circuit 11 is incremented each time a code word is read onto the transmission line 9. The smoothing address changeover switch 12 is switched in response to reading or writing to the smoothing memory, and the smoothing read address or write address is connected to the address terminal of the smoothing memory 8.

(4) The interframe prediction error quantized by the quantization circuit 6 is dequantized by the dequantization circuit 13, and then added to the reference frame signal by the addition circuit 14, and stored in the frame memory. 3. The signal stored in the frame memory 3 is used as a reference frame signal when predictively encoding the next frame.

The above is the configuration of the conventional encoding device. Next, the conventional configuration of a receiving side decoding device will be explained using FIG. 5.

(1) The variable length encoded signal received at a constant speed via the transmission line 9 is read out to the variable length decoding circuit 22 via the smoothing memory 21.

(2) The variable length decoding circuit 22 decodes the signal to obtain a quantized value of the prediction error signal, and obtains the original prediction error signal via the inverse quantization circuit 23.

(3) The prediction error signal is sent to the adder circuit 2.
4, it is added to the reference frame signal stored in the frame memory 25 and restored to the original TV signal.

(4) The TV signal is displayed on the display device 27 after being subjected to digital/analog conversion by the digital/analog converter 26. The above TV signal is
The signal is stored in the frame memory 25 and used as a reference frame signal for the next frame. (5) In the above, the read/write address of the smoothing memory 21 is generated by the smoothing write address generation circuit 28 and the smoothing read address generation circuit 29,
It is switched by the smoothing address changeover switch 30. The address of the frame memory 25 is generated by a frame memory address generation circuit 31.

As explained above, conventionally, both encoding and decoding devices have separate memories for frame memory and smoothing. Next, FIG. 3 shows an embodiment in which a frame memory and a smoothing memory are shared, which is a feature of the present invention. That is, if the size of the LSI memory is 512 x 512 and the frame memory area is 352 x 288, then
For example, (512-288) x 51 of the remainder as shown in the figure
2 is allocated to the smoothing memory.

A case in which the above-mentioned shared use of the frame memory and smoothing memory is applied to an encoding device will be explained with reference to FIG. Note that circuits given the same numbers as in FIG. 4 have equivalent functions.

(1) When the LSI memory 41 is used as a frame memory, the address generated by the frame memory address generation circuit 4 and the address generated by the smoothing memory write/read address generation circuits 10 and 11 are The frame memory address is connected to the address terminal of the LSI memory 40 through the address changeover switch 42 that switches the frame memory address. At the same time, the frame memory write signal is connected to the data write terminal of the LSI memory 40 through the LSI memory write signal changeover switch 43.

(2) The variable length code word generated by the variable length encoding circuit 7 is stored in the first small capacity memory 44. When the storage amount in the first small capacity memory 44 exceeds a predetermined threshold, the small capacity memory 44 outputs a control signal to the variable length encoding circuit 7 to request interruption of variable length encoding.

(3) The variable length encoding circuit 7 takes in the above interruption request when it becomes possible to interrupt processing, such as at a break in signal processing in units of scanning lines, etc., and sends out a first interruption request acceptance signal. This switches the address changeover switch 42 to connect the address terminal of the LSI memory 41 to the smoothing memory write address generation circuit 10. The write signal changeover switch 43 connects the output signal of the first small capacity memory 44 to the data write terminal of the LSI memory 41 .

(4) At the same time as above, the variable length encoded signal is read out from the second small capacity memory 45 at a constant speed and sent to the transmission line 9. When the storage amount in the second small capacity memory 45 becomes less than a predetermined value, a control signal is issued to the variable length encoding circuit 7 similarly to (2) to request interruption of variable length encoding.

(5) Similarly to (3), the variable length encoding circuit 7 receives the above interruption request at a time when interruption is possible, and
A second interrupt request acceptance signal is sent. As a result, the address changeover switch 42 is switched to connect the smoothing memory read address generation circuit 11 to the address terminal of the LSI memory 41. At the same time, the second small capacity memory 45
The variable length encoded signal read from the LSI memory 41 is written into the second small capacity memory 45 by setting it in a write state and incrementing the write address of the second small capacity memory 45.

Next, a case in which the present invention is applied to a decoding device will be described in detail using FIG. In the figure, components given the same numbers as those in FIG. 5 have equivalent functions.

(1) When the LSI memory 51 is used as a frame memory, the addresses generated by the frame memory address generation circuit 31 and the addresses generated by the smoothing memory write/read address generation circuits 28 and 29 The frame memory address is connected to the address terminal of the LSI memory 51 through an address switching circuit 52 that switches between the frame memory address and the address terminal of the LSI memory 51. At the same time, the LSI memory write signal switching circuit 53 connects the frame memory write signal to the data write terminal of the LSI memory 51.

(2) The variable length encoded signal input from the transmission line 9 at a constant speed is written into the third small capacity memory 54. When the storage amount in the third small capacity memory 54 exceeds a predetermined value, a control signal is output to the variable length decoding circuit 22 to request interruption of variable length decoding.

(3) The variable length decoding circuit 22 takes in the above interruption request when the decoding process can be interrupted, such as at a break in scanning line processing, and sends out a third interruption request acceptance signal. As a result, the address switching circuit 52 is switched to
A write address for the smoothing memory is connected to the address terminal of the SI memory 51 to set it in a write state. Furthermore, the write signal switching circuit 53 causes the third small capacity memory 54 to
The output terminal of the LSI memory 51 is connected to the data write terminal of the LSI memory 51. At the same time, by incrementing the read address of the third small capacity memory 54, the variable length encoded signal written in the third small capacity memory 54 is written to the LSI memory 51.

(4) The variable length decoding circuit 22
The variable length code word is read from the small capacity memory 55 of. Fourth
When the storage amount in the fourth small capacity memory 55 becomes less than a predetermined threshold, a control signal is sent from the fourth small capacity memory 55 to the variable length decoding circuit 22 to request interruption of variable length decoding.

(5) The variable length decoding circuit 22 takes in the above interruption request when interruption is possible, and sends out a fourth interruption request acceptance signal. In response to this fourth interruption request acceptance signal, the address switching circuit 52 connects the smoothing memory read address generation circuit 29 to the address terminal of the LSI memory 51. At the same time, the write address of the fourth small capacity memory 55 is incremented to enter the write state, so that the variable length encoded signal is transferred to the LSI memory 55.
from there to the fourth small capacity memory.

With the operations described above, a single LSI memory can realize the functions of both a frame memory and a smoothing memory in both encoding and decoding.

In the above embodiment, simple inter-frame prediction was explained as inter-frame prediction, but ``motion-compensated inter-frame prediction'' detects the amount of motion between frames, compensates for it, and then performs inter-frame prediction. The present invention is also applicable to "prediction".

The present invention can also be applied to the following modification of the quantization method.

(1) Instead of simply quantizing the prediction errors between frames, a method of vector quantizing a plurality of the above prediction errors at once.

(2) An orthogonal transform encoding method in which a plurality of the above prediction errors are similarly grouped together, orthogonally transformed, and the orthogonal transform results are quantized.

[0042]

[Effect of the invention] According to the present invention, a dedicated LSI and a single LS
I-memory makes it possible to realize an encoding device and a decoding device. This contributes to miniaturization and economicalization of the image encoding/decoding device, and is therefore of great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an interframe encoding device of the present invention.

FIG. 2 is a block configuration diagram of an interframe decoding device of the present invention.

FIG. 3 is a diagram showing an example of division of an LSI memory into a frame memory area and a smoothing memory area when the present invention is applied.

FIG. 4 is a block configuration diagram of a conventional interframe encoding device.

FIG. 5 is a block diagram of a conventional interframe decoding device.

[Explanation of symbols]

1...TV camera, 2...analog/digital converter, 3
, 25...Frame memory, 4, 31...Address generation circuit for frame memory, 5...Subtraction circuit, 6...Quantization circuit, 7
...Variable length encoding circuit, 8, 21... Smoothing memory, 9... Transmission line, 10, 28... Memory write address generation circuit for smoothing, 11, 29... Memory read address generation circuit for smoothing, 12, 30, 42, 43, 52, 53... Switch, 13, 23... Inverse quantization circuit, 14, 24... Addition circuit, 22... Variable length decoding circuit, 26... Digital/analog converter, 27... Display device, 41, 51 ...LSI memory, 44, 45, 54, 55...Small capacity memory.

Claims (1)

[Claims] Claim 1: An interframe predictive coding/decoding device including a frame memory for storing a TV signal of a reference frame and outputting a predicted value, and sending a variable length coded signal to a transmission path at a constant speed. 1. An interframe predictive coding/decoding device, characterized in that a smoothing memory and a smoothing memory are implemented in the same memory chip.