KR100296095B1 - Frame record control circuit in decoder of hdtv receiver - Google Patents

Abstract

PURPOSE: A frame record control circuit in a decoder of an HDTV receiver is provided to simultaneously select a memory in which the current frame data is written and a memory from which the current frame data is read using picture forms of previous two frames. CONSTITUTION: A frame record control circuit in a decoder of an HDTV receiver includes the first, second and third buffer memories(22,23,24), and a controller(21). The first, second and third buffer memories store the current frame data and two previous frames data items, respectively. The controller selects one of the first, second and third buffer memories, in which the current frame data will be written, using picture forms of the two previous frames and, simultaneously, selects one of the buffer memories, from which the current frame data will be read.

Description

Frame recording control circuit in decoder of high definition television receiver

1 is a block diagram showing a general decoder in a high definition television receiver;

2 is a circuit diagram showing a frame write control circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

21: controller 22, 23, 24: buffer memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder of a high definition television (hereinafter, referred to as HDTV) receiver, and more particularly to a frame recording control circuit for controlling the recording form of a current frame using the picture form of a previous frame.

HDTV is the next generation TV that provides large screen, high-definition video, and compact disc-quality sound. It is a new integrated product that covers electronic, information, and digital communication technologies. The impact is very large.

1 is a block diagram showing a decoder applied to a general HDTV receiver. Referring to FIG. 1, the VLD 11 performs variable length decoding to restore an encoded video signal transmitted through a channel to a signal before variable length encoding, and the inverse quantizer IQ 12 In order to restore the decoded video signal to the signal before quantization, the variable length decoder 11 outputs it by inverse quantization. The inverse discrete cosine transformer (IDCT) 13 performs inverse discrete cosine transform to restore the inverse quantized image signal from the inverse quantizer 12 to the signal before the discrete cosine transform, and the adder 14 inverts the discrete cosine transformer 13. ) And the motion compensated video signal are added to output the final reconstructed video. The frame delay 15 stores the reconstructed image output from the adder 14 in units of frames, and the motion compensator MC 16 compensates the motion by referring to the reconstructed image of the previous frame stored in the frame delay 15 and adds the adder. Output to (14).

Looking at the algorithm used in the above-described decoder, frame recording is required during the decoding process. For example, if there is no frame recording during the decoding process, I → P → B → B ... will be displayed in the order of I → B → B → P .... Here, the I frame is a frame to which only interframe coding is applied, and the P frame is a frame that is predictively encoded by a forward motion estimation and compensation from a previous I frame or a P frame, and a B frame is a before and after I frame. It is a frame that is predictively encoded by bidirectional motion compensation from two frames of frame or P frame.

Therefore, the decoded frames must be rearranged in the order of I → P → B → B ... to display them in the order of I → B → B → P .... It requires a control circuit to control.

Conventionally, the absolute position of the frame order is set using the PTS of the header information. In this case, additional information is additionally input when the frame is rearranged.

Accordingly, an object of the present invention is to provide a frame write control circuit for selecting a memory to be read at the same time using the picture form of the previous two frames in the decoder of the HDTV receiver in order to solve the above problems. To provide.

In order to achieve the above object, in the decoder of an HDTV receiver, the frame recording control circuit according to the present invention is

First to third buffer memories for storing current frame n, previous frame n-1, and previous frame n-2 data; And

The memory of the first to third buffer memories is selected from among the first to third buffer memories using the picture types of the previous two frames n-1 and n-2, and the data of the current frame n is selected. It characterized in that it comprises a controller for selecting a memory to read.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

2 is a circuit diagram showing a frame write control circuit according to the present invention, and includes first to third buffers for storing data of a current frame n, a previous frame n-1, and a previous frame n-2, respectively. Data of the current frame n among the first to third buffer memories 22, 23, and 24 using the memory 22, 23, and 24 and the picture form of the previous two frames n-1 and n-2. And a controller 21 for selecting a buffer memory for writing data and selecting a buffer memory for reading data of the current frame n.

The operation according to the configuration of FIG. 2 is as follows.

In order to implement the frame write control circuit according to the present invention, a buffer memory for storing three types of frame data, namely, the current frame n, the previous frame n-1, and the previous frame n-2, 22, 23, 24). This frame buffer memory is composed of DRAM.

The frame write control circuit according to the present invention receives only the picture type P_TYPE as shown in FIG. This picture type (P_TYPE) is a signal that changes in units of frames and means a picture type of frame data input to the write data bus W_data_bus. The picture type (P_TYPE) is represented by 2 bits because there are three types of I, B, and P frames.

The controller 21 writes data to one buffer memory of the three frame buffer memories 22, 23, and 24, and reads data into one buffer memory using ADDR, / W, CAS, and RAS signals. Control the operation. Since the ADDR, CAS, and RAS signals are responsible for addressing one frame for each frame, a buffer memory for writing data and a buffer memory for reading data are selected according to the write control signal (/ W). This is expressed as a table as follows.

Here, I frame is regarded as P frame.

In the table, an index is added for convenience, and a P1 position at a read and write position means a buffer memory to which a P1 frame is written. In addition, "Another" means a buffer memory other than the buffer memory in which the frame n-2 and the frame n-1 are written.

That is, when frame n-2 is a P frame, the write position is a buffer memory other than the buffer memory in which frames n-2 and n-1 have been written, and are not frames n-2 P frames. In this case, the write position is the buffer memory in which the frame n-2 is written.

On the other hand, when frame n-1 is a B frame, the read position is a buffer memory to which frame n-1 is written, and when frame n-2 is a P frame, the read position is frame n-2. When this buffer memory is written and the frame n-2 is not a P frame, the read position is a buffer memory other than the buffer memory in which the frames n-2 and n-1 have been written.

As described above, in the decoder of the high-definition television receiver, the frame recording control circuit according to the present invention selects the memory to write the current frame by using the picture form of the previous two frames and selects the memory to be read out, thereby providing the codec algorithm of the HDTV. There is an advantage that can easily solve the reverse of the frame order caused by.

Claims (1)

First to third buffer memories 22, 23, and 24 for storing current frame n, previous frame n-1, and previous frame n-2 data, respectively; And When the previous frame (n-2) is a P frame, the data writing position of the current frame (n) is a buffer memory other than the buffer memory in which the previous frame (n-2) and the previous frame (n-1) are written. If the previous frame (n-2) is not a P frame, the previous frame (n-2) is selected as the buffer memory to which the previous frame (n-2) is written, and the data reading position of the current frame (n) is the previous frame (n-1). Is the buffer memory where the previous frame (n-1) is written, and the previous frame (n-2) is the buffer memory where the previous frame (n-2) is written, and the previous frame (n-2) when the previous frame (n-2) is a P frame. A decoder 21 for selecting a buffer memory other than the buffer memory in which the previous frame n-2 and the previous frame n-1 have been written if the frame is not the P frame. A frame write control circuit.