KR0136612B1 - Slow regenerative apparatus and method of a hdtv decoder - Google Patents

Abstract

The present invention relates to a slow reproducing apparatus and method for an HDTV decoder in which a slow reproducing function is added to a memory control unit of an image compression signal demodulation unit so that the HDTV decoder can process slow reproducing.

In view of the conventional technology, the HDTV decoder could not have a slow playback function in connection with an HDVCR or another recording and playback system. Accordingly, the present invention controls the decoding of the VLD unit, controls the decoding of the VLD unit, It is configured to control the light according to the slow playback mode, determines the VLD enable signal high picture coding type, controls the multiplexing of the read / write and multiplexer of the frame memory and the memory unit according to the picture coding type, and the VLD enable signal. By preventing writing to the raw frame memory and controlling the multiplexing of the read / write and multiplexer of the frame memory according to the toggle signal, it can be decoded and displayed in slow playback mode without adding a separate memory or a large amount of logic. HDTV decoder can be implemented The.

Description

Slow playback device and method of HDTV decoder

1 is a block diagram of a typical HDTV decoder.

2 is a diagram showing examples of input / output and decoder output of a general HDTV encoder.

3 is an operation timing diagram for implementing FIG.

4 is an operation flowchart of the membrane control unit of FIG.

5 is a configuration diagram of a VLD enable signal generator of a memory controller according to the present invention.

6 is a block diagram of a frame memory read / write signal generator of the memory controller according to the present invention.

7 is a configuration diagram of a memory unit write signal generator of the memory controller according to the present invention.

8 is a configuration diagram of a selection signal generator of a memory controller according to the present invention.

9 is an operation timing diagram of the present invention.

10 is a flowchart of the operation of the present invention.

* Explanation of symbols for main parts of the drawings

1: Video buffer 2: VLD part

3: inverse quantization and inverse CDT section 4: adder

5: Motion Compensation Unit 6, 7: Frame Memory

8 memory unit 9 memory control unit

10: VLD enable signal generator 11: frame memory read / write signal generator

12: memory unit write signal generator 13: selection signal generator

The present invention relates to an apparatus and method for slow playback of an HDTV decoder. More particularly, the present invention provides a slow play back function to a memory control unit of an image compression signal demodulation unit. The present invention relates to a slow playback apparatus and method of an HDTV decoder.

In general, the function of the HDTV decoder is to interpret the input bit stream to form image data and output the image data to a video display processor (VDP). FIG. 1 illustrates a configuration of a general HDTV decoder.

The video buffer 1 temporarily stores the bit stream input at a constant bit rate, and the variable length decoder 2 extracts the bit stream from the video buffer 1 in accordance with the frame time to obtain coefficient data and motion vectors. (Motion Vector) and other information necessary for composing the image are interpreted.

The coefficient data are converted into pixel values in the inverse quantization and inverse DCT unit 3, which are added to the motion compensated signal of the motion compensator 5 in the adder 4 to form an image (P or B picture). ) Outputs immediately (I picture).

The frame data is alternately stored in the frame memories 6 and 7 and used when composing the next image. The motion compensator 5 uses an adder using a motion vector decoded by the VLD 2. The reference image IR (t) is output to 4).

In addition, the memory unit 8 and the multiplexer MUX1 provided for frame reordering are used to change the order of the frames to be output, and the read of the frame memories 6, 7, and 8 may be performed. The memory control unit 9 for generating the write control and the selection signal of the multiplexer MUX1 performs control in units of frames.

On the other hand, when the I, P, B frames are described, they are frame components of a general video signal. I-frames process image compression data using pure spatial trans form without motion compensation. Image compression is performed by motion compensation using a forward motion vector, and the B frame performs image compression more efficiently by selectively using a forward motion vector and a backward motion vector.

The video encoder encodes and outputs the input image into I, P, and B frames as shown in FIGS. 2A to 2C, decodes it in a decoder, and reconstructs and outputs it in the order input from the encoder.

That is, since the B frame may be composed of I and P frames before and after, P to be displayed later than B should be decoded first, so that P is decoded first. After the frame is output, the P frame is exported.

As shown in FIG. 2, the flow of data between the frame memories 6, 7 and the memory unit 8 must be controlled so that the order of the decoded frame and the displayed frame is different.

In FIG. 3, one frame of data is decoded by the VLD unit 2 during one period of the frame clock.

In order to rearrange and display the decoded frame data, there is a delay of one frame between the decoding time and the display time.

On the other hand, if the frame memory 6 is referred to as FMA, the frame memory 7 is referred to as FMB, and the memory unit 8 is referred to as FMR, the FMR delays the data of I and P frames by one frame. When the B frame is decoded, it is selected by the multiplexer (MUX1) so that it is displayed as it is decoded without going through the FMR.

The role of the multiplexer MUX1 depends on the picture coding type (I, P, B) of the frame currently being decoded. When I or P is selected, the output of the FMR is selected, and when the B picture is selected, the output of the VLD unit 2 is selected. Done.

Referring to FIG. 4 together with the flowchart of FIG. 4, first, it is determined which picture coding type is (S1), and in the case of an I or P frame, it is determined whether the toggle signal is 0 or 1 (S2).

In the I or P frame, whether the FMA is read or written depends on whether the toggle signal is 0 or 1, and the FMB is operated in the opposite way to the read and write operation of the FMA. In FMR, read and write operations always continue in I and P frames, and FMR does not operate at all in B frames.

That is, if it is determined in step S2 that the toggle signal is 0, writing to the FMB is performed without writing to the FMA, reading to the FMA, and not reading from the FMB (S3).

When the toggle signal is determined to be 1, FLEM and writing of FMA and FMB are performed in contrast to step S3 (S4). After performing steps S3 and S4, writing to FMR and reading from FMB is performed by multiplexer. The selection signal of (MUX1) is set to 1 and toggled, and the toggle is inverted frame by frame in the case of I and P frames (S5-S7).

On the other hand, if it is determined in the step S1 that the picture coding type is B frame, reading from FMA and FMB is performed without writing to FMA and FMB, and reading from FMB without writing to FMR and multiplexer MUX1 is performed. The selection signal is set to 0 (S8-S10).

The prior art relocates the displayed frames using a frame memory for reconstructing P or B frames and a memory unit for delaying I or P, which is conventionally known as HDVCR or other recording. Slow playback could not be performed when connected to the medium.

The present invention is to solve this problem, the object of the present invention is to control the data flow between the memory to fit the slow playback mode, HDTV decoder can accommodate the slow playback function in conjunction with the recording and playback system without the addition of memory An apparatus and method for slow playback of an HDTV decoder are provided.

A feature of the present invention for achieving the above object is a VLD unit for decoding an input video signal and outputting a motion vector, a dequantization and inverse DCT unit, a motion compensation unit, the first and second frame memories in which I or P frames are stored; An HDTV decoder comprising a memory unit and a multiplexer for frame rearrangement of a video signal, and a memory controller for controlling read / write and multiplexing of the first and second frame memories and the memory unit. A slow playback apparatus of an HDTV decoder configured to control decoding and to control read and write of the first and second frame memories and the memory unit in a slow playback mode.

According to another aspect of the present invention, there is provided a first step of determining a VLD enable signal high picture coding type, and a second step of controlling read / write and multiplexing of the first and second frame memories and the memory unit according to the picture coding type. And a third step of prohibiting writing to the first and second frame memories when the VLD enable signal is low and controlling multiplexing of the read / write and multiplexers of the first and second frame memories and the memory unit according to the toggle signal. There is a slow playback method of HDTV decoder.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the present invention is to control the decoding of the VLD without additional memory to perform the slow playback mode, and to control the read and write signals between the memory to the slow playback mode, to obtain the slow playback mode, the normal decoding in the HDTV decoder The previous frame may be repeatedly displayed by one frame between each frame while the memory controller controls the data path between each frame memory according to the picture coding type (I, P, B) in the conventional configuration of FIG. 9) should be configured.

That is, the memory control unit 9 is a VLD enable signal generation unit 10 for generating the enable signal of the VLD unit 2 in the frame clock period in the slow playback mode, and the VLD enable signal generation unit 10. A frame memory read / write signal generator 11 for controlling reads and writes of the frame memories 6 and 7 according to the VLD enable signal and the frame clock from the VLD enable signal generator 10; A multiplexer according to the VLD enable signal generation unit 12 and the memory unit write signal generation unit 12 which generates a write signal of the memory unit in response to the VLD enable signal input from It consists of a selection signal generator 13 for generating a selection signal of MUX1, and the same reference numerals are used for the same parts as in the prior art.

The VLD enable signal generator 10 is configured as a T flip-flop TFF1 as shown in FIG. 5, and the frame memory read / write signal generator 11 is shown in FIG. AND gate AND1 to which the VLD enable signal and I or P frame data are input, and T flip-flop TFF2 to which the frame clock is input to the clock terminal when the output of the AND gate AND1 is input to the toggle input terminal T. ), The AND gate AND2 to which the VLD enable signal and the B frame data are input, the output of the AND gate AND1, and the output of the T flip-flop TFF2 are input to write the write signal of the frame memory 6. The generated AND gate AND3 and the output of the T flip-flop TFF2 are inverted by the inverter INV1 and the output of the AND gate AND1 are input to generate a write signal of the frame memory 7. AND gate AND4 and the output of the T flip-flop TFF2 are Ora gate OR1 for inputting the signal inverted by the input signal INV2 and the output of the AND gate AND2 to generate a read signal of the frame memory 6, the output of the AND gate AND2, and the T; The output of the flip-flop TFF2 is input to constitute an OR gate OR2 which generates a read signal of the frame memo 7.

As shown in FIG. 7, the memory unit write signal generator 12 includes a NLD gate NAND1 for inputting a VLD enable signal and I or P frame data to generate a memory unit write signal.

In addition, the selection signal generator 13 receives an inverter INV3 for inverting data of an I or P frame, an output of the inbuffer INV3, and a VLD enable signal as shown in FIG. And a NAND gate NAND2 for generating a select signal of the multiplexer MUX1.

According to the present invention having the configuration described above, in the slow play mode, as shown in FIG. 9, the decoding enable signal of the VLD is decoded by only one frame section for every two frames, and the next one frame section stops decoding and waits. To do that.

At this time, 1I, 4P, 2B, 3B, 7P, 5B,... At two frame intervals. … Decoded in VLD in order to display 1I, 1I, 2B, 2B, 3B, 3B, 4P, 4P, 5B, 5B,... … Display in order.

The delay in decoding and display is two frames. Each frame is divided into a decoding frame and a repeating frame. The decoding frame is a frame having a VLD decoding enable of 1, and the repeating frame is a frame having a VLD enable of 0.

When the frame memory 6 is FMA, the frame memory 7 is FMB, and the memory unit 8 is FMR, the frame written to the FMA and FMB is cryptic when the frame is written in the I or P frame as in the normal mode. This means that only decoded frames are written to FMA and FMB.

Even if I or P frames, the VLD does not decode during the repeating frame period, so writing to the FMA and FMB is stopped.

The FMA and FMB are only read during the repetitive frame period, in the same way as when the motion vector is zero.

Which FMA or FMB to read in a repeating frame is crypted at every I or P frame, as in writing. Unlike writing at the start of a decoding frame when writing the view, it is toggled at the beginning of the repeating frame.

And, like the normal mode, the B frame is not written in the FMA and FMB, but the difference is that the B frame is also written in the FMR. This is because FMR is used as a memory for frame repetition.

The FMR write control writes the input of the FMR regardless of decoding or repeating frames in the case of B frames, but in the case of I or P frames, writes are prohibited in the decoding frames and only written in the repeating frames. This is because the frame that was used must be displayed in the repeating frame.

In addition, the frame output to the display is selected by the multiplexer (MUX1). When the selection signal of the multiplexer (MUX1) is 0, the frame data is decoded in the VLD or the signal output from the FMA and FMB is selected. Will be selected.

In addition, the selection signal of the multiplexer (MUX1) is controlled differently in the case of I or P frame and B frame. In I or P frame, the selection signal of FMR is selected regardless of the repeated frame and the decoded frame. Selects 0 to display the B-frame decoded in the current VLD and 1 to select the data output from the FMR to display the B-frame data one more time in the repetitive frame.

In this case, the output from FIG. 9 to VDP is 1I, 1I, 2B, 2B, 3B, 3B, 4P, 4P... … It is output in order of being able to display in slow playback mode.

On the other hand, the VLD enable signal generator 10 for outputting as described above repeats the VLD enable signal 0 and 1 in the frame clock period when the slow play mode signal is 1, that is, when the slow play mode signal is 1.

The frame memory read / write signal generator 11 activates the write of the FMA and the FMB when the VLD enable signal is 1 in the I or P frame, and the read signal is activated only when the VLD enable signal is zero.

In addition, the memory unit write signal generation unit 12 generates an FMR write signal according to the VLD enable signal, which prohibits writing only when the VLD enable signal is 1 and I or P frames, and writes all other cases. .

When the VLD enable signal is 1 in the B frame, the selection signal generator 13 selects the VLD output, and in other cases, selects the output of the FMR.

This will be described with reference to the flowchart of FIG. 10 as follows.

First, it is determined whether the VLD enable signal is 1 or 0 (S11). If the VLD enable signal is 1, it is not written to the FMR in step S16 to display the same frame twice. The steps S12-S15, S17-S19, and S21 are the same as before, except that reading is performed, writing to the FMR in step S20, and reading from the FMB.

If the VLD enable signal is 0, it is not written to FMA and FMB (S22), and it is determined whether the toggle signal is 1 or 0 (S23).

If it is determined that the toggle signal is 0, it reads from the FMA and does not read from the FMB. If the toggle signal is determined to be 1, the lead signal is read from the FMB without reading from the FMA. After that, the selection signal of the multiplexer MUX1 is set to 1 (S24-S27).

As described above, the present invention can implement an HDTV decoder capable of decoding and displaying in slow playback mode without adding a separate memory or a large amount of logic, so that the HDTV decoder can be used by connecting to an HDVCR or another recording / playing system. In this case, the slow playback provided by the recording / playback system can be accommodated.

Claims (6)

A VLD unit for decoding an input image signal and outputting a motion vector, an inverse quantization and inverse DCT unit, a motion compensator, first and second frame memories storing I or P frames, and repositioning frames of an image signal 10. A HDTV decoder having a memory section and a multiplexer, and a memory control section for controlling read / write and multiplexing of the first and second frame memories and the memory section, wherein the memory control section controls the decoding of the VLD section. 1, Slow playback device of the HDTV decoder, characterized in that configured to control the read and write of the second frame memory and the memory unit in accordance with the slow playback mode. The VLD enable signal generator of claim 1, wherein the memory controller is configured to generate an enable signal of the VLD unit in a frame clock period in a slow play mode, and a VLD enable signal and a frame clock from the VLD enable signal generator. And a frame memory read / write signal generator for controlling the first and second frame memory reads and writes, and a memory for generating a write signal of the memory unit according to a VLD enable signal input from the VLD enable signal generator. And a select signal generator for generating a select signal of a multiplexer according to a VLD enable signal from the VLD enable signal generator. 3. The frame memory read / write signal generator of claim 2, wherein the frame memory read / write signal generator comprises a first end gate through which a VLD enable signal and I or P frame data are input, and a clock end when an output of the first end gate is input to a toggle input terminal. The T flip-flop to which the frame clock is input, the second end gate to which the VLD enable signal and the B frame data are input, and the output of the first end gate and the T flip-flop are input to write the light signal of the first frame memory. A third end gate generating a second gate, a fourth end gate outputting the output of the T flip-flop and an output of the first end gate to generate a write signal of a second frame memory, and the T flip-flop A first OR gate for generating a read signal of a first frame memory by receiving an inverted signal and an output of the second end gate, and an output of the second end gate and the T Slow reproduction apparatus of the HDTV decoder, characterized by consisting of a second Iowa gate the output of the lip-flop are input for generating the read signal in the second frame memory. A first step of determining a VLD enable signal high picture coding type, a second step of controlling read / write and multiplexing of the first and second frame memories and memory units according to the picture coding type, and a VLD enable A third step of preventing writing to the first and second frame memories when the signal is low and controlling multiplexing of the read / write and multiplexers of the first and second frame memories and the memory unit according to the toggle signal. How to play slow. 5. The method of claim 4, wherein the second step prohibits writing of the memory unit and the first step of reversely reading and writing the first and second frame memories according to the toggle signal when the picture coding type is I or P picture. A second step of reading from the frame memory, a third step of turning the selection signal of the multiplexer high and toggling on a frame-by-frame basis, and writing of the first and second frame memories is prohibited when the picture coding type is B picture. And a fifth step of writing to the memory section and reading of the second frame memory, and a sixth step of setting the multiplexer's selection signal to a low level. 5. The method of claim 4, wherein the third step includes a first step of prohibiting writing to the first and second frame memories and reversing reading of the first and second frame memories according to a toggle signal, and writing and writing to the memory section. And a third step of reading a two-frame memory and a third step of selecting a multiplexer's selection signal high.