JPH08214300A - Decoder and mpeg video decoder - Google Patents

Abstract

PURPOSE: To obtain an MPEG video decoder at a low cost. CONSTITUTION: When a switching circuit 5 is switched to the side of a node 5a and a switching circuit 6 is switched to the side of a node 6b, a video output is stored in an area 4a of a display buffer 4. After storing a video output for sixteen lines in the area 4a, the circuit 5 is switched to the side of a node 5b and the circuit 6 is switched to the side of a node 6a. Thereby a video output is stored in an area 4b of the buffer 4. The video output for sixteen lines stored in the area 4a is outputted to a display as a high resolution still picture output through the node 6a of the circuit 6. Said operation is repeated in each video output of sixteen lines. Since one macro block in an MPEG video part is constituted of sixteen lines, a video output for sixteen lines is outputted to the display.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a decoder and MPEG.
(Moving Picture Expert Group) Video decoder.

[0002]

2. Description of the Related Art CDs (Compact Disks) are widely used all over the world as media for providing high-quality music information.
In recent years, not only music information but also multimedia in which image information and audio information are mainly used has been promoted. Various CDs used in multimedia are collectively called a CD family. The CD family includes the CD-DA (CD-Digital Audio) family, which is a so-called music CD, and the CD-RO, which is a so-called data CD.
There are M (CD-Read Only Memory) families. C
The D-ROM family includes CD-IFMV (CD-Interac
tive Full Motion Video) or CD-IDV (CD-Inte
ractive Digital Video) etc. CD-IFMV
Has video CDs and karaoke CDs.

The information handled by multimedia is enormous and diverse, and it is necessary to process such information at high speed in order to put multimedia into practical use. In order to process information at high speed, data compression / decompression technology is essential. Compression of such data
As an extension technology, "MPEG (Moving Picture Expert Gro
up) ”method. This MPEG system is IS
O (International Organization for Standardizatio
n) / IEC (Intarnational Electrotechnical Commiss)
ion) MPEG committee (ISO / IEC JTC1 / SC29 / WG1
It is being standardized by 1). MPEG is composed of three parts. In Part 1, "MPEG System Part" (ISO / IEC IS 11172 Part1: Systems),
A multiplexing structure of video data and audio data and a synchronization method are specified. Part 2, "MPEG Video Part" (ISO / IEC IS
11172Part2: Video) specifies a high-efficiency coding method for video data and a video data format. Part 3, "MPEG Audio Part" (ISO / IE
CIS 11172 Part3: Audio) specifies a high-efficiency encoding method for audio data and an audio data format.

By using the MPEG system, a CD
-Video reproduction is possible even in the ROM family.
Karaoke CD is MP from CD-IFMV format
Only the part relating to the EG method is taken out and only the moving image is reproduced. In addition to video playback, video CDs
A menu playback function called PBC (Play Back Control) that enables a still image playback and a combined expression of still image playback and moving image playback is added. Therefore,
Video CD is compatible with CD-IFMV, CD-I
An FMV player can play a video CD format disc.

At present, MPEG-1, MPEG-, mainly due to the difference in encoding rate.
There are two methods. MPEG-1 is mainly CD-RO
Supports storage media such as M family, MP
EG-2 supports a wide range of applications including MPEG-1.

The video data handled by the MPEG video part relates to a moving image, and the moving image is composed of several tens (for example, 30) frames (screens) per second. The video data is a sequence (Sequenc
e), GOP (Group Of Pictures), pictures, slices (Slices), macroblocks (Macroblocks), and blocks in this order have a hierarchical structure of 6 layers. In MPEG-1, a frame corresponds to a picture. In MPEG-2, frames or fields can be associated with pictures. Two fields make up one frame. A structure in which a frame corresponds to a picture is called a frame structure, and a structure in which a field corresponds to a picture is called a field structure. A data string (bit stream) of video data encoded according to the MPEG video part is called an MPEG video stream.

The MPEG video part also includes a function of displaying a high-definition still image (high-resolution still image, hereinafter abbreviated as high-resolution still image). For example, the currently commercially available video CD player is MPEG-1.
You can use to display high-resolution still images.

FIG. 2 shows a block circuit of a main part of a conventional MPEG video decoder 11 having a high resolution still image display function. The MPEG video decoder 11 includes a bit buffer 12, an MPEG video decode core circuit (hereinafter abbreviated as decode core circuit) 13, and a frame buffer 14.

External device (for example, video CD player)
MPEG video stream transferred from
The video stream will be input to the bit buffer 12. The bit buffer 12 is a FIFO (First-In-F
It is composed of a RAM (Random Access Memory) having an irst-Out) structure and stores a video stream for one line (scan line).

The decode core circuit 13 reads out a video stream for one line from the bit buffer 12. Then, the decode core circuit 13 generates a video output for one line by decoding the video stream according to the MPEG video part, and transfers the video output to the frame buffer 14.

The frame buffer 14 is an R having a FIFO structure.
It is composed of AM and sequentially accumulates the video output transferred from the decode core circuit 13. Here, the bit buffer 12 and the frame buffer 14 are provided separately in one RAM 15. The RAM 15 is externally attached to the decode core circuit 13 composed of one chip. In this way, the bit buffer 12 and the frame buffer 14 are provided in one RAM 15 in order to reduce the number of parts and to make the MPEG video decoder 11
This is for the purpose of cost reduction.

After that, when one frame of video output is accumulated in the frame buffer 14, the accumulated video output is collectively output to a display (not shown) as high-resolution still image output. Then, a high-resolution still image is displayed on the display.

[0013]

The high resolution still image is a standard television format NTSC (Nation).
al Television System Committee, scanning lines: 525 lines and PAL (Phase Alternation by Line, scanning lines: 62)
5) and standardized for NTSC
High Resonance Mode (hereinafter referred to as NTSC High Resonance Mode) and PAL High Resonance Mode (hereinafter referred to as P
It is called AL high resolution mode). NTSC
In the format, one frame is 29.97Hz and the number of pixels is (35
2 × 240), whereas the NTSC high resolution mode format doubles the number of pixels (704 × 480).
On the other hand, in the PAL format, one frame has 25 Hz and the number of pixels is (352 × 288), whereas in the PAL high resolution mode format, the number of pixels is doubled (704 × 57).
6)

By the way, in order to store a video stream for one line, the capacity of the bit buffer 12 is 7-10.
K bytes are required. Further, in order to store the video output for one frame, the capacity of the frame buffer 14 is 123.75.
~ 594 Kbytes are required.

Therefore, in the NTSC high resolution mode, R
The capacity of the AM 15 (= the capacity of the bit buffer 12 + the capacity of the frame buffer 14) is 4 Mbits or less. On the other hand, in the PAL high resolution mode, the RAM 15 needs to have a capacity of at least 5 Mbits.

When a moving image is reproduced by the MPEG system, the capacity of the RAM 15 is 4M in any operation mode.
Less than a bit is sufficient. Therefore, only in the PAL high resolution mode, the capacity of the RAM 15 is additionally required by 1 Mbit. That is, the RAM 15 having a large capacity must be used only for the PAL high resolution mode. Since the price of RAM increases with its capacity, R
As the capacity of the AM 15 increases, the cost of the MPEG video decoder 11 increases.

The present invention has been made to solve the above problems, and an object thereof is to provide a low-cost decoder and an MPEG video decoder.

[0018]

The gist of the invention described in claim 1 is to output the video output for every preset number of lines to the outside as a still image output in the still image mode.

According to a second aspect of the present invention, in the still picture mode, the video output for every preset number of lines is repeatedly output to the outside as a still picture output.
The idea is to generate still image output for frames.

According to the third aspect of the invention, a bit buffer for accumulating an MPEG video stream transferred from the outside, an MPEG video stream read from the bit buffer, and the MPEG video stream is MPE
A decode core circuit that generates a video output by decoding in accordance with the G video part, first and second display buffers that store the video output, and a video output generated from the decode core circuit as a first or The gist of the present invention is to include a control means for outputting the video output read from the second or first display buffer to the outside as a still image output at the same time as inputting to the second display buffer. .

According to a fourth aspect of the invention, a bit buffer for accumulating an MPEG video stream transferred from the outside, an MPEG video stream read from the bit buffer, and the MPEG video stream is MPE
A decode core circuit that generates a video output by decoding in accordance with the G video part, first and second display buffers that store the video output, and a video output generated from the decode core circuit as a first or At the same time as inputting to the second display buffer, the video output read from the second or first display buffer is output to the outside as a still image output, and is output to the first or second display buffer. The gist of the invention is to have a control means for switching the input and output for each preset number of lines.

According to a fifth aspect of the present invention, a bit buffer for accumulating an MPEG video stream for one frame transferred from the outside and an MPEG video stream for one line are read from the bit buffer and the MPE thereof is performed.
A decode core circuit that generates a video output for one line by decoding the G video stream in accordance with the MPEG video part, and first and second displays that accumulate the video output corresponding to a preset number of lines. Buffer and the video output generated from the decoding core circuit are input to the first or second display buffer, and at the same time, the video output read from the second or first display buffer is output as a still image. As a gist of the present invention, there is provided a control means for outputting to the outside and switching the input and output to the first or second display buffer for each of the preset number of lines.

According to a sixth aspect of the present invention, a bit buffer for accumulating an MPEG video stream for one frame transferred from the outside and an MPEG video stream for one line are read from the bit buffer and the MPE thereof is performed.
A decode core circuit that generates a video output for one line by decoding the G video stream in accordance with the MPEG video part, and first and second displays that accumulate the video output corresponding to a preset number of lines. The video output for the predetermined number of lines is alternately switched from the video buffer and the decode core circuit, and the video output is transferred to the first or second display buffer. The switching means and the video output for the predetermined number of lines are alternately switched every time the video output for the predetermined number of lines is read from the switching means and the first or second display buffer, and the video output is output to the outside as a still image output. When the video output generated from the second switching means and the decode core circuit is output to the first display buffer, is it the second display buffer? The read video output is output to the outside, and when the video output generated from the decode core circuit is output to the second display buffer, the video output read from the first display buffer is output to the outside. Thus, the gist of the present invention is to include a switching control means for controlling the first and second switching means.

According to a seventh aspect of the present invention, in the MPEG video decoder according to any one of the third to sixth aspects, the bit buffer and the first and second display buffers are one RAM. This is the gist.

According to an eighth aspect of the invention, in the MPEG video decoder according to any one of the second to seventh aspects, the still image output complies with the NTSC high resonance mode or the PAL high resonance mode. Is the gist.

[0026]

According to the first aspect of the present invention, a storage device for temporarily storing the video output by externally outputting the video output for every preset number of lines as a still image output. The capacity can be reduced. Therefore, since a storage device having a small capacity may be used, the cost of the entire decoder can be reduced.

According to the second aspect of the present invention, the storage device for temporarily storing the video output by outputting the video output for every preset number of lines to the outside as the still image output. The capacity can be reduced. Then, by repeating the video output for every preset number of lines, a still image output for one frame can be generated. Therefore, since it is sufficient to use a storage device having a small capacity, the cost of the entire MPEG video decoder can be reduced.

According to the invention of any one of claims 3 to 6, the input and the output to the first or second display buffer are switched for each preset number of lines, thereby presetting. It is possible to output the video output for each number of lines thus generated to the outside as a still image output. Therefore, the first or second display buffer has only to store the video output for a preset number of lines, and the capacity thereof can be reduced. Therefore, since a display buffer having a small capacity may be used, the cost of the MPEG video decoder as a whole can be reduced.

According to the fifth or sixth aspect of the invention, since the bit buffer stores the MPEG video stream for one frame, its capacity becomes large. However, since the capacities of the first and second display buffers are small, the total capacity of the storage device, which is the total capacity of the bit buffers and the capacities of the first and second display buffers, is small.

According to the sixth aspect of the present invention, by providing the first and second switching means, the number of lines for which the input and the output to the first or second display buffer are set in advance is set. It is possible to reliably perform the operation of switching each time.

According to the seventh aspect of the invention, since the bit buffer and the first and second display buffers can be configured by a single RAM having a small capacity, MPE is possible.
The overall cost of the G video decoder can be significantly reduced.

According to the invention described in claim 8, NTSC
High-resolution still image output or PAL high-resolution still image output can be obtained.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block circuit of a main part of an MPEG video decoder 1 of this embodiment having a high resolution still image display function.

The MPEG video decoder 1 is composed of a bit buffer 2, an MPEG video decode core circuit (hereinafter abbreviated as decode core circuit) 3, a display buffer 4, switching circuits 5, 6, and a timing generation circuit 7.

External device (for example, video CD player)
MPEG video stream transferred from
The video stream will be input to the bit buffer 2. The bit buffer 2 is composed of a RAM having a FIFO structure and stores a video stream for one frame (screen).

The decode core circuit 3 includes a bit buffer 2
To read one line (scan line) of video stream. Then, the decode core circuit 3 decodes the video stream according to the MPEG video part to generate a video output for one line, and transfers the video output to the switching circuit 5.

The switching circuit 5 includes two nodes 5a and 5b. The connection between the nodes 5a and 5b is alternately switched every time 16 lines of video output are transferred. Then, the video output generated by the decode core circuit 3 is transferred to the display buffer 4 via either one of the nodes 5a and 5b.

The display buffer 4 is a RAM having a FIFO structure.
The video output transferred from the decode core circuit 3 via the switching circuit 5 is sequentially accumulated. Here, the bit buffer 2 and the display buffer 4 are one RAM 8
It is provided by dividing the area inside. RAM8 is 1
It is externally attached to the decode core circuit 3 composed of a chip. Thus, the bit buffer 2 and the display buffer 4 are provided in one RAM 8 in order to reduce the number of parts and reduce the cost of the MPEG video decoder 1.

Further, each of the display buffers 4 has 16
It is divided into areas 4a and 4b capable of accumulating video output for lines. When the switching circuit 5 is switched to the node 5a side, the video output is input to the area 4a, and when the switching circuit 5 is switched to the node 5b side, the video output is input to the area 4b.

The video output read from the display buffer 4 is transferred to the switching circuit 6. The switching circuit 6 includes two nodes 6a and 6b. The connection between the nodes 6a and 6b is alternately switched every time 16 lines of video output are transferred. The 16 lines of video output read from the display buffer 4 are collectively output to a display (not shown) as high-resolution still image output via one of the nodes 6a and 6b.
Then, a high-resolution still image is displayed on the display.

Here, when the switching circuit 5 is switched to the node 5a side, the switching circuit 6 is switched to the node 6b side, and when the switching circuit 5 is switched to the node 5b side, the switching circuit 6 is switched to the node 6a side. To be The switching operation of each of the switching circuits 5a and 5b is controlled by the control signal S output from the timing generation circuit 7.

Next, the operation of this embodiment will be described. First,
The switching circuit 5 is switched to the node 5a side, and the switching circuit 6
Are switched to the node 6b side. Then, the video output is accumulated in the area 4a of the display buffer 4.

When 16 lines of video output are accumulated in the area 4a, the switching circuit 5 is switched to the node 5b side and the switching circuit 6 is switched to the node 6a side. Then, the video output is accumulated in the area 4b of the display buffer 4. At this time, 1 accumulated in the area 4a
The video output for 6 lines is output to the display as a high-resolution still image output via the node 6a of the switching circuit 6.

The above operation is repeated for every 16 lines of video output. Here, the video output for 16 lines is output to the display because one macroblock is composed of 16 lines in the MPEG video part.

As described above, according to this embodiment, since the bit buffer 2 stores the video stream for one frame, the capacity of the bit buffer 2 needs to be at least 224 Kbytes. In addition, each area 4a of the display buffer 4,
Since each of 4b stores 16 lines of video output, the display buffer 4 as a whole needs to store 32 (= 16 + 16) lines of video output. for that reason,
The display buffer 4 requires a capacity of at least 33 Kbytes.

Therefore, in this embodiment, R is used not only in the NTSC high resolution mode but also in the PAL high resolution mode.
The capacity of the AM 8 (the capacity of the bit buffer 2 + the capacity of the frame buffer 4) is 4 Mbits or less. M
When the moving image is reproduced by the PEG method, the capacity of the RAM 8 is 4 Mbits or less in any operation mode. That is, according to this embodiment, the capacity of the RAM 8 can be set to 4 Mbits or less for all reproduction including high-resolution still images. Since the price of the RAM increases with its capacity, if the capacity of the RAM 8 can be reduced, the cost of the MPEG video decoder 1 can be reduced.

The above embodiments may be modified as follows, and in that case, the same operation and effect can be obtained. (1) Each area 4a, 4b of the display buffer 4 stores not a video output for 16 lines but a video output for an appropriate number of lines (32, 64, 128, etc.) that is a multiple of 16. Here, the number of lines of video output to be stored in each of the areas 4a and 4b is a multiple of 16 because one macroblock is composed of 16 lines in the MPEG video part.

In this case, the timing generating circuit 7 has the switching circuits 5 and 6 for each of the predetermined number of lines.
Each node 5a, 5b, 6a, 6b of is switched. Also, the higher the number of lines of video output accumulated in each of the areas 4a and 4b, the higher the image quality of high-resolution still images, but
On the other hand, the capacity of the display buffer 4 becomes large.

(2) As an external device, a VTR (Video Tape Recorder), an LD (La
MPs such as ser disk) and DVD (Digital Video Disk)
It is applied to all playback devices for storage media using the EG method. Further, the invention is applied not only to storage media but also to all communication media using the MPEG system.

(3) Not only the MPEG method but also the MPEG method
It is applied to methods derived from the method and methods including the MPEG method. As described above, each embodiment has been described.
The technical ideas other than the claims that can be understood from each embodiment will be described below along with their effects.

(A) The MPEG video decoder according to any one of claims 2 to 8, wherein the set number of lines is a multiple of the number of lines forming a macro block.

By doing so, a highly vivid still image can be displayed. (B) The MPEG video decoder according to claim 7, wherein the RAM has a FIFO structure.

By doing so, writing and reading of the MPEG video stream and the video output can be easily performed. (C) The MPEG video decoder according to claim 7, wherein the RAM has a capacity of 4 Mbits or less.
Video decoder.

In this way, a commercially available external R
AM can be used. By the way, in the present specification, members or names relating to the constitution of the invention are defined as follows.

(A) The control means is composed of switching circuits 5 and 6 and a timing generation circuit 7. (B) The first display buffer is composed of the area 4a of the display buffer 4, and the second display buffer is composed of the area 4b of the display buffer 4.

(C) The first switching means is composed of the switching circuit 5, and the second switching means is composed of the switching circuit 6. (D) The switching control means is composed of the timing generation circuit 7.

(E) The MPEG system is the current MPEG
-1 and 2 as well as methods derived from the MPEG method and methods including the MPEG method are included.

[0058]

As described above in detail, according to the present invention, it is possible to provide a low-cost decoder and an MPEG video decoder.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a main part of one embodiment.

FIG. 2 is a block circuit diagram of a main part of a conventional example.

[Explanation of symbols]

 1 MPEG Video Decoder 2 Bit Buffer 3 MPEG Video Decoding Core Circuit 4 Display Buffer 5, 6 Switching Circuit 7 Timing Generation Circuit 7

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 5/92 H04N 5/92 H

Claims (8)

[Claims] 1. A decoder for outputting a video output for every preset number of lines to the outside as a still image output in the still image mode. 2. An MPEG video decoder for generating a still image output for one frame by repeatedly outputting a video output for every preset number of lines to the outside as a still image output in the still image mode. 3. A bit buffer for accumulating an MPEG video stream transferred from the outside, a MPEG video stream is read from the bit buffer, and the MPEG video stream is decoded according to the MPEG video part to generate a video output. A decoding core circuit for storing the video output, first and second display buffers for accumulating the video output, and inputting the video output generated from the decoding core circuit to the first or second display buffer and at the same time for the second display buffer.
Alternatively, an MPEG video decoder having a control means for outputting the video output read from the first display buffer to the outside as a still image output. 4. A bit buffer for accumulating an MPEG video stream transferred from the outside, a MPEG video stream is read from the bit buffer, and the MPEG video stream is decoded according to the MPEG video part to generate a video output. A decoding core circuit for storing the video output, first and second display buffers for accumulating the video output, and inputting the video output generated from the decoding core circuit to the first or second display buffer and at the same time for the second display buffer.
Alternatively, the video output read from the first display buffer is externally output as a still image output, and the first or second
An MPEG video decoder having a control means for switching input and output to the display buffer for each of the preset line numbers. 5. A bit buffer for accumulating an MPEG video stream for one frame transferred from the outside, an MPEG video stream for one line is read from the bit buffer, and the MPEG video stream is MP-processed.
A decode core circuit that generates a video output for one line by decoding in accordance with the EG video part; first and second display buffers that store a video output corresponding to a preset number of lines; At the same time as inputting the video output generated from the decode core circuit to the first or second display buffer,
Alternatively, the video output read from the first display buffer is externally output as a still image output, and the first or second
MPE including control means for switching input and output to the display buffer for each of the preset number of lines
G video decoder. 6. A bit buffer for accumulating an MPEG video stream for one frame transferred from the outside, an MPEG video stream for one line is read from the bit buffer, and the MPEG video stream is MP-processed.
A decode core circuit that generates a video output for one line by decoding in accordance with the EG video part; first and second display buffers that store a video output corresponding to a preset number of lines; Each time the video output for the predetermined number of lines is transferred from the decode core circuit, it is switched alternately,
First switching means for transferring the video output to the first or second display buffer, and the video output for the predetermined number of lines are read from the first or second display buffer. Second switching means for alternately switching the video output to the outside as a still image output, and the second output means when the video output generated from the decoding core circuit is output to the first display buffer. When the video output read from the display buffer is output to the outside and the video output generated from the decode core circuit is output to the second display buffer, the video output read from the first display buffer To be output to the outside,
An MPEG video decoder provided with a switching control means for controlling the first and second switching means. 7. M according to any one of claims 3 to 6.
The PEG video decoder, wherein the bit buffer and the first and second display buffers are one RAM. 8. M according to any one of claims 2 to 7.
In the PEG video decoder, the still image output is NT
An MPEG video decoder that complies with SC high resonance mode or PAL high resonance mode.