JPH04323831A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04323831A JPH04323831A JP9221991A JP9221991A JPH04323831A JP H04323831 A JPH04323831 A JP H04323831A JP 9221991 A JP9221991 A JP 9221991A JP 9221991 A JP9221991 A JP 9221991A JP H04323831 A JPH04323831 A JP H04323831A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- stress
- film
- melting point
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 13
- 239000010937 tungsten Substances 0.000 claims abstract description 13
- 230000007935 neutral effect Effects 0.000 claims abstract description 8
- 238000002844 melting Methods 0.000 claims description 18
- 230000008018 melting Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 3
- 150000002739 metals Chemical class 0.000 claims 1
- 230000004927 fusion Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 229910018125 Al-Si Inorganic materials 0.000 description 7
- 229910018520 Al—Si Inorganic materials 0.000 description 7
- 229910018594 Si-Cu Inorganic materials 0.000 description 7
- 229910008465 Si—Cu Inorganic materials 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910018523 Al—S Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体装置において高
融点材料を使用した配線部の形成方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming wiring portions using high melting point materials in semiconductor devices.
【０００２】0002
【従来の技術】これまで半導体素子の配線材料としてＡ
ｌ−Ｓｉ，Ａｌ−Ｓｉ−Ｃｕ合金単層が用いられてきた
。しかし配線の微細化に伴い信頼性を劣化させる問題、
すなわち電流ストレスで不良を招くエレクトロマイグレ
ーション、膜ストレスによるストレスマイグレーション
が発生してきた。従って、半導体素子の微細化による素
子の性能確保が実現不可能となる。これに対しＡｌ−Ｓ
ｉ，Ａｌ−Ｓｉ−Ｃｕ合金と高融点材料との積層構造配
線を用いることによりＡｌ−Ｓｉ，Ａｌ−Ｓｉ−Ｃｕ単
層配線よりも信頼性を向上させる方法がある。下層高融
点材料としてはＴｉＷ、ＴｉＮ、ＷＳｉｘ等が用いられ
ている。また高融点単層配線で信頼性を向上させる方法
がある。[Prior Art] Until now, A
l-Si, Al-Si-Cu alloy monolayers have been used. However, as wiring becomes finer, reliability deteriorates.
In other words, electromigration that causes defects due to current stress and stress migration due to membrane stress have occurred. Therefore, it becomes impossible to ensure the performance of semiconductor elements by miniaturizing them. On the other hand, Al-S
There is a method of improving reliability compared to single layer wiring of Al-Si or Al-Si-Cu by using a layered wiring structure of an Al-Si-Cu alloy and a high melting point material. TiW, TiN, WSix, etc. are used as the lower layer high melting point material. There is also a method to improve reliability using a high melting point single layer wiring.
【０００３】0003
【発明が解決しようとする課題】しかし以上述べた方法
であっても、積層構造における上層Ａｌ−Ｓｉ，Ａｌ−
Ｓｉ−Ｃｕ配線が断線しやすいことには変わりない。上
層Ａｌ−Ｓｉ，Ａｌ−Ｓｉ−Ｃｕ合金が断線すると下層
高融点配線に電流が流れる。一般に下層高融点配線に用
いられる材料は抵抗が高い。従って電流が流れる時に発
生するジュール熱が大きく溶断する。さらに、Ａｌとの
反応を起こしやすく相互拡散あるいは化合物の生成等に
よる抵抗増大が発生する。従ってＡｌ−Ｓｉ，Ａｌ−Ｓ
ｉ−Ｃｕ合金と高融点材料との積層構造配線であっても
、Ａｌ−Ｓｉ，Ａｌ−Ｓｉ−Ｃｕ合金単層配線よりは信
頼性は向上するものの、根本的な配線の信頼性を向上さ
せる方法ではない。また、高融点単層配線においてはタ
ングステンが一般的であるが、通常スパッタ法で形成し
た場合、圧縮応力膜となりその後の熱処理によりシリサ
イド化が生じ抵抗増加が生じる。[Problems to be Solved by the Invention] However, even with the method described above, the upper layer Al-Si, Al-
There is no change in the fact that Si-Cu wiring is easily disconnected. When the upper layer Al-Si or Al-Si-Cu alloy is disconnected, current flows to the lower layer high melting point wiring. Generally, the materials used for the lower layer high melting point wiring have high resistance. Therefore, the Joule heat generated when current flows causes a large amount of melting. Furthermore, it tends to react with Al, resulting in an increase in resistance due to mutual diffusion or the formation of compounds. Therefore, Al-Si, Al-S
Even if the wiring has a laminated structure of i-Cu alloy and high melting point material, the reliability will be better than single layer wiring of Al-Si or Al-Si-Cu alloy, but the fundamental reliability of the wiring will be improved. Not the method. Furthermore, tungsten is commonly used in high-melting point single-layer interconnects, but when formed by normal sputtering, it becomes a compressive stress film and becomes silicided during subsequent heat treatment, resulting in an increase in resistance.
【０００４】この方法は以上述べたＡｌ−Ｓｉ，Ａｌ−
Ｓｉ−Ｃｕ合金単層配線の断線とＡｌ−Ｓｉ，Ａｌ−Ｓ
ｉ−Ｃｕ合金と高融点材料との積層構造配線における断
線、溶断、抵抗増大の問題を除去するため、タングステ
ン膜のストレスを制御して堆積し、配線を形成すること
によりシリサイド化が生じず低抵抗で高信頼性の配線を
提供することを目的とする。[0004] This method is applicable to the above-mentioned Al-Si, Al-
Disconnection of Si-Cu alloy single layer wiring and Al-Si, Al-S
In order to eliminate the problems of disconnection, melting, and increased resistance in laminated interconnects made of i-Cu alloy and high-melting point materials, the stress of the tungsten film is controlled and deposited to form interconnects, thereby reducing silicidation. The purpose is to provide highly reliable wiring using resistors.
【０００５】[0005]
【課題を解決するための手段】この発明は前述の課題解
決のため、半導体素子の配線形成方法において、スパッ
タ条件により応力制御を行い、引張り応力とニュートラ
ル応力の高融点金属膜を積層形成するようにしたもので
ある。[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a method for forming interconnections of semiconductor devices in which stress is controlled by sputtering conditions and high melting point metal films with tensile stress and neutral stress are laminated. This is what I did.
【０００６】[0006]
【作用】本発明は前述のように、スパッタ条件により応
力を制御し、下地材料とシリサイド化反応の生じない引
張り応力の高融点金属膜（例えばタングステン）と、そ
の膜より低抵抗のニュートラル応力の高融点金属膜との
積層構造の配線としたので、低抵抗で高信頼性の配線を
実現できる。[Operation] As described above, the present invention controls stress by sputtering conditions, and combines a high melting point metal film (such as tungsten) with a tensile stress that does not cause a silicidation reaction with the underlying material and a neutral stress film with a lower resistance than that film. Since the wiring has a laminated structure with a high melting point metal film, it is possible to realize wiring with low resistance and high reliability.
【０００７】[0007]
【実施例】図２はスパッタ条件により応力を制御したタ
ングステン膜の応力と比抵抗との関係を示す図である。
この図から解るように、ニュートラル（Ｘ軸の０点）で
比抵抗は最小値を示し引張り応力、圧縮応力が大きくな
るにつれて比抵抗は大きくなる。本発明は、このスパッ
タ条件による応力制御を利用して配線を形成するもので
あり、その実施例の製造工程を図１に示し、以下に説明
する。EXAMPLE FIG. 2 is a diagram showing the relationship between stress and specific resistance of a tungsten film whose stress was controlled by sputtering conditions. As can be seen from this figure, the specific resistance has a minimum value at neutral (0 point on the X axis), and increases as the tensile stress and compressive stress increase. The present invention forms wiring by utilizing stress control based on the sputtering conditions, and the manufacturing process of an embodiment thereof is shown in FIG. 1 and will be described below.
【０００８】まず、図１（ａ）に示すように、ＩＣ基板
２１上に形成された絶縁膜２２上に、スパッタ法により
ＤＣパワー１ｋＷ、アルゴン圧１５ｍＴｏｒｒの条件で
下地絶縁膜２２とシリサイド化反応を生じない引張り応
力のタングステン膜２３を約１００ｎｍ推積させる。続
いて図１（ｂ）のように、ＤＣパワー２ｋＷ、アルゴン
圧１７．５ｍＴｏｏｒの条件で比抵抗が引張り応力タン
グステン膜より小さい前記ニュートラル応力のタングス
テン膜２４を約２００ｎｍ堆積させる。その後図１（ｃ
）のように、ホトリソグラフィ・エッチング技術を利用
して配線２５を形成する。最後に保護膜２６を形成して
完成する（図１（ｄ））。First, as shown in FIG. 1A, a silicidation reaction is performed on an insulating film 22 formed on an IC substrate 21 with a base insulating film 22 by sputtering under conditions of a DC power of 1 kW and an argon pressure of 15 mTorr. The tungsten film 23 with a tensile stress that does not cause any stress is estimated to be approximately 100 nm thick. Subsequently, as shown in FIG. 1B, about 200 nm of the neutral stress tungsten film 24 having a resistivity smaller than the tensile stress tungsten film is deposited under the conditions of DC power of 2 kW and argon pressure of 17.5 mToor. After that, Figure 1(c)
), the wiring 25 is formed using photolithography and etching technology. Finally, a protective film 26 is formed to complete the process (FIG. 1(d)).
【０００９】[0009]
【発明の効果】以上のようにこの発明の製造方法によれ
ば、スパッタ条件により応力を制御し、下地材料とシリ
サイド化反応の生じない引張り応力のタングステンと引
張り応力のタングステンより低抵抗のニュートラル応力
のタングステンとの積層高融点配線としたので、低抵抗
で断線、溶断が発生しにくい高信頼性の配線の実現が期
待できる。As described above, according to the manufacturing method of the present invention, stress can be controlled by sputtering conditions, and tungsten with tensile stress that does not cause a silicidation reaction with the underlying material and neutral stress with a lower resistance than tungsten with tensile stress can be produced. Since this layered high-melting-point wiring is made with tungsten, it is expected that high-reliability wiring with low resistance and less chance of disconnection or melting will occur.
【図１】本発明の実施例の製造工程断面図[Fig. 1] Cross-sectional view of the manufacturing process of an embodiment of the present invention
【図２】Ｗ膜
の比抵抗−応力関係図[Figure 2] Specific resistance-stress relationship diagram of W film
２１ ＩＣ基板 ２２ 絶縁膜 ２３ 引張り応力Ｗ膜 ２４ ニュートラル応力Ｗ膜 ２５ 配線 ２６ 保護膜 21 IC board 22 Insulating film 23 Tensile stress W film 24 Neutral stress W film 25 Wiring 26 Protective film
Claims (2)
ａ）半導体基板上に、下地材料とシリサイド化を生じな
い引張り応力を有する第１の高融点金属膜を堆積する工
程と、（ｂ）前記第１の高融点金属膜の上に該膜より低
抵抗のニュートラル応力を有する第２の高融点金属膜を
堆積する工程と、を含み配線部を形成することを特徴と
する半導体装置の製造方法。[Claim 1] When forming wiring of a semiconductor device, (
a) depositing on the semiconductor substrate a first high melting point metal film having a tensile stress that does not cause silicidation with the underlying material; 1. A method of manufacturing a semiconductor device, comprising the step of depositing a second high melting point metal film having a resistance neutral stress to form a wiring portion.
において前記第１及び第２の高融点金属をタングステン
とし、その堆積方法をスパッタ法としたことを特徴とす
る半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second high melting point metals are tungsten and the deposition method thereof is a sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9221991A JPH04323831A (en) | 1991-04-23 | 1991-04-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9221991A JPH04323831A (en) | 1991-04-23 | 1991-04-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04323831A true JPH04323831A (en) | 1992-11-13 |
Family
ID=14048338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9221991A Pending JPH04323831A (en) | 1991-04-23 | 1991-04-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04323831A (en) |
-
1991
- 1991-04-23 JP JP9221991A patent/JPH04323831A/en active Pending
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