JPH0432298A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JPH0432298A
JPH0432298A JP2140535A JP14053590A JPH0432298A JP H0432298 A JPH0432298 A JP H0432298A JP 2140535 A JP2140535 A JP 2140535A JP 14053590 A JP14053590 A JP 14053590A JP H0432298 A JPH0432298 A JP H0432298A
Authority
JP
Japan
Prior art keywords
circuit pattern
layer
printed wiring
inner layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2140535A
Other languages
Japanese (ja)
Inventor
Koichiro Shibayama
耕一郎 柴山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2140535A priority Critical patent/JPH0432298A/en
Publication of JPH0432298A publication Critical patent/JPH0432298A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To extensively avoid the break of a fine circuit pattern, etc., by thermal history, temperature change in use circumstance, etc., by constituting an inner layer circuit pattern and a interlayer conductor out of a conductive resin composition, which contains metallic powder, and besides constituting at least one layer of the inner circuit pattern out of a metallic foil. CONSTITUTION:A copper foil 12mum thick is stuck together to a polysulfone resin film approximately 0.05mm thick, and a required hole for connection is bored, and then a circuit pattern is formed on one side or both sides by selective etching. Next, an inner layer circuit pattern element plate is prepared, in which an interlayer connecting conductor 5 is made by charging conductive paste, containing dispersed copper powder with the polysulfone resin as a binder ingredient, in the hole for connection by screen printing method. Plural sheets of inner layer circuit pattern element plates prepared are combined with said second circuit pattern element plates, and are aligned and a put on the other. The fellow surfaces facing each other are fused together and united, and also the interlayer connecting conductors 5 corresponding to each other are filled up and united.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は多層プリント配線板に係り、特に実装回路装置
用の改良された多層プリント配線板に関する。
DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (Industrial Field of Application) The present invention relates to multilayer printed wiring boards, and more particularly to improved multilayer printed wiring boards for packaged circuit devices.

(従来の技術) 配線回路の小形化ないし回路部分のフンパクト化などを
目的にして、多層プリント配線板を基体とし、これに所
要の電子部品を搭載・実装し、た構成の実装回路装置が
広く実用に供されている。
(Prior art) For the purpose of downsizing wiring circuits or making circuit parts more compact, mounted circuit devices with a multilayer printed wiring board as a base, on which required electronic components are mounted and mounted, have been widely used. It is put into practical use.

しかして、上記実装回路用多層プリント配線板の−形式
として、合成樹脂系の多層プリント配線板がある。すな
わち、第1の方式として、絶縁紙やガラスクロスなどを
基材どした樹脂含浸型の絶縁体層面に貼むした金属箔の
選択エツチングにより所要の回路パターンを形成した内
層回路パターン素板と、この内層回路パターン素板に介
在してこれらを一体化するプリプレグ硬化層と、同じく
プリプレグ硬化層を介して一体化された金属箔の選択エ
ツチングによって形成された最外層回路パターン素板と
を具備して成る多層プリント配線板が挙げられる。第2
の方式としては、前記内外各層の回路パターンを、たと
えば銀、銅、金、ニッケルなどの金属粉末とバインダー
としての合成樹脂を含む導電性組成物で構成した多層プ
リント配線板が挙げられる。なお、上記構成の多層プリ
ント配線板においては、内層回路パターン間、内層回路
パターンー外層回路パターン間あるいは外層回路パター
ン間についてスルホールやピアホールなどにより所要の
電気的な接続が行われている。
As a type of the above-mentioned multilayer printed wiring board for mounted circuits, there is a synthetic resin multilayer printed wiring board. That is, as a first method, an inner layer circuit pattern blank is formed with a desired circuit pattern by selective etching of a metal foil pasted on the surface of a resin-impregnated insulator layer made of insulating paper or glass cloth as a base material; A prepreg hardened layer that interposes on this inner layer circuit pattern blank plate and integrates them, and an outermost layer circuit pattern blank formed by selective etching of metal foil that is also integrated via the prepreg hardened layer. For example, a multilayer printed wiring board consisting of Second
Examples of this method include a multilayer printed wiring board in which the circuit patterns of the inner and outer layers are made of a conductive composition containing a metal powder such as silver, copper, gold, or nickel, and a synthetic resin as a binder. In the multilayer printed wiring board having the above configuration, necessary electrical connections are made between inner layer circuit patterns, between inner layer circuit patterns and outer layer circuit patterns, or between outer layer circuit patterns using through holes, peer holes, or the like.

(発明が解決しようとする課題) しかし、上記構成の合成樹脂系多層プリント配線板には
、実用上次のような不都合が認められる。先ず第1の方
式の場合、つまり各層の回路パターンが、金属箔をベー
スにして形成されている多層プリント配線板の場合は、
回路パターン層間の電気的な接続層や回路パターン層と
マトリックスを成す合成樹脂系(絶縁体)との物性、た
とえば熱膨脹率などが大きく相違するため、熱履歴、応
力作用あるいは冷熱サイクルによって、微細な回路パタ
ーンが切断などすることがしばしばあり、所要の回路機
能が損われるなど信頼性の点に問題がある。また、第2
の方式の場合、つまり内層回路パターンも含めて導電体
領域全体を、いわゆる導電性ペーストで形成した多層プ
リント配線板の場合は、その回路形成方法が、スクリー
ン印刷によるため、パターン幅やパターン間隔(ギャッ
プ幅)の微細化に大きな制約があり、高い配線密度を得
ることができない。
(Problems to be Solved by the Invention) However, the synthetic resin multilayer printed wiring board having the above structure has the following practical disadvantages. First, in the case of the first method, that is, in the case of a multilayer printed wiring board in which the circuit pattern of each layer is formed based on metal foil,
Because the electrical connection layer between the circuit pattern layers and the physical properties of the circuit pattern layer and the synthetic resin (insulator) forming the matrix, such as coefficient of thermal expansion, are significantly different, thermal history, stress action, or cooling/heating cycles may cause microscopic differences. There are problems with reliability, such as circuit patterns often being cut, and required circuit functions being impaired. Also, the second
In the case of the above method, that is, in the case of a multilayer printed wiring board in which the entire conductor region including the inner layer circuit pattern is formed with a so-called conductive paste, the circuit formation method is screen printing, so the pattern width and pattern spacing ( There are major restrictions on miniaturization (gap width), making it impossible to obtain high wiring density.

本発明は上記事情に対処してなされたもので、配線密度
の高い多層プリント配線板の提供を目的とする。
The present invention was made in response to the above-mentioned circumstances, and an object of the present invention is to provide a multilayer printed wiring board with high wiring density.

[発明の構成] (課題を解決するための手段) 本発明は、電子部品を搭載・半田付けする最外層回路パ
ターン、内層回路パターンおよび回路パターン層間を電
気的に接続する層間導体を備えた多層プリント配線板に
おいて、 前記内層回路パターンおよび層間導体を金属粉末含有の
導電性樹脂組成物で構成しかつ、内層回路パターンの少
くとも一層を金属箔にて構成して成ることを特徴とする
[Structure of the Invention] (Means for Solving the Problems) The present invention provides a multilayer circuit pattern that includes an outermost layer circuit pattern on which electronic components are mounted and soldered, an inner layer circuit pattern, and an interlayer conductor that electrically connects the circuit pattern layers. The printed wiring board is characterized in that the inner layer circuit pattern and the interlayer conductor are made of a conductive resin composition containing metal powder, and at least one layer of the inner layer circuit pattern is made of metal foil.

(作 用) 上記構成によれば、回路パターン層間の電気的な接続層
や一部の回路パターン層とマトリックスを成す合成樹脂
系(絶縁体)との物性、たとえば熱膨脹率など近似して
いるため、熱履歴や使用環境の温度変化などによる微細
な回路パターンなどの破断ち全面的に回避し得る。また
、内層回路パターンの少くとも一層(一部の内層回路パ
ターン)は、金属箔をベースとしエツチング法によって
形成されているため、高い配線密度を達成し得る。
(Function) According to the above configuration, the physical properties of the electrical connection layer between the circuit pattern layers and some of the circuit pattern layers and the synthetic resin system (insulator) forming the matrix are similar, such as the coefficient of thermal expansion. , breakage of minute circuit patterns due to thermal history or temperature changes in the usage environment can be completely avoided. Moreover, since at least one layer of the inner layer circuit pattern (a part of the inner layer circuit pattern) is formed by etching based on metal foil, high wiring density can be achieved.

(実施例) 以下第1図を参照して本発明の詳細な説明する。第1図
は本発明に係る多層プリント配線板の構成例を断面的に
示したもので、1はたとえばポリスルホン樹脂のような
耐熱性熱可塑性樹脂層、2は前記耐熱性熱可塑性樹脂層
1中に多層的にかつ、互いに電気的に絶縁されて配設さ
れた内層回路パターン層である。しかして、この内層回
路パターン層2の一部(一部の層)は、金属油をベース
とし選択的なエツチングで形成されたものである。また
、3は所要の電子部品4のマウントやリードなど半田付
けするパッド部を備えたを外層回路パターン層で、前記
内層回路パターン層2の一部とともに合成樹脂をバイン
ダー成分とする導電性ペーストで形成されている。5は
前記内層回路パターン層2間、内層回路パターン層2−
外層回路パターン層3間あるいは外層回路パターン層3
間についてスルホールやピアホールなどにより、所要の
電気的な接続を行ういわゆる合成樹脂をバインダー成分
とする導電性ペーストから成る層間接続導体部である。
(Example) The present invention will be described in detail below with reference to FIG. FIG. 1 shows a cross-sectional view of an example of the structure of a multilayer printed wiring board according to the present invention, in which 1 is a heat-resistant thermoplastic resin layer such as polysulfone resin, and 2 is a layer of heat-resistant thermoplastic resin in the heat-resistant thermoplastic resin layer 1. This is an inner circuit pattern layer arranged in multiple layers and electrically insulated from each other. A portion (some layers) of this inner circuit pattern layer 2 is formed by selective etching using metal oil as a base. Further, 3 is an outer circuit pattern layer having pads for soldering such as mounts and leads of the necessary electronic components 4, and is made of a conductive paste containing a synthetic resin as a binder component together with a part of the inner circuit pattern layer 2. It is formed. 5 is between the inner circuit pattern layers 2 and 2-
Between outer circuit pattern layers 3 or outer circuit pattern layers 3
This is an interlayer connection conductor section made of a conductive paste containing a so-called synthetic resin as a binder component, which performs the required electrical connection by using through holes or pier holes between the layers.

しかして、上記構成の本発明に係る多層プリント配線板
は、次のようにして容易に製造し得る。
Therefore, the multilayer printed wiring board according to the present invention having the above structure can be easily manufactured as follows.

たとえば、厚さ 0.051程度のポリスルホン樹脂フ
ィルムに厚さ12μの銅箔を貼り合せ、所要の接続用孔
を穿設するとともに、選択エツチングによってその片面
もしくは両面に回路パターンを形成する。次いで、たと
えばポリスルホン樹脂をバインダー成分とし銅粉末を分
散・含有する導電性ペーストをスクリーン印刷法により
、前記接続用孔内に充填し層間接続導体部5を形成した
内層回路パターン素板を用意する。一方、同じく厚さ 
o、05膳履程度のポリスルホン樹脂フィルムに所要の
接続用孔を穿設するとともに、たとえばポリスルホン樹
脂をバインダー成分と15銅粉末を分散・含有する導電
性ペーストをスクリーン印刷法により、所要の回路パタ
ーンおよび層間接続導体部5を形成した第2の回路パタ
ーン素板を用意する。
For example, a copper foil with a thickness of 12 μm is bonded to a polysulfone resin film with a thickness of about 0.051 mm, the required connection holes are bored, and a circuit pattern is formed on one or both sides of the film by selective etching. Next, a conductive paste containing polysulfone resin as a binder component and copper powder dispersed therein is filled into the connection holes by a screen printing method to form an interlayer connection conductor portion 5, thereby preparing an inner circuit pattern blank. On the other hand, the thickness
o. A required connection hole is made in a polysulfone resin film of about 0.05 mm, and a conductive paste containing polysulfone resin as a binder component and 15 copper powder dispersed therein is printed using a screen printing method to form the required circuit pattern. Then, a second circuit pattern blank plate on which interlayer connection conductor portions 5 are formed is prepared.

しかる後、上記用意した内層回路パターン素板複数枚を
、前記第2の回路パターン素板と組み合せ、位置合せ1
7て重ね合ぜる。この重ね合せにおいて、少くとも外側
に第2の回路パターン素板を位置させるが、内層におい
ては内層回路パターン素板と第2の回路パターン素板と
が交互に配置されてもよいし、両回路パターン素板ごと
に配置した構成としてもよい。
After that, the plurality of inner layer circuit pattern blank plates prepared above are combined with the second circuit pattern blank plate, and alignment 1 is performed.
7 and overlap. In this superposition, the second circuit pattern blank plate is positioned at least on the outside, but in the inner layer, the inner layer circuit pattern blank plate and the second circuit pattern blank plate may be arranged alternately, or both circuit pattern blank plates may be arranged alternately. It is also possible to have a configuration in which they are arranged for each pattern blank.

上記位置合せして重ねた後、加熱・加圧成形処理を施し
、前記重ね合せられたポリスルホン樹脂フィルムの互い
に対接する面同士を溶着一体化させるとともに、互いに
対応する層間接続導体部5を充填一体化させることによ
り、所望の多層プリント配線板を得ることができる。
After the above-mentioned alignment and stacking, heating and pressure molding processing is performed to weld and integrate the mutually opposing surfaces of the stacked polysulfone resin films, and the corresponding interlayer connection conductor portions 5 are filled and integrated. By this, a desired multilayer printed wiring board can be obtained.

このようにして構成し得る本発明に係る多層プリント配
線板、たとえばIOX lee膳、厚さ 0.5腸■、
回路パターン4層構成で、内層回路パターン層間同士お
よび内層回路パターン層−外層回路パターン層間の層間
接続導体部500箇所、貫通接続導体部100箇所を有
する多層プリント配線板(実施例)と、前記従来例の第
1の方式で絶縁層をガラスクロス−エポキシ樹脂系とし
て構成された同一構成を採った多層プリント配線板(比
較例)とについて、熱衝撃テストおよび曲げテストをそ
れぞれ行ったところ次のごとくであった。
A multilayer printed wiring board according to the present invention that can be constructed in this manner, for example, IOX lee board, thickness 0.5 mm,
A multilayer printed wiring board (embodiment) having a four-layer circuit pattern structure and having 500 interlayer connection conductor parts between the inner circuit pattern layers and between the inner circuit pattern layer and the outer circuit pattern layer, and 100 through connection conductor parts, and the conventional A thermal shock test and a bending test were conducted on a multilayer printed wiring board (comparative example) with the same structure in which the insulating layer was made of glass cloth and epoxy resin based on the first method of the example, and the following results were obtained. Met.

実施例の場合。For example.

熱衝撃テスト 回路を成す導体層に異常なし、曲げテス
ト  回路を成す導体層に異常なし、比較例の場合。
Thermal shock test: No abnormality in the conductor layer forming the circuit. Bending test: No abnormality in the conductor layer forming the circuit. Comparative example.

熱衝撃テスト 回路を成す導体層にオープンが多発し測
定不能、 曲げテスト  曲げ回数1回で回路を成す導体層にオー
ブン発生、 なお、熱衝撃テストは、−60℃30分、+125℃3
0分を1サイクルとして500サイクル繰り返した場合
であり、また曲げテストは、曲げ率20%として100
0回繰り返した場合である。
Thermal shock test: The conductor layer that forms the circuit has many opens, making measurement impossible. Bending test: After one bend, the conductor layer that forms the circuit generates an oven. Thermal shock test is conducted at -60℃ for 30 minutes and +125℃ for 30 minutes.
This is the case where 500 cycles are repeated with 0 minutes as one cycle, and the bending test is 100 cycles with a bending rate of 20%.
This is the case where it is repeated 0 times.

上記では多層プリント配線板の絶縁体層をポリスルホン
樹脂で構成したが、たとえばポリフェニレンサルファイ
ド樹脂、ポリエーテル樹脂、ポリエーテルイミド樹脂ポ
リエーテルエーテルケトン樹脂など他の熱可塑性樹脂や
たとえば絶縁紙ないし絶縁クロス類を基材としたもので
もよい。
In the above example, the insulating layer of the multilayer printed wiring board is made of polysulfone resin, but other thermoplastic resins such as polyphenylene sulfide resin, polyether resin, polyetherimide resin, polyether ether ketone resin, etc., or insulating paper or insulating cloth may be used. It may be based on.

また、回路パターン層間の電気的な接続導体部および内
層回路パターン層の形成も、前記例示の導電性ペースト
に限らず、合成樹脂をバインダーとした他の導電性ペー
ストで構成してもよい。
Further, the formation of the electrical connection conductor portion between the circuit pattern layers and the inner circuit pattern layer is not limited to the above-mentioned conductive paste, but may be formed using another conductive paste using a synthetic resin as a binder.

[発明の効果] 上記本発明によれば、回路パターン層間の電気的な接続
導体部や回路パターン層とマトリックスを成す合成樹脂
系(絶縁体)との物性が近似しているため、熱履歴や使
用環境の温度変化などによって、微細な回路パターンな
どが破断することも全面的に回避され、所要の回路機能
を常な保持し得る。しかも、内層回路パターンの少くと
も一層(一部の内層回路パターン層)は、金属箔をベー
スとして形成されているため、高い配線密度を成し得る
。かくして、本発明に係る多層プリント配線板は、機能
性や信頼性の高い実装回路装置の構成に適するものとい
える。
[Effects of the Invention] According to the present invention, the electrical connection conductor between the circuit pattern layers and the physical properties of the circuit pattern layer and the synthetic resin system (insulator) forming the matrix are similar, so thermal history and Breakage of minute circuit patterns due to temperature changes in the usage environment is completely avoided, and the required circuit functions can be maintained at all times. Moreover, since at least one layer of the inner circuit pattern (a part of the inner circuit pattern layer) is formed using metal foil as a base, high wiring density can be achieved. Thus, it can be said that the multilayer printed wiring board according to the present invention is suitable for constructing a mounted circuit device with high functionality and reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る多層プリント配線板の構成例を示
す断面図である。 1・・・・・・耐熱性熱可塑性樹脂層 2・・・・・・内層回路パターン層 3・・・・・・最外層回路パターン層 4・・・・・・電子部品 5・・・・・・回路パターン層間接続導体部出願人  
   株式会社 東芝
FIG. 1 is a sectional view showing an example of the structure of a multilayer printed wiring board according to the present invention. 1...Heat-resistant thermoplastic resin layer 2...Inner circuit pattern layer 3...Outermost circuit pattern layer 4...Electronic component 5... ...Circuit pattern interlayer connection conductor section applicant
Toshiba Corporation

Claims (1)

【特許請求の範囲】 電子部品を搭載・半田付けする最外層回路パターン、内
層回路パターンおよび回路パターン層間を電気的に接続
する層間導体を備えた多層プリント配線板において、 前記内層回路パターンおよび層間導体を金属粉末含有の
導電性樹脂組成物で構成しかつ、内層回路パターンの少
くとも一層を金属箔にて構成して成ることを特徴とする
多層プリント配線板。
[Scope of Claims] A multilayer printed wiring board comprising an outermost layer circuit pattern on which electronic components are mounted and soldered, an inner layer circuit pattern, and an interlayer conductor that electrically connects the circuit pattern layers, the inner layer circuit pattern and the interlayer conductor 1. A multilayer printed wiring board, comprising: a conductive resin composition containing metal powder; and at least one layer of an inner layer circuit pattern is made of metal foil.
JP2140535A 1990-05-29 1990-05-29 Multilayer printed wiring board Pending JPH0432298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2140535A JPH0432298A (en) 1990-05-29 1990-05-29 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2140535A JPH0432298A (en) 1990-05-29 1990-05-29 Multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH0432298A true JPH0432298A (en) 1992-02-04

Family

ID=15270933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2140535A Pending JPH0432298A (en) 1990-05-29 1990-05-29 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH0432298A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10443608B2 (en) 2015-03-30 2019-10-15 Mitsubishi Electric Corporation Impeller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10443608B2 (en) 2015-03-30 2019-10-15 Mitsubishi Electric Corporation Impeller

Similar Documents

Publication Publication Date Title
US6205032B1 (en) Low temperature co-fired ceramic with improved registration
KR940009175B1 (en) Multi-printed wiring board
US5375042A (en) Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositely facing surfaces of a thick film circuit
US4300115A (en) Multilayer via resistors
US6483037B1 (en) Multilayer flexible FR4 circuit
JPH04283987A (en) Electronic circuit device and manufacture thereof
KR100489820B1 (en) Ceramic Multilayer Substrate and its Manufacturing Process
US4417297A (en) Printed circuit board
JP2715934B2 (en) Multilayer printed wiring board device and method of manufacturing the same
JP2001274555A (en) Printed wiring board, blank board for printed wiring, semiconductor device, manufacturing method for printed wiring board and manufacturing method for semiconductor device
JPH0432298A (en) Multilayer printed wiring board
JP2630293B2 (en) Multilayer wiring board
JP3126382B2 (en) Circuit manufacturing method
US6381120B2 (en) Mounting arrangement for multilayer electronic part
US5763060A (en) Printed wiring board
JPS62196811A (en) Ceramic substrate with built-in capacitor
JPS6236900A (en) Manufacture of compound printed wiring board
JPH03190187A (en) Multilayer printed wiring board
WO2019240000A1 (en) Method for manufacturing electric element, electric element, and electric element mounting structure
WO2021108775A1 (en) Pcb fabrication with dielectric powder or suspension
JPS6175596A (en) Manufacture of through hole multilayer circuit board
JPH01289201A (en) Chip resistor and manufacture thereof
JPH03136396A (en) Electronic circuit component, manufacture thereof and electronic circuit apparatus
JPS60236279A (en) Plate for circuit
JP3250166B2 (en) Multilayer composite electronic components