JPH04321231A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance an amplification factor without lowering the breakdown voltage of a bipolar element by a method wherein a thin insulating film in a direction crossed with a carrier movement direction is formed in an emitter region. CONSTITUTION:An SiO2 film 10 is formed inside an opening part 11 in an oxide film 4 so as to pass an emitter region 3 in the transverse direction (the plane direction). The lower part of the SiO2 film 10 is formed as an N<--> type region 3a formed by an impurity diffusion technique; its upper part is formed as a polysilicon layer 3b as an emitter electrode; the layers 3a and 3b constitute one emitter. The SiO2 film 10 is formed to be thin at 50Angstrom or lower, especially at 10 to 20Angstrom . This is realized by implanting ions into the N<--> type region 3a and by oxidizing it. When the thin SiO2 film 10 is formed in the emitter region 3, the tunneling probability of holes whose effective mass is large as compared with that of electrons is made small and an IBE can be lowered.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and particularly to a semiconductor device having a bipolar transistor element. [0002] In a conventional bipolar element, as shown in FIG. 8, for example, a P+ type base region 2 and an N++ type emitter region 3 are formed in an N- type collector region 1 by diffusion technology. (4 in the figure is a surface oxide film). However, although cross-sectional hatching is omitted in FIG. 8 for ease of understanding, the same may be done in other drawings to be described later. However, in order to improve the performance of the device, it is extremely difficult to increase the current amplification factor hFE and the withstand voltage (drop voltage BVceo between emitter and collector) of these NPN type bipolar elements. There was found. This is considered to be due to the following reasons. [0004] In the above bipolar element, simply P
Since the structure is just two N junctions combined, the hole 5 enters the emitter region 3 from the base region 2 and easily passes through the emitter region 3 as HOLE (1), as shown in FIG. . At this time, part of the hall is HOLE (2
), which combines with electrons in the emitter region 3 and disappears. Therefore, the base current Ibase is Ibase=Iho
It can be expressed as le(1)+Ihole(2). On the other hand, electrons 6 enter the base region 2 from the emitter region 3, pass through the base region 2, reach the collector region 1, and enter the I
It becomes ce. Therefore, in the bipolar element shown in FIG. 8, the breakdown voltage does not become very high because a potential difference occurs between the base region 2 and the collector region 1. In addition, hFE can be expressed as hFE=ICE/IBE, and from the above, I
BE becomes large and hFE tends to become small. And h
If an attempt is made to reduce the base thickness and increase the base concentration in order to increase the FE, the BVceo will actually decrease. OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor device that can increase the amplification factor without reducing the breakdown voltage of a bipolar element. SUMMARY OF THE INVENTION That is, the present invention provides a semiconductor device having an emitter region, a base region, and a collector region, and in which a thin insulating film is formed in the emitter region in a direction intersecting the direction of carrier movement. This is related to. [Examples] Examples of the present invention will be described in detail below. 1 to 3 show an NPN bipolar device according to a first embodiment of the present invention. The basic structure of the bipolar element according to this example is the same as that of the conventional example shown in FIG. 8, so common parts are given common reference numerals and explanations may be omitted. However, what should be noted in this example is that inside the emitter region 3,
An extremely thin SiO2 film 10 is formed in the plane direction. This SiO2 film 10 is formed in the opening 11 of the oxide film 4, passing through the emitter region 3 laterally (in the planar direction). The lower part of the SiO2 film 10 is an N++ type region 3a formed by ordinary impurity diffusion technology, and the upper part is a polysilicon layer 3b as an emitter electrode, and these 3a and 3b constitute one emitter. ing. [0011] The SiO2 film 10 has a thickness of 50 Å or less, particularly 10
It is preferable to form the layer as extremely thin as ~20 Å. This can be easily achieved by forming the N++ type region 3a by ion implantation technique and then performing oxidation according to a conventional method. As described above, it has been found that by providing the thin SiO2 film 10 in the emitter region 3, the tunneling probability of holes, which have a larger effective mass than electrons, is reduced, thereby reducing the IBE. The effective mass m* can be expressed as follows. Electron: m*(e)=0.26m Hole: m*(h)=0.49m Further, the tunneling probability T is defined as follows. [Equation 1] (However, m*: effective mass, Eg: energy gap, q: total charge, h: Planck's constant, φ: electric field) 00
14] From the above, since m*(e)<m*(h), the tunneling probability becomes T(m*(e))>T(m*(h)), and holes tunnel through the SiO2 film. It turns out that it is difficult to cause this. According to this example, as shown in FIGS. 1 and 3, the SiO2 film 10 inserted into the emitter region 3 prevents the holes 5 from entering the emitter region 3a from the base region 2. , it is considered that it cannot penetrate to the upper part 3b side. That is, [Equation 2]. As a result, the above hole 5 or HOLE(
2) combines with electrons, which are the majority carriers in the emitter region, and disappears, so it can be expressed as follows. That is, IBE decreases. At this time, electrons 6 tunnel through the SiO2 film 10, enter the base region 2 from the emitter region, penetrate the base region 2, and reach the collector region 1. [0017] First, regarding hFE, hFE=
Since it can be expressed as ICE/IBE, IBE is
Since there is effectively less hFE, the apparent hFE increases. Generally, BVceo is an avalanche breakdown caused by a high electric field 12 generated between the base region 2 and collector region 1, as shown in FIG. 2, and the electrons 6' generated at this time are attracted to the area. On the other hand, the hole 5′ that occurred is
It is held back by the SiO2 film 10 inserted into the emitter region 3. In this case, holes that cannot combine with electrons and disappear are pushed back to the base region 2, so the base potential increases and the base-collector potential difference decreases. As a result, it is thought that the apparent breakdown voltage (BVceo) increases and the breakdown voltage improves. [0019] The above hFE is a SiO2 film 10
The film thickness changes depending on the film thickness, so the film thickness must be appropriately controlled. This can be achieved by selecting the atmospheric temperature, gas composition, etc. after ion implantation. [0020] Furthermore, after the growth of this SiO2 film 10,
Typically, the structure of FIG. 1 is created by depositing polysilicon over the entire surface by CVD (chemical vapor deposition) and patterning it, leaving it as layer 3b. FIG. 4 shows the oxidation time (
(corresponding to film thickness) is plotted. The data are summarized below. Oxidation time 0 minutes
30 minutes 1 hour 6 hours
hFE (average) 421 457
590 856
hFE (min) 365
419 503 696
hFE (max) 465
514 644
[942] According to this, it can be seen that hFE is improved depending on the natural oxidation time, especially when the natural oxidation time is 1 hour or more. This is SiO2 film 1
This means that the larger the film thickness of 0, the smaller the IBE. FIG. 5 shows a specific structural example of the above-mentioned NPN type bipolar element. The silicon substrate consists of a P- type semiconductor layer 13 and a P+ type diffusion layer 14, and after forming an N+ type buried layer 15, a P- type epitaxial layer 16 is formed, and the collector region 1 described above is further formed in this epitaxial layer 16. An N- type well region is formed, and the P+ type region 2 as the base region is formed. Further, after the formation of the P++ type base extraction region 17, a surface oxide film 18 is grown by LOCOS (selective oxidation method), and N+ which reaches the buried region 15 by impurity diffusion from the region without this surface oxide film. mold area 1
9 and an N++ type collector extraction region 20 are formed. Next, N type impurities are implanted into the P+ type region 2 by ion implantation to form an N++ type emitter region 3a. Next, a SiO2 film 10 having a thickness of 10 to 20 Å is grown on the surface of the emitter region 3a by oxidation. Then, a SiO2 film 4 is used as an emitter diffusion mask.
A polysilicon layer is deposited thereon and patterned by etching to form the emitter upper region 3b. Thereafter, a normal process is applied to form a sidewall insulating film 21, a SiO2 film 22, and aluminum interconnections 23, 24, and 25, respectively. The bipolar transistor shown in FIG.
Specifically, it can be incorporated as a pull-down transistor Tr1 of a bi-C-MOS type inverter shown in FIG. That is, the emitter of this transistor Tr1 is grounded (Vee), and the base is an N-channel MOS for discharging.
The collector is connected to the drain of the transistor MOS1, and the collector is connected to the output (Vout), the gate of MOS1, and the input side N.
It is connected to the drain of the channel MOS transistor MOS2. The other pull-up bipolar transistor Tr2 may also have the same configuration as Tr1, with its emitter connected to Vout and its base connected to the discharge N-channel M.
The drain and collector of the OS transistor MOS3 are connected to a power supply (Vcc) and a P-channel MOS transistor MOS4 on the input side. FIG. 7 shows a second embodiment of the invention. In the bipolar transistor of this example, a SiO2 film 10 similar to that described above is formed in the emitter region, and at the same time, SiO2 is also formed on the surface of the upper emitter region 3b.
A thin SiO2 film 30 equivalent to the film 10 is formed by oxidation. That is, since the SiO2 film 30 is provided on the surface in addition to the SiO2 film 10, the holes that have entered the emitter region 3 from the base region 2 will pass through the emitter region 3 based on the phenomenon explained in FIGS. 1 to 3. It becomes more difficult for electrons to penetrate through the collector, while the electrons can easily move to the collector side. Therefore, compared to the above-mentioned example, hFE and breakdown voltage can be set to different values, and in particular, it is easier to control them to optimal setting values. Regarding the SiO2 film 30, normally, as shown in FIG.
In order to deposit the aluminum wiring 23 as shown in
The iO2 film 30 is removed, but in this example, such Si
By leaving the O2 film 30 as it is, penetration of holes is further prevented. Although the embodiments of the present invention have been described above, the embodiments described above can be further modified based on the technical idea of the present invention. For example, the above-mentioned SiO2 film 10 (or even 30) can be replaced with another insulating film. Such an insulating film may be any film that has electron and hole transmission selectivity, and in addition to SiO2, silicon nitride such as Si3 N4 can also be used. Furthermore, when such an insulating film is inserted into the emitter as in the above example, in addition to inserting only one layer as shown in FIG. 1 or two layers as shown in FIG. 7, three or more layers are inserted. An insulating film may also be provided. With multiple layers, it is easier to adjust the carrier transmittance and set it to an optimum value than in the case of a single layer. The formation position of the insulating film may also be changed, and it may be provided only on the surface of the emitter region. The above-mentioned emitter regions are the lower part 3a and the upper part 3b.
However, it is also possible to form a normal diffusion region consisting only of the lower part 3a, and in this case, a SiO2 film 10 or the like is formed on the surface of the emitter region. Furthermore, when providing the above-mentioned upper emitter region 3b, its material is not limited to polysilicon, but various conductive materials such as tungsten, tantalum, or silicide thereof can be used; however, if metal is used, electrons will not be Since it is a majority carrier, it allows electrons to pass through easily and has excellent selective permeability. Effects of the Invention As described above, the present invention forms a thin insulating film in the emitter region so as to cross the direction of carrier movement, thereby effectively reducing or reducing the penetration of carriers entering the emitter from the base. This makes it possible to improve the amplification factor, reduce the base-collector potential difference, and increase the breakdown voltage.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part for explaining improvement in hFE of an NPN bipolar element according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part for explaining improvement in breakdown voltage of a bipolar element.

FIG. 3 is a schematic diagram illustrating the situation of FIG. 1 with an energy barrier;

FIG. 4 is a graph showing a comparison of hFE of the bipolar device according to oxidation conditions.

[Figure 5] Bi-C-MO incorporating the above bipolar element
It is a sectional view of an S inverter.

FIG. 6 is an equivalent circuit diagram of the same inverter.

FIG. 7 is a cross-sectional view of an NPN bipolar device according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view of a conventional NPN type bipolar element.

[Explanation of symbols]

1 Collector area 2 Base area 3 Emitter area 3a Lower emitter area 3b Upper emitter area 5, 5' hole 6, 6' electron 10, 30 SiO2 film

Claims (1)

[Claims] 1. A semiconductor device comprising an emitter region, a base region, and a collector region, and a thin insulating film is formed in the emitter region in a direction intersecting a carrier movement direction.