JPH04320540A - Duplex system - Google Patents

Duplex system

Info

Publication number
JPH04320540A
JPH04320540A JP3113800A JP11380091A JPH04320540A JP H04320540 A JPH04320540 A JP H04320540A JP 3113800 A JP3113800 A JP 3113800A JP 11380091 A JP11380091 A JP 11380091A JP H04320540 A JPH04320540 A JP H04320540A
Authority
JP
Japan
Prior art keywords
bus
cpu
signal
stand
standby
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3113800A
Other languages
Japanese (ja)
Inventor
Hideyuki Shimura
秀幸 志村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3113800A priority Critical patent/JPH04320540A/en
Publication of JPH04320540A publication Critical patent/JPH04320540A/en
Pending legal-status Critical Current

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  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To stabilize the operation of a system consisting of an operating system and a stand-by system by preventing the application of a bus utilization permission to the stand-by system when the stand-by system is abnormally driven even if the stand-by system outputs a bus utilization request. CONSTITUTION:A switching circuit 3 imparts the utilization right of a system bus 4 to an A system CPU 1 or a B system CPU 2. When the CPU 1 is an operating system and the CPU 2 is stand-by system, the CPU 1 uses the bus 4. In the case of switching the CPU 1 to the stand-by system and the CPU 2 to the operating system, the CPU 1 outputs a bus aborting signal 200 to the circuit 3. The circuit 3 judges whether the CPU 2 is normal or not by checking a status signal 300 outputted from the CPU 2, and only when the CPU 2 is normal, outputs a bus utilization permission signal 400 and stops the output of the signal 400 to the CPU 1. When the CPU 2 is abnormal, the circuit 3 does not impart the signal 400 to the CPU 2.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔発明の目的〕 [Purpose of the invention]

【0001】0001

【産業上の利用分野】本発明はCPU等のバスマスタを
2重化したシステムに係わり、特に稼動系と待機系の切
り替え方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system in which bus masters such as CPUs are duplicated, and more particularly to a system for switching between an active system and a standby system.

【0002】0002

【従来の技術】図2は従来この種の2重化システムの一
例を示したブロック図である。今、A系、B系の両CP
U1、2が動作していない時、A系のCPU1がバス要
求信号100を調停回路3に出力すると、この調停回路
3は前記要求信号を受け付けてバス使用許可信号101
をCPU1に与える。これにより、CPU1はシステム
バス4を使用してジョブを実行する。一方、B系のCP
U2は待機系になる。この待機系となったCPU2が何
等かの原因で暴走し、A系のCPU1が稼動系にあるに
も拘らず、バス要求信号100を調停回路3に出してし
まったとする。調停回路3はバス要求信号の受け付けの
早いもの順にバス使用権を与える処理を行うため、上記
のようにCPU2からバス要求信号が出されると、この
CPU2にバス使用許可信号101を与えてしまう。こ
れにより、本来待機系であるはずのCPU2がシステム
バス4を使用して稼動してしまい、2重化システムの原
則、即ち待機系が現用稼働系の動作を破壊してはならな
いという原則破れてしまい、システムの処理を混乱させ
てしまうという欠点があった。
2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional duplex system of this type. Currently, both A-type and B-type CP
When U1 and U2 are not operating, when the A-system CPU 1 outputs the bus request signal 100 to the arbitration circuit 3, the arbitration circuit 3 receives the request signal and outputs the bus use permission signal 101.
is given to CPU1. Thereby, the CPU 1 uses the system bus 4 to execute the job. On the other hand, B-type CP
U2 becomes a standby system. Suppose that the CPU 2 in the standby system goes out of control for some reason and outputs the bus request signal 100 to the arbitration circuit 3 even though the CPU 1 in the A system is in the active system. Since the arbitration circuit 3 performs the process of granting the bus use right in the order of receiving the bus request signal first, when the bus request signal is issued from the CPU 2 as described above, the bus use permission signal 101 is given to the CPU 2. As a result, CPU2, which was originally supposed to be a standby system, started operating using system bus 4, breaking the principle of the redundant system, that is, the principle that the standby system should not destroy the operation of the active system. This has the disadvantage of causing confusion in system processing.

【0003】0003

【発明が解決しようとする課題】上記のような従来の2
重化システムでは、稼動系に対して待機系がバス要求信
号を何等かの障害により調停回路に出した場合、この調
停回路は前記バス要求信号を出した待機系に対してバス
使用権を与えてしまうため、待機系が暴走してシステム
に障害を起こしてしまうという欠点があり、冗長構成の
メリットが生かし切れないと言う欠点があった。
[Problem to be solved by the invention] The conventional two methods as described above
In a redundant system, when a standby system sends a bus request signal to an arbitration circuit due to some kind of failure in response to an active system, this arbitration circuit grants the right to use the bus to the standby system that issued the bus request signal. This had the disadvantage that the standby system could go out of control and cause system failure, and the advantages of the redundant configuration could not be fully utilized.

【0004】そこで本発明は上記の欠点を除去するもの
で、待機系がバス使用要求を出しても待機系が異常に動
作している場合は前記待機系にバスの使用許可を与える
ことを防止して、安定な動作を行うことができる2重化
システムを提供することを目的としている。〔発明の構
成〕
Therefore, the present invention aims to eliminate the above-mentioned drawbacks, and prevents the standby system from being granted permission to use the bus if the standby system is operating abnormally even if the standby system issues a request to use the bus. The purpose of this invention is to provide a duplex system that can operate stably. [Structure of the invention]

【0005】[0005]

【課題を解決するための手段】本発明は複数のバスマス
タを有し、これらバスマスタの1つにバス使用権を与え
ると共に、待機系のバスマスタにはバス使用権を与えな
い制御を行う2重化システムにおいて、バス権放棄信号
を出した系が正常状態にあるか異常状態であるかを判定
する第1の判定手段と、この第1の判定手段によってバ
ス権放棄信号を出した系が正常でないと判定された場合
は前記バス権放棄信号を受付けない制御を行う第1のバ
ス権切替手段と、これからバス使用権を与える系が正常
状態であるか異常状態であるかを判定する第2の判定手
段と、この第2の判定手段によってこれからバス使用権
を与える系が異常状態であると判定された場合はバス使
用権を前記系に与えない制御を行う第2のバス権切替手
段とを具備した構成を有する。
[Means for Solving the Problems] The present invention has a plurality of bus masters, and provides redundant control for giving the right to use the bus to one of these bus masters, while not giving the right to use the bus to a standby bus master. In the system, there is a first determining means for determining whether the system that issued the bus relinquishment signal is in a normal state or an abnormal state, and the first determining means determines that the system that issued the bus relinquishment signal is not normal. If it is determined that this is the case, a first bus right switching means performs control such that the bus right abandonment signal is not accepted; a determining means; and a second bus right switching means for performing control such that if the second determining means determines that the system to which the right to use the bus is to be given is in an abnormal state, the right to use the bus is not granted to the system. It has a complete configuration.

【0006】[0006]

【作用】本発明の2重化システムにおいて、第1の判定
手段はバス権放棄信号を出した系が正常状態にあるか異
常状態であるかを判定する。第1のバス権切替手段は前
記第1の判定手段によってバス権放棄信号を出した系が
正常でないと判定された場合は前記バス権放棄信号を受
付けない制御を行う。第2の判定手段はこれからバス使
用権を与える系が正常状態であるか異常状態であるかを
判定する。第2のバス権切替手段は前記第2の判定手段
によってこれらかバス使用権を与える系が異常状態であ
ると判定された場合はバス使用権を前記系に与えない制
御を行うとを具備した構成を有する。
In the duplex system of the present invention, the first determining means determines whether the system that issued the bus relinquishment signal is in a normal state or in an abnormal state. The first bus right switching means performs control such that the bus right relinquishing signal is not accepted when the first determining means determines that the system that issued the bus right relinquishing signal is not normal. The second determining means determines whether the system to which the right to use the bus is granted is in a normal state or in an abnormal state. The second bus right switching means is configured to perform control such that the bus right is not granted to the system when it is determined by the second determining means that one of the systems to which the right to use the bus is granted is in an abnormal state. It has a configuration.

【0007】[0007]

【実施例】以下、本発明の一実施例を図面を参照して説
明する。図1は本発明の2重化システムの一実施例を示
したブロック図である。1はA系のCPU、2はB系の
CPU、3はA系又はB系のCPUにシステムバス4の
使用権を与える切替回路、4はA系のCPU1又はB系
のCPU2によって使用されるシステムバスである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the duplex system of the present invention. 1 is the CPU of the A system, 2 is the CPU of the B system, 3 is a switching circuit that gives the right to use the system bus 4 to the CPU of the A system or the B system, and 4 is used by the CPU 1 of the A system or the CPU 2 of the B system. It is a system bus.

【0008】次に本実施例の動作について説明する。 今、A系のCPU1が稼動系で、B系のCPU2が待機
系であった場合、A系のCPU1がシステムバス4を使
用して各種ジョブを行っている。その後、A系のCPU
1が待機系に、B系のCPU2を稼動系にすべく切り替
える場合、A系のCPU1はバス放棄信号200を切替
回路3に出力する。切替回路3はバス放棄信号200を
受けると、B系のCPU2から出力されているステータ
ス信号300を見て、前記B系のCPU2が正常である
か異常であるかを判定し、B系のCPU2が正常であっ
た場合にのみ、このCPU2にバス使用許可信号400
を出力すると共に、A系のCPU1に出していたバス使
用許可信号400の出力を停止する。これにより、B系
のCPU2がシステムバス4を使用してジョブの処理を
開始し、一方、A系のCPU1は待機系となる。
Next, the operation of this embodiment will be explained. Now, if the A-system CPU 1 is the active system and the B-system CPU 2 is the standby system, the A-system CPU 1 is using the system bus 4 to perform various jobs. After that, the A-based CPU
When the CPU 1 of the A system is to be switched to the standby system and the CPU 2 of the B system to be the active system, the CPU 1 of the A system outputs a bus abandonment signal 200 to the switching circuit 3. When the switching circuit 3 receives the bus abandonment signal 200, it looks at the status signal 300 output from the B-system CPU 2, determines whether the B-system CPU 2 is normal or abnormal, and switches the B-system CPU 2 is normal, the bus use permission signal 400 is sent to this CPU2.
At the same time, the output of the bus use permission signal 400 sent to the A-system CPU 1 is stopped. As a result, the B-system CPU 2 starts processing the job using the system bus 4, while the A-system CPU 1 becomes a standby system.

【0009】ところで、上記の稼動系と待機系の切り替
え時に、B系のCPU2のステータス信号300を切替
回路3が見た結果、CPU2が異常であった場合、切替
回路3はA系のCPU1からのバス放棄信号200の出
力に拘らず、バス使用許可信号400をこのままA系の
CPU1に出して、A系のCPU1を稼動系のままにす
る。これと同時に、切替回路3はB系のCPU2にバス
使用許可信号400を与えず、このまま待機状態として
、稼動系、待機系の切り替えを行わない。
By the way, when switching between the active system and the standby system as described above, if the switching circuit 3 checks the status signal 300 of the CPU 2 of the B system and finds that the CPU 2 is abnormal, the switching circuit 3 switches the status signal from the CPU 1 of the A system. Regardless of the output of the bus abandonment signal 200, the bus use permission signal 400 is output as is to the CPU 1 of the A system, and the CPU 1 of the A system remains in the active system. At the same time, the switching circuit 3 does not give the bus use permission signal 400 to the B-system CPU 2, keeps it in a standby state, and does not switch between the active system and the standby system.

【0010】次に、稼動中のA系のCPU1が異常状態
になると、切替回路3はCPU1から出力されているス
テータス信号300によりCPU1の異常を知る。これ
により、切替回路3は、A系のCPU1に出していたバ
ス使用許可信号400の出力を停止し、代わりにバス使
用許可信号をB系のCPU2に出して、B系のCPU2
を稼動系に、A系のCPU1を待機系に切り替える。
[0010] Next, when the A-system CPU 1 in operation becomes abnormal, the switching circuit 3 learns of the abnormality of the CPU 1 from the status signal 300 output from the CPU 1. As a result, the switching circuit 3 stops outputting the bus use permission signal 400 that was being sent to the A-system CPU 1, and instead outputs the bus use permission signal 400 to the B-system CPU 2.
is switched to the active system, and the CPU 1 of the A system is switched to the standby system.

【0011】ここで、待機状態にあるB系のCPU2が
暴走してバス放棄信号200を切替回路3に出しても、
切替回路3はB系のCPU2から出力されるステータス
信号からCPU2が異常であることを認識し、このCP
U2から出されたバス放棄信号を受付けるようなことは
しないため、B系のCPU2にはそのまま待機系にとど
まる。
Here, even if the B system CPU 2 in the standby state goes out of control and sends the bus abandonment signal 200 to the switching circuit 3,
The switching circuit 3 recognizes that the CPU 2 is abnormal from the status signal output from the B-system CPU 2, and
Since the bus abandonment signal sent from U2 is not accepted, the B-system CPU2 remains in the standby system.

【0012】本実施例によれば、稼動系、待機系の正常
/異常状態を監視して、バス放棄信号を出した系が異常
であった場合はこのバス放棄信号を受付けず、又バス使
用許可信号を与える系が異常であった場合はこの系に前
記バス使用許可信号を与えないようにしているため、待
機系が暴走してこの待機系にバス権を与えてしまう等と
いう誤動作を防止することができ、2重化システムの本
来のメリットを最大限引き出すことができる。
According to this embodiment, the normal/abnormal state of the active system and the standby system is monitored, and if the system that has issued the bus abandonment signal is abnormal, this bus abandonment signal is not accepted, and the bus is not used. If the system that gives the permission signal is abnormal, the bus usage permission signal is not given to this system, which prevents malfunctions such as the standby system going out of control and giving the bus right to the standby system. This makes it possible to maximize the inherent benefits of a redundant system.

【0013】[0013]

【発明の効果】以上記述した如く本発明の2重化システ
ムによれば、待機系がバス使用要求を出しても待機系が
異常に動作している場合は前記待機系にバスの使用許可
を与えることを防止して、安定な動作を行うことができ
る。尚、上記実施例では2重化システムについて本発明
に適用した例について述べたが、n重化システムについ
て本発明を適用した同様の効果を得ることができる。但
しn≧2
As described above, according to the redundant system of the present invention, even if the standby system issues a bus use request, if the standby system is operating abnormally, the standby system is granted permission to use the bus. It is possible to perform stable operation by preventing damage from occurring. In the above embodiment, an example in which the present invention is applied to a duplex system has been described, but similar effects can be obtained when the present invention is applied to an n-duplex system. However, n≧2

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の2重化システムの一実施例を示したブ
ロック図。
FIG. 1 is a block diagram showing an embodiment of a duplex system of the present invention.

【図2】従来の2重化システムの一例を示した図。FIG. 2 is a diagram showing an example of a conventional duplex system.

【符号の説明】[Explanation of symbols]

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数のバスマスタを有し、これらバスマス
タの1つにバス使用権を与えると共に、待機系のバスマ
スタにはバス使用権を与えない制御を行う2重化システ
ムにおいて、バス権放棄信号を出した系が正常状態にあ
るか異常状態であるかを判定する第1の判定手段と、こ
の第1の判定手段によってバス権放棄信号を出した系が
正常でないと判定された場合は前記バス権放棄信号を受
付けない制御を行う第1のバス権切替手段と、これから
バス使用権を与える系が正常状態であるか異常状態であ
るかを判定する第2の判定手段と、この第2の判定手段
によってこれからバス使用権を与える系が異常状態であ
ると判定された場合はバス使用権を前記系に与えない制
御を行う第2のバス権切替手段とを具備したことを特徴
とする2重化システム。
Claim 1: In a duplex system having a plurality of bus masters, in which one of these bus masters is given the right to use the bus, and a standby bus master is not given the right to use the bus, a bus right relinquishing signal is provided. a first determining means for determining whether the system that issued the bus right relinquishing signal is in a normal state or an abnormal state; a first bus right switching means that performs control not to accept a bus right abandonment signal; a second determining means that determines whether the system to which the right to use the bus is to be given is in a normal state or in an abnormal state; and a second bus right switching means that performs control such that if the system to which the right to use the bus is to be given is determined to be in an abnormal state by the determining means, the right to use the bus is not granted to the system. Duplex system.
JP3113800A 1991-04-19 1991-04-19 Duplex system Pending JPH04320540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3113800A JPH04320540A (en) 1991-04-19 1991-04-19 Duplex system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3113800A JPH04320540A (en) 1991-04-19 1991-04-19 Duplex system

Publications (1)

Publication Number Publication Date
JPH04320540A true JPH04320540A (en) 1992-11-11

Family

ID=14621399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3113800A Pending JPH04320540A (en) 1991-04-19 1991-04-19 Duplex system

Country Status (1)

Country Link
JP (1) JPH04320540A (en)

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