JPS62173538A - Deciding system for working or spare state - Google Patents

Abstract

PURPOSE:To fix both working and spare central control units CP with a duplexed CPU by securing a time difference between the application of a power supply and the transmission of the start signal received from each start time limit part. CONSTITUTION:A connection terminal 39a is connected in a CPU 3a and a connection terminal 39b is cut off in a CPU 3b respectively. When the power supply voltage V0 is applied, the input voltage V1a has a sudden rise compared with the input voltage V1b. Thus a gate A in a power supply application circuit 31a can set the output voltage V2a to a high level from a low level in a short time compared with a gate A in a power supply application circuit 31b. Therefore the start signal (ra) is outputted from the circuit 31a earlier than the circuit 31b. Thus the signals Sa and Sb are set in a using state and a spare state respectively.

Description

[Detailed Description of the Invention] [Summary] In a redundant central control unit, the time required for each power-on unit to output a start signal is made different, so that the start signal is output earlier, and the central control unit becomes the active system. By fixing the device, it is convenient for maintenance and system management.

[Industrial application field]

TECHNICAL FIELD The present invention relates to an improvement of a working preliminary determination scheme in a redundant central control unit.

In particular, central control units such as electronic exchanges that require high reliability are duplicated, with one operating as an active system and the other on standby as a standby system. If the active system central controller is affected, the active system and standby system are immediately switched, and the standby central controller starts operating as the active system.

When power is turned on to such a central control unit, the central control unit that becomes operational early is set as the active system, and the central control unit that becomes operational later is set as the standby system.

In such a case, in a multiprocessor type central processing system that uses multiple sets of duplicated central control units, it is recommended for maintenance and system management that the central control unit that becomes the active system when the power is turned on is fixed in advance. Highly requested.

[Conventional technology]

FIG. 4 is a diagram showing an example of a central processing system to which the present invention is applied.

In FIG. 4, one set of management processing devices 1 and a plurality of sets of call processing devices 2 each refer to a redundant central control device 3.
one central control device 3a or jb operates as an active system, and the other central control device 3b or 3a stands by as a standby system.

FIG. 5 is a diagram showing an example of a conventional central control device,
6 is a diagram showing an example of the power-on circuit in FIG. 5, and FIG. 7 is a diagram showing various voltages in FIG. 6.

In FIG. 5, the central control device 3a (3b) includes a power-on circuit (PO) 31a (3lb), a processor (MPU) 32a (32b) that controls call processing, etc., and a central control device 3a (3b). Emergency control circuit (EMA) 33a that detects a fault and switches between the active system and the standby system
(33b), and gate 34a (34b)
, 35a (35b), a resistor 36a (36b), and a capacitor 37a (37b).

In FIG. 6, power-on circuit (PO) 3La (3l
b) is composed of gate A and inverter (2). The gate A receives an input voltage Via (Vlb) obtained by dividing the power supply voltage VO by a resistor 36a (36b) and a capacitor 37a (37b). When the power is turned on,
Even if the power supply voltage VO reaches a steady value after a short time, the input voltage Vla (Vlb) gradually increases based on the time constant determined by the resistor 36a (36b) and the capacitor 37a (37b), and after a predetermined time T, the input voltage Vla (Vlb) increases. When the dark value voltage Vt of A is reached, the gate output voltage V2a (V2b) output from A changes from a low level to a high level. Output voltage V3 output from inverter I
a (V3b) is set to a high level immediately after the power is turned on, and maintains a high level while the gate output voltage v2a (V2b) is set to a low level, but the gate output voltage V
When 2a (V2b) changes to a high level, it changes to a low level and is sent to the processor (MPU) as an activation signal ra (rb).
32a (32b).

In FIG. 5, a processor (MPU) 32a (32b
) becomes operational when the power supply voltage VO reaches a stable value after power-on, but the power-on circuit (PO) 31a
(3l b) output voltage V3a (V
It does not start operation while 3b) is set to high level. After a predetermined time T, the power-on circuit (PO) 31a (3
When the output voltage V3a (V3b) from the processor (MPU) 32a (32b) changes to a low level, the output voltage V3a (V3b) from the processor (MPU) 32a (32b
) starts working.

Note that the output voltage v3a (V3b) output from the power supply circuit (PO) 31a (3lb) is applied to the gate 34.
a (34b) is also input. Output voltage ■3a (V3
b) is at a high level, the output voltage of gate 34a (34b) is set to a low level, and gate 35a (35
The output voltage of step b), ie, the working standby signal 5a (sb), is set to a high level.

In such a state, for example, if the output voltage v3 from the power-on circuit (PO) 31a first changes to a low level, the game) 3
The output voltage of the gate 35a changes to a high level, the output voltage of the gate 35a changes to a low level, the working standby signal sa is set to the working state, and the central controller 3a operates as a working system.

Next, the output voltage from the power supply circuit (PO) 31b ■3
When the voltage changes to a low level, the output voltage of the gate 34b changes to a high level, but since the working standby signal Sa, which is already set to a low level, is input to the gate 35b, the output voltage of the gate 35a changes to a high level. The level is maintained, the active standby signal sb is set to the standby state, and the central controller 3b stands by as a standby system.

Since the central controllers 3a and 3b have the same configuration, which one of the central controllers 3a and 3b becomes the active system when the power is turned on depends on the specifications of the resistors 36a and 36b and the capacitors 37a and 37b. It depends on the deviation from the value and is not fixed.

[Problem that the invention seeks to solve]

As is clear from the above description, in the conventional central control device, the central control devices 3a and 3 have the same configuration.
It was doubled by b.

Therefore, in the central processing system as shown in FIG. 4, when the power is turned on, which central control device 3a (3b) in the management processing bag W1 and each call processing device 2 becomes the active system? and 3b differ from the standard characteristics, which is inconvenient in terms of maintenance and system management.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 3a and 3b are duplicated central control units that are the object of the present invention.

100a and 100b are processing units 200a and 200 after a predetermined time sufficient to stabilize the power supply voltage VO when the power is turned on.
This is a power-on unit that inputs activation signals ra and rb to b.

200a and 200b are processing units that manage various processes.

Reference numeral 300 denotes a current/preliminary determining unit which determines that the earlier output timing of activation signals ra and rb from each power-on unit 100a and 100b is the active system, and the later one is the backup system.

400a and 400b are provided according to the present invention, and each power-on section 100a, 100b receives a start signal r after power-on.
This is a time limit means that allows a difference in time until outputting a and rb.

[Effect]

In the present invention, after the power is turned on, each startup timer 100a
There is a difference in the time it takes for the start signal ra or rb to be output from the start signal 100b.

As a result, the central control units 3a (3b) which become the active system and the standby system when the power is turned on are fixed, which is convenient for maintenance and system management.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a central control unit according to an embodiment of the present invention, and FIG. 3 is a diagram showing various voltages in FIG. 2. Note that the same reference numerals refer to the same objects throughout the plan.

In FIG. 2, a resistor 38 is shown in parallel with each resistor 36a and 36b in each central controller 3a and 3b.
a and the connecting terminal 39a, and the resistor 38b and the connecting terminal 39
b are provided as timer means 400a and 400b.

If the connecting terminal 39a in the central controller W3a is now connected and the connecting terminal 39b in the central controller 3b is disconnected, the resistor 38a will be connected in parallel to the resistor 36a in the central controller 3a. .

Therefore, as shown in FIG.
The input voltage Via to 1a is the input voltage Vl to power-on circuit (PO) 31b in central controller 3b.
b, and the gate A in the power-on circuit (PO) 31b in the central controller 3b changes the gate output voltage V2b from a low level to a high level at T1 for a sufficiently short time compared to the time T. , the gate) A in the power-on circuit (PO) 31a in the central controller 3a is the gate output voltage V.
2a from low level to high level.

As a result, the power-on circuit (PO) 31a always outputs the activation signal ra earlier than the power-on circuit (PO) 31b, and when the power is turned on, the working standby signal sa is always in the working state, and the working standby signal sb is always in the working state. will be set to the standby state.

Therefore, in the central processing system as shown in FIG. 4, the connection terminals 39a in all the central control devices 3a in the management processing device 1 and each call processing device 2 are connected, and the connection terminals 39b in the central control device 3b are disconnected. If this is done, when the power is turned on, in all the management processing devices 1 and call processing devices 2, the central control device 3a becomes the active system and the central control device 3b becomes the standby system.

As is clear from the above description, according to this embodiment, in the management processing device 1 and each call processing device 2, when the power is turned on, all the central control devices 3a are in the active system, and all the central control devices 3b are in the active system. will be fixedly set in the standby system.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and for example, the timer means 400a and 400b are not limited to those shown, and many other modifications may be considered. However, the effects of the present invention remain the same in either case. It goes without saying that the central processing system to which the present invention is applied is not limited to that shown in the drawings.

Effects of the Invention As described above, according to the present invention, in the central control unit, the central control units that become the active system and the standby system are fixed when the power is turned on, which is convenient for maintenance and system management.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a central control unit according to an embodiment of the present invention, FIG. 3 is a diagram showing various voltages in FIG. 2, and FIG. 4 is a diagram showing the present invention. FIG. 5 is a diagram showing an example of a conventional central control device, FIG. 6 is a diagram showing an example of the power-on circuit in FIG. 5, and FIG. FIG. 6 is a diagram showing various voltages in FIG. 6; In the figure, 1 is a management processing device, 2 is a call processing device, and 3a
and 3b is a central control unit, 31a and 31b are power-on circuits (PO), and 32a and 32b are processors (
MPU), 33a and 33b are emergency control circuits (EMA
), 34a, 34b, 35a and 35b are gates, 3
6 a, 36 b. 38a and 38b are resistors, 37a and 37b are capacitors, 39a and 39b are connection terminals, 100a and 100b are power-on sections, 200a and 200b are processing sections, 300 is a working preliminary determination section, 400a and 400
b is a timer, A is a gate, ■ is an inverter, ra and rb are start signals, sa and sb are active standby signals, T
and T1 is time, ■0 is power supply voltage, Via and Vl
b is the input terminal, V2a and v2b are the gate output voltages,
V3a and v3b are the output voltages, and Vt is the dark value. Chuo 22;, 1 Yoshihiro Tate
,ryJ Fig.f

Claims (1)

[Scope of Claims] A processing unit (200a, 200b) in charge of various processes, and a startup signal (r
a, rb) are input to the power input unit (100a, 100b).
) and the output timing of the activation signals (ra, rb) from each power supply unit (100a, 100b) is set as the active system,
In a duplex central control unit (3a, 3b) comprising a current use/preparation determining unit (300) that determines the slower one as a backup system, each power supply unit (100a, 100b) receives the start signal ( A time limit means (400a, 400b) is provided to set a difference in time until outputting the signals (ra, rb), and the central controllers (3a, 3b), which become the active system and the standby system, are fixed when the power is turned on. The current preliminary determination method.