JPH04320055A - Lead frame and semiconductor package - Google Patents

Lead frame and semiconductor package

Info

Publication number
JPH04320055A
JPH04320055A JP11224191A JP11224191A JPH04320055A JP H04320055 A JPH04320055 A JP H04320055A JP 11224191 A JP11224191 A JP 11224191A JP 11224191 A JP11224191 A JP 11224191A JP H04320055 A JPH04320055 A JP H04320055A
Authority
JP
Japan
Prior art keywords
polysilazane
lead frame
resin
semiconductor package
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11224191A
Other languages
Japanese (ja)
Inventor
Takayuki Ando
孝行 安藤
Masayuki Hida
雅之 飛田
Yoshinori Ujiie
氏家 喜則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP11224191A priority Critical patent/JPH04320055A/en
Publication of JPH04320055A publication Critical patent/JPH04320055A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Silicon Polymers (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To increase adhesive properties with sealing resin and to improve crack resistance and moisture resistance reliability of a resin-sealed semiconductor package by covering a surface of a lead frame with special polysilazane. CONSTITUTION:A material of a lead frame is formed of materials such as Fe-Ni alloy such as 42 alloy, a Cu-based alloy, etc., Polysilazane covering the frame is represented by a formula, where its average molecular weight is desirably 100-100000. The polysilazane is used by diluting with inactive solvent such as benzene, toluene, etc., but 100% polysilazane may be used. After the frame is covered with the polysilazane, the polysilazane is crosslinked or condensed by baking to form a stable film. A silicon chip 4 is wire bonded on a stage 2 in the frame 1 in which the polysilazane 3 is baked, and then sealed with epoxy-based sealing resin 6 after wire bonding 5 to manufacture a semiconductor package.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体チップを搭載す
るリードフレームおよびこのリードフレームを用いて樹
脂封止した半導体パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame on which a semiconductor chip is mounted and a semiconductor package sealed with resin using this lead frame.

【0002】0002

【従来の技術】近年、半導体チップをリードフレームに
搭載したのち、エポキシ樹脂等で樹脂封止した半導体パ
ッケージは、耐湿信頼性等が向上し量産性が良くかつ比
較的低コストなために、セラミック系パッケージを圧倒
する勢いで数量ともに伸び実用化されている。しかし、
これらの樹脂封止した半導体パッケージは、空気中に放
置されると封止樹脂が水分を吸収し、プリント基板に半
田付けする際の熱衝撃によって樹脂とリードフレームの
界面が剥離して樹脂にクラックが発生したり、半導体素
子の機能を損なうなどの支障があった。この現象を解決
するために、エポキシ系封止樹脂の低吸湿化や耐クラッ
ク性およびリードフレームとの密着性の改良のほか、リ
ードフレームの改良などが試みられている。
[Prior Art] In recent years, semiconductor packages in which a semiconductor chip is mounted on a lead frame and then sealed with epoxy resin, etc., have been developed using ceramics, which have improved moisture resistance and reliability, are easy to mass produce, and are relatively low cost. It has been put into practical use and is increasing in both quantity and overwhelming the other packages. but,
When these resin-sealed semiconductor packages are left in the air, the sealing resin absorbs moisture, and the interface between the resin and lead frame peels off due to thermal shock when soldering to a printed circuit board, causing cracks in the resin. There have been problems such as generation of problems and damage to the functions of semiconductor devices. In order to solve this phenomenon, attempts have been made to reduce the moisture absorption of the epoxy sealing resin, improve crack resistance, and improve adhesion to the lead frame, as well as improve the lead frame.

【0003】0003

【発明が解決しようとする課題】上記のリードフレーム
と封止樹脂との密着性を向上させる目的で、リードフレ
ーム側からも様々な対策が検討されている。例えば、リ
ードフレームの表面をシランカップリング剤で処理する
方法( 特開昭56−164,564号公報、特開昭5
7−152,157号公報) 、リードフレーム表面に
細かい凹凸を形成する方法( 特開昭56−115,5
51号公報、特開平2−285,662 号公報) お
よびポリイミドをコーティングする方法等が提案されて
いる。ところが、これらの方法によっても、吸湿したパ
ッケージを熱衝撃にさらすとリードフレームと樹脂の界
面が部分的に剥離し、クラックが生じたり、耐湿信頼性
を損ねるなどの問題を残していた。本発明は、これらの
問題点に鑑みなされたものであって、密着性、耐クラッ
ク性および耐湿信頼性に優れるリードフレームおよび半
導体パッケージがを提供することを目的とするものであ
る。
[Problems to be Solved by the Invention] In order to improve the adhesion between the lead frame and the sealing resin, various measures have been considered from the lead frame side. For example, a method of treating the surface of a lead frame with a silane coupling agent (JP-A-56-164,564, JP-A-5
7-152,157), a method of forming fine irregularities on the surface of a lead frame (Japanese Patent Application Laid-Open No. 115-1988)
51, Japanese Unexamined Patent Publication No. 2-285,662) and a method of coating with polyimide have been proposed. However, even with these methods, problems remain, such as when a moisture-absorbed package is exposed to thermal shock, the interface between the lead frame and the resin partially peels off, causing cracks and impairing moisture-resistance reliability. The present invention has been made in view of these problems, and an object of the present invention is to provide a lead frame and a semiconductor package that have excellent adhesion, crack resistance, and moisture resistance reliability.

【0004】0004

【課題を解決するための手段】本発明者らは、上述の問
題点を解決するために鋭意検討した結果、リードフレー
ムの表面が特定のポリシラザンで被覆されてなるリード
フレームが封止樹脂との密着性に優れ、このリードフレ
ームに半導体チップを搭載し、樹脂封止された半導体パ
ッケージが耐クラック性および耐湿信頼性が極めて良好
なことを見い出し、本発明に到達した。すなわち、本発
明は以下を要旨とするものである。
[Means for Solving the Problems] As a result of intensive studies to solve the above-mentioned problems, the present inventors have developed a lead frame whose surface is coated with a specific polysilazane, which is compatible with a sealing resin. We have discovered that a semiconductor package with excellent adhesion, in which a semiconductor chip is mounted on this lead frame and sealed with resin, has extremely good crack resistance and moisture resistance reliability, and has thus arrived at the present invention. That is, the gist of the present invention is as follows.

【0005】第1の発明は下記の式〔化2〕で表される
繰り返し単位を有するポリシラザンでその表面が被覆さ
れてなることを特徴とするリードフレームである。
The first invention is a lead frame whose surface is coated with polysilazane having a repeating unit represented by the following formula [Formula 2].

【0006】[0006]

【化2】 ( 式中、R1 、R2 およびR3 はそれぞれ水素
原子、アルキル基、アルケニル基、シクロアルケニル基
、アミノ基、アルキルアミノ基、アルキルシリル基、ま
たはこれらの基以外で主鎖の珪素および窒素に直結する
基が炭素である基デある。ただし、R1 、R2 およ
びR3 の少なくとも1つは水素原子である。)
[Formula 2] (In the formula, R1, R2 and R3 are each a hydrogen atom, an alkyl group, an alkenyl group, a cycloalkenyl group, an amino group, an alkylamino group, an alkylsilyl group, or a group other than these groups that represents silicon in the main chain and There is a group in which the group directly bonded to nitrogen is carbon. However, at least one of R1, R2 and R3 is a hydrogen atom.)

【0007】第2の発明は第1の発明のリードフレーム
に半導体チップを搭載し、樹脂封止されてなることを特
徴とする樹脂封止半導体パッケージである。
A second invention is a resin-sealed semiconductor package characterized in that a semiconductor chip is mounted on the lead frame of the first invention and sealed with resin.

【0008】以下、本発明についてさらに詳細に説明す
る。本発明のリードフレームの素材は、例えば42アロ
イなどの鉄/ニッケル系合金や銅系の合金など公知のリ
ードフレーム素材が用いられる。リードフレームの構造
としては、樹脂封止型の半導体パッケージ用のリードフ
レームであれば、その半導体パッケージの構造とともに
特に限定するものではない。DIP(Dual In−
linePackage, デュアルインラインパッケ
ージ)、SIP(Single In−line Pa
ckage, シングルインラインパッケージ)、ZI
P(Zig−Zag In−line Package
, ジグザグインラインパッケージ) 、SOP(Sm
all Outline Package,  スモー
ルアウトラインパッケージ) 、SOJ(Small 
Outline J−leaded Package,
 スモールアウトライン J− リードパッケージ) 
、QFP(Quad Flat Package,  
クワッドフラットパッケージ) 、またはPLCC(P
lastic Leaded Chip Carrie
r, プラスチックリーデッドチップキャリア) など
通常の樹脂封止型半導体パッケージが全て対象となる。 また、TAB(Tape Automated Bon
ding, テープオートメイティッドボンディング)
 、COL(Chip on lead, チップオン
リード) または、LOC(Lead on Chip
, リードオンチップ) 等の金属製リードを含む類似
の部品やその半導体パッケージも本発明に含まれる。
The present invention will be explained in more detail below. As the material of the lead frame of the present invention, a known lead frame material such as an iron/nickel alloy such as 42 alloy or a copper alloy is used. The structure of the lead frame is not particularly limited as long as it is a lead frame for a resin-sealed semiconductor package. DIP (Dual In-
linePackage, dual in-line package), SIP (Single In-line Pa
ckage, single inline package), ZI
P (Zig-Zag In-line Package
, zigzag in-line package), SOP (Sm
all Outline Package, SOJ (Small
Outline J-lead Package,
Small Outline J- Lead Package)
, QFP (Quad Flat Package,
quad flat package) or PLCC (P
Lastic Leaded Chip Carrier
This applies to all ordinary resin-sealed semiconductor packages such as plastic leaded chip carriers. In addition, TAB (Tape Automated Bon
ding, tape automated bonding)
, COL (Chip on lead) or LOC (Lead on Chip)
, lead-on-chip) and similar components including metal leads and their semiconductor packages are also included in the present invention.

【0009】本発明のリードフレームに被覆されるポリ
シラザンは、上記式〔化2〕で表され、分子構造や製造
方法などを限定するものではない。例えば、ジハロシラ
ンとアンモニアとをエーテル溶媒中で反応させて得られ
たポリシラザン(米国特許第4,397,828 号明
細書)ジハロシランと塩基との反応によりアダクトを形
成させた後にアンモニアと反応させて得られたポリシラ
ザン( 特公昭63−16,325 号公報)ジハロシ
ランとメチルアミンをエ−テル溶媒中で反応させて得ら
れたN−メチルポリシラザン(特公表64−500,0
31明細書) 、およびメチルジハロシランとアンモニ
アをジクロロメタン溶媒中で反応させたS−メチルポリ
シラザン(米国特許第 4,482,669号明細書)
などを挙げることができる。
The polysilazane coated on the lead frame of the present invention is represented by the above formula [Formula 2], and the molecular structure and manufacturing method are not limited. For example, polysilazane obtained by reacting dihalosilane and ammonia in an ether solvent (US Pat. No. 4,397,828), polysilazane obtained by reacting dihalosilane with a base to form an adduct, and then reacting with ammonia. N-methylpolysilazane obtained by reacting dihalosilane and methylamine in an ether solvent (Japanese Patent Publication No. 64-500,0)
31 Specification), and S-methylpolysilazane obtained by reacting methyldihalosilane and ammonia in a dichloromethane solvent (U.S. Pat. No. 4,482,669).
etc. can be mentioned.

【0010】使用するポリシラザンは数平均分子量が1
00 〜1000000 の範囲のものが好ましい。ポ
リシラザンは、一般にポリシラザンに不活性な溶媒、例
えばベンゼン、トルエン、キシレンなどの溶媒で希釈し
て使用されるが、100 %のポリシラザンで使用する
こともできる。   ポリシラザンでリードフレームを被覆する方法は特
に限定するものではなく、ディッピング法やスピンコー
ト法などの方法が可能である。膜厚を調製するために、
被覆する方法に応じて溶媒希釈濃度を決定すればよい。 繰り返し塗布し、被覆してもかまわない。
The polysilazane used has a number average molecular weight of 1
A value in the range of 00 to 1,000,000 is preferable. Polysilazane is generally used diluted with a solvent inert to polysilazane, such as benzene, toluene, xylene, etc., but 100% polysilazane can also be used. The method of coating the lead frame with polysilazane is not particularly limited, and methods such as dipping and spin coating are possible. To adjust the film thickness,
The solvent dilution concentration may be determined depending on the coating method. It may be coated repeatedly.

【0011】一方、ポリシラザンはそのままでは安定性
に欠けるため、空気中の水分と反応してポリシラザンが
劣化し、ポリシラザンの特性に経時的障害を来すことが
ある。そこで、安定化処理として焼成を施す必要がある
。この焼成処理によってポリシラザンは架橋または縮合
し、安定な被膜を形成させることができる。焼成条件は
昇温速度 0.1〜50℃/min が好ましく、さら
に好ましくは1 〜10℃/min の範囲で設定すれ
ばよい。焼成温度は100 〜500 ℃、さらに好ま
しくは300 〜400 ℃の範囲である。熱源は抵抗
加熱または高周波加熱などが使用できる。なお、焼成雰
囲気は、空気あるいは窒素ガスなどの不活性ガスまたは
水素、アンモニア等の還元性ガス、あるいはこれらの混
合ガスのいずれでも差し支えない。
On the other hand, since polysilazane lacks stability as it is, it reacts with moisture in the air and deteriorates, which may cause problems in the properties of polysilazane over time. Therefore, it is necessary to perform firing as a stabilizing treatment. This baking treatment crosslinks or condenses the polysilazane to form a stable film. The firing conditions are preferably set at a temperature increase rate of 0.1 to 50°C/min, more preferably 1 to 10°C/min. The firing temperature is in the range of 100 to 500°C, more preferably 300 to 400°C. As the heat source, resistance heating or high frequency heating can be used. Note that the firing atmosphere may be air, an inert gas such as nitrogen gas, a reducing gas such as hydrogen or ammonia, or a mixed gas thereof.

【0012】リードフレームをポリシラザンで被覆する
部分は、基本的には後工程で封止樹脂と界面を形成する
部分であれば特に限定するものではない。けれども、ス
テージと呼ばれる半導体チップを搭載するフレーム部分
の裏面と、封止後、樹脂との界面を形成するリードの部
分面が特に好ましい。なお、これらの処理する面を特定
する場合には、マスクを利用すれば容易に目的を達成で
きる。また、さらに封止樹脂との密着性を向上させるた
めに、リードフレームに、事前に、またはポリシラザン
を塗布し被覆した後に、表面を粗化したり凹凸などを加
える物理的処理をしても差し支えない。また、目的に応
じて本発明のリードフレームをシランカップリング剤な
どで処理しても差し支えない。  本発明の半導体パッ
ケージで用いる封止樹脂は、通常のトランスファー成形
用として市販されている固形のエポキシ系樹脂やシリコ
ーン系樹脂、ビスマレイミド樹脂、ポリイミド系樹脂、
フェノール樹脂または不飽和ポリエステル樹脂などの熱
硬化性樹脂のほか、ポリフェニレンサルファイドやポリ
エーテルイミド、液晶ポリマー、ポリフェニレンエーテ
ル、ポリスルホン、ポリアリールスルホン、ポリイミド
スルホン、ポリエーテルケトン、ポリエーテルエーテル
ケトン、ポリイミド、ポリアミドおよびポリアミドイミ
ドなどの射出成形が可能な熱可塑性樹脂が挙げられる。 また、上述の熱硬化性エポキシ樹脂やシリコーン樹脂な
どでポッティング封止する液状の材料も使用できる。な
かでも、固形の熱硬化性エポキシ樹脂が好適である。
The portion of the lead frame to be coated with polysilazane is not particularly limited as long as it is basically a portion that will form an interface with the sealing resin in a subsequent process. However, particularly preferred is the back surface of a frame portion called a stage on which a semiconductor chip is mounted, and the partial surface of a lead that forms an interface with the resin after sealing. Note that when specifying these surfaces to be processed, the purpose can be easily achieved by using a mask. In addition, in order to further improve the adhesion with the sealing resin, the lead frame may be subjected to physical treatment such as roughening or unevenness on the surface in advance or after coating with polysilazane. . Further, depending on the purpose, the lead frame of the present invention may be treated with a silane coupling agent or the like. The sealing resin used in the semiconductor package of the present invention includes solid epoxy resins, silicone resins, bismaleimide resins, polyimide resins, etc., which are commercially available for normal transfer molding.
In addition to thermosetting resins such as phenolic resins or unsaturated polyester resins, polyphenylene sulfide and polyetherimide, liquid crystal polymers, polyphenylene ethers, polysulfones, polyarylsulfones, polyimide sulfones, polyetherketones, polyetheretherketones, polyimides, and polyamides. and thermoplastic resins that can be injection molded, such as polyamideimide. Furthermore, a liquid material that is potted and sealed with the above-mentioned thermosetting epoxy resin or silicone resin can also be used. Among these, solid thermosetting epoxy resins are preferred.

【0013】[0013]

【実施例】以下、実施例および比較例を挙げて本発明の
リードフレームおよび半導体パッケージを具体的に説明
する。 実施例1〜3、比較例1〜2。鉄/ニッケル系合金(4
2 アロイ)製または銅系のリードフレームをトリクレ
ンで超音波洗浄しアセトンですすぎ、これらの溶剤を乾
燥させた後に、表1に記載した各々の条件にてポリシラ
ザンを塗布し処理した。ここで、表1中、ペルヒドロポ
リシラザンとは式〔化2〕において、R1 ,R2 お
よびR3 は全て水素原子であるポリシラザンを示す。 また、N−メチルポリシラザンとはR1 およびR2 
は水素基、R3 はメチル基であるポリシラザンを示す
EXAMPLES Hereinafter, the lead frame and semiconductor package of the present invention will be specifically explained with reference to Examples and Comparative Examples. Examples 1-3, Comparative Examples 1-2. Iron/nickel alloy (4
2 alloy) or copper-based lead frames were ultrasonically cleaned with trichlene, rinsed with acetone, and after drying these solvents, polysilazane was applied and treated under each of the conditions listed in Table 1. Here, in Table 1, perhydropolysilazane refers to polysilazane in which R1, R2 and R3 are all hydrogen atoms in the formula [Chemical formula 2]. Also, N-methylpolysilazane is R1 and R2
represents a hydrogen group and R3 represents a methyl group, polysilazane.

【0014】[0014]

【表1】[Table 1]

【0015】被覆する方法はキシレンで1%まで希釈し
た上記ポリシラザン溶液に該リ−ドフレ−ムのフレ−ム
部分の裏面以外をマスキング後、ディッピング処理を行
った。ディッピング後、管状炉により窒素およびアンモ
ニア雰囲気の下、昇温速度10℃/min、焼成温度4
00℃で30分間保持した後室温まで冷却した。以上の
様な処理を施した該リードフレームに、対向する櫛形ア
ルミニウム配線の評価用シリコンチップをステージ上に
ボンディングし、さらにワイヤーボンディングし、市販
のエポキシ系封止樹脂をトランスファー成形して封止し
半導体パッケージを作製した。実施例1のリードフレー
ム裏面の部分図を図1(c)、これを用いた半導体パッ
ケージの断面模式図を図1(a)に示す。また、実施例
3の半導体パッケージの断面模式図を図1(b)に示す
。作製した半導体パッケージのリードフレームと樹脂の
■密着性、■耐クラック性( クラック発生個数) お
よび■耐湿信頼性について下記の評価方法で評価した結
果を表1にまとめた。なお、比較例1は従来の鉄/ニッ
ケル系合金(42 アロイ) 製リードフレームの場合
、比較例2は従来の銅系リードフレームの場合である。
[0015] The coating method was to mask the lead frame except for the back side of the frame portion with the above polysilazane solution diluted to 1% with xylene, and then perform a dipping treatment. After dipping, a tube furnace was used in a nitrogen and ammonia atmosphere at a heating rate of 10°C/min and a firing temperature of 4.
After being held at 00°C for 30 minutes, it was cooled to room temperature. A silicon chip for evaluation with opposing comb-shaped aluminum wiring was bonded on the stage to the lead frame treated as described above, wire bonding was further performed, and commercially available epoxy sealing resin was transfer molded for sealing. A semiconductor package was manufactured. A partial view of the back side of the lead frame of Example 1 is shown in FIG. 1(c), and a schematic cross-sectional view of a semiconductor package using this is shown in FIG. 1(a). Further, a schematic cross-sectional view of the semiconductor package of Example 3 is shown in FIG. 1(b). Table 1 summarizes the results of evaluating the lead frame and resin of the fabricated semiconductor package in terms of (1) adhesion, (2) crack resistance (number of cracks generated), and (2) moisture resistance reliability using the following evaluation methods. Note that Comparative Example 1 is a case of a conventional lead frame made of iron/nickel alloy (42 alloy), and Comparative Example 2 is a case of a conventional copper lead frame.

【0016】(評価方法)■密着性 樹脂封止およびアフターキュアした半導体パッケージを
、85℃、相対湿度85%の条件で48時間吸湿させて
から、260 ℃の半田浴中に10秒間浸漬した。取り
出した半導体パッケージの封止樹脂とリードフレームの
ステージ裏面との密着性を超音波探査映像装置で観察し
、次の基準で比較評価した。 全面が密着している                
......  A中央部が密着し周囲は剥離している
  ......  B全面が剥離している     
           ......  C■耐クラッ
ク性( クラック発生個数)■と同様に半田浸漬した半
導体パッケージ10個のうち、外部クラックが発生した
個数を記した。 ■耐湿信頼性 同様にエポキシ樹脂で封止およびアフターキュアした半
導体パッケージを、260 ℃の半田浴に10秒間浸漬
し、20ボルトのバイアス電圧をかけながら、125 
℃の飽和加圧水蒸気雰囲気のバイアスプレッシャークッ
カー試験に供した。各々20個ずつの評価用シリコンチ
ップを搭載した半導体パッケージにて、80時間と20
0 時間後にアルミニウム配線の腐食によってオープン
不良となるパッケージの個数で評価した。
(Evaluation method) (1) Adhesion The resin-sealed and after-cured semiconductor package was allowed to absorb moisture for 48 hours at 85° C. and 85% relative humidity, and then immersed in a 260° C. solder bath for 10 seconds. The adhesion between the encapsulating resin of the removed semiconductor package and the back surface of the lead frame stage was observed using an ultrasonic imaging device, and compared and evaluated using the following criteria. The entire surface is in close contact
.. .. .. .. .. .. The central part of A is adhered and the surrounding area is peeled off. .. .. .. .. .. B The entire surface has peeled off.
.. .. .. .. .. .. C. Crack resistance (Number of cracks generated) Similarly to ■, the number of external cracks generated among the 10 semiconductor packages dipped in solder is recorded. ■Moisture-resistance reliability A semiconductor package sealed with epoxy resin and after-cured in the same way was immersed in a solder bath at 260°C for 10 seconds, and while applying a bias voltage of 20 volts,
It was subjected to a bias pressure cooker test in a saturated pressurized steam atmosphere at ℃. 80 hours and 20 hours in a semiconductor package each equipped with 20 silicon chips for evaluation.
The evaluation was based on the number of packages that became open defects due to corrosion of the aluminum wiring after 0 hours.

【0017】[0017]

【発明の効果】以上のように、本発明のポリシラザンで
被覆されたリードフレームは、封止樹脂との密着性が良
好で、このリードフレームに半導体チップを搭載して樹
脂封止された半導体パッケージは、優れた耐クラック性
および耐湿信頼性を示す。
As described above, the lead frame coated with polysilazane of the present invention has good adhesion with the sealing resin, and a semiconductor package in which a semiconductor chip is mounted on the lead frame and sealed with the resin can be obtained. shows excellent crack resistance and moisture resistance reliability.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】(a)は本発明の一例を示す樹脂封止半導体パ
ッケージの断面図、(b)は同じく本発明の一例を示す
樹脂封止半導体パッケージの断面図、(c)は本発明の
樹脂封止半導体パッケージ用のリードフレームをチップ
搭載面の反対から見た図である。
1(a) is a cross-sectional view of a resin-sealed semiconductor package showing an example of the present invention, (b) is a cross-sectional view of a resin-sealed semiconductor package also showing an example of the present invention, and (c) is a cross-sectional view of a resin-sealed semiconductor package showing an example of the present invention. FIG. 2 is a view of a lead frame for a resin-sealed semiconductor package viewed from the opposite side of the chip mounting surface.

【図2】(a)は従来のリードフレームを用いた樹脂封
止半導体パッケージの断面図、(b)は、従来の封止樹
脂半導体パッケージのリードフレームを示す。
FIG. 2(a) is a cross-sectional view of a resin-sealed semiconductor package using a conventional lead frame, and FIG. 2(b) shows a lead frame of a conventional resin-sealed semiconductor package.

【符号の説明】[Explanation of symbols]

1;リードフレーム 2;リードフレームのステージ 3;ポリシラザンで被覆された部分 4;半導体チップ 5;ボンディングワイヤー 6;封止樹脂 1; Lead frame 2; Lead frame stage 3; Part covered with polysilazane 4; Semiconductor chip 5; Bonding wire 6; Sealing resin

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  下記の式〔化1〕で表される繰り返し
単位を有するポリシラザンで、その表面が被覆されてな
ることを特徴とするリードフレーム。 【化1】 ( 式中、R1 、R2 およびR3 はそれぞれ水素
原子、アルキル基、アルケニル基、シクロアルケニル基
、アミノ基、アルキルアミノ基、アルキルシリル基、ま
たはこれらの基以外で主鎖の珪素および窒素に直結する
基が炭素である基である。ただし、R1 、R2 およ
びR3 の少なくとも1つは水素原子である。)
1. A lead frame, the surface of which is coated with polysilazane having a repeating unit represented by the following formula [Chemical formula 1]. [Formula 1] (In the formula, R1, R2 and R3 are each a hydrogen atom, an alkyl group, an alkenyl group, a cycloalkenyl group, an amino group, an alkylamino group, an alkylsilyl group, or other than these groups, silicon and A group in which the group directly connected to nitrogen is carbon.However, at least one of R1, R2 and R3 is a hydrogen atom.)
【請求項2】  請求項1のリードフレームに半導体チ
ップを搭載し、樹脂封止されてなることを特徴とする樹
脂封止半導体パッケージ。
2. A resin-sealed semiconductor package, characterized in that a semiconductor chip is mounted on the lead frame according to claim 1 and sealed with a resin.
JP11224191A 1991-04-18 1991-04-18 Lead frame and semiconductor package Pending JPH04320055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11224191A JPH04320055A (en) 1991-04-18 1991-04-18 Lead frame and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11224191A JPH04320055A (en) 1991-04-18 1991-04-18 Lead frame and semiconductor package

Publications (1)

Publication Number Publication Date
JPH04320055A true JPH04320055A (en) 1992-11-10

Family

ID=14581780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11224191A Pending JPH04320055A (en) 1991-04-18 1991-04-18 Lead frame and semiconductor package

Country Status (1)

Country Link
JP (1) JPH04320055A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04341705A (en) * 1991-05-16 1992-11-27 Tokyo Ohka Kogyo Co Ltd Inter-layer isolating film
EP0613155A2 (en) * 1993-02-12 1994-08-31 Sumitomo Electric Industries, Limited Heat resistant insulated wire and method of preparing the same
US5358739A (en) * 1993-02-05 1994-10-25 Dow Corning Corporation Coating electronic substrates with silica derived from silazane polymers
US5665643A (en) * 1994-11-15 1997-09-09 Fujitsu Limited Manufacture of planarized insulating layer
US6501158B1 (en) * 2000-06-22 2002-12-31 Skyworks Solutions, Inc. Structure and method for securing a molding compound to a leadframe paddle

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04341705A (en) * 1991-05-16 1992-11-27 Tokyo Ohka Kogyo Co Ltd Inter-layer isolating film
US5358739A (en) * 1993-02-05 1994-10-25 Dow Corning Corporation Coating electronic substrates with silica derived from silazane polymers
EP0613155A2 (en) * 1993-02-12 1994-08-31 Sumitomo Electric Industries, Limited Heat resistant insulated wire and method of preparing the same
EP0613155A3 (en) * 1993-02-12 1994-11-02 Sumitomo Electric Industries Heat resistant insulated wire and method of preparing the same.
US5431954A (en) * 1993-02-12 1995-07-11 Sumitomo Electric Industries, Ltd. Heat resistant insulated wire and method of preparing the same
US5665643A (en) * 1994-11-15 1997-09-09 Fujitsu Limited Manufacture of planarized insulating layer
US6501158B1 (en) * 2000-06-22 2002-12-31 Skyworks Solutions, Inc. Structure and method for securing a molding compound to a leadframe paddle

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