JPH04319815A - Bus circuit - Google Patents

Abstract

PURPOSE:To prevent the conflict of plural signals caused on a bus line by turning on only one of plural tristate buffers. CONSTITUTION:The tristate buffers 10-30 are turned on when the switching signals C11-C31 received from the switching signal generating circuit 11-31 are set at logic '1' and then sent to a bus line 40 for input signals S1-S3. A D-type flip-flop circuits 13-33 set the signals C11-C31 at logic '0' when the reset signals C13-C33 received from the 3-input NAND circuits 14-34 are equal to logic '1'. The 2-input NAND circuits 16-36 generate the trigger signals C12-C32 when the control signals C1-C3 is changed to logic '1' from logic '0' and then transmit these trigger signals to the circuits 14-34 of other switching signal generating circuits. Then the circuits 14-34 set the signals C13-C33 at logic '1' when the trigger signals are received from other switching signal generating circuits.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus circuit for logic circuits, and more particularly to a bus circuit that selects one of a plurality of input signals in accordance with a control signal and outputs the selected signal via a bus line.

0002

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional bus circuit, in which a tri-state buffer 51 operates on and off in response to control signals C1 to C3 and sends input signals S1 to S3 to a bus line 50, respectively. ~53, and an output buffer 54 that receives and outputs a signal from the bus line 50.
It is made up of. Tri-state buffer 51-5
3 is in an on state and outputs an input signal when the control signals C1 to C3 are logic "1". In addition, control signals C1 to C3
When is logic "0", it is in an off state and does not output an input signal.

0003

[Problems to be Solved by the Invention] As described above, in the conventional bus circuit, when two or more control signals become logic "1", a plurality of tri-state buffers are turned on, and each Since the signal is sent to the bus line, a plurality of signals are simultaneously output on the bus line and compete with each other, resulting in an undefined state. Therefore, if different signals compete with each other, not only will the state of the bus line become unstable and malfunction, but in the worst case, an excessive current will flow through the output section of the tri-state buffer, causing it to burn out. .

An object of the present invention is to provide a bus circuit in which a plurality of signals do not compete on a bus line even if two or more control signals are at logic "1".

[0005]

A bus circuit according to the present invention receives a plurality of input signals and a plurality of control signals corresponding to each input signal, and selects one of the plurality of input signals in response to the plurality of control signals. The bus circuit selects and sends the input signal to the bus line, and includes a plurality of switch circuits that are provided corresponding to each of the input signals and turn on and off in response to a switching signal to send the input signal to the bus line; a plurality of switching signal generation circuits provided corresponding to the switch circuits and generating the switching signals according to the control signals, the switching signal generation circuits including a delay circuit that provides a predetermined delay to the input control signal; , receives a reset signal and the output signal of the delay circuit, and when the reset signal instructs reset, outputs the switching signal that turns off the switch circuit, and when the reset signal instructs reset release, outputs the switching signal, and when the reset signal instructs reset cancellation, outputs the switching signal. a flip-flop circuit that outputs the switching signal that turns on the switch circuit in accordance with an output signal of the circuit; means for generating a trigger signal by inverting the output logic level by a certain amount of time; and means for generating the reset signal by receiving the input control signal and the trigger signal generated by another switching signal generation circuit. It is configured. Further, the trigger signal generation means includes an inverter that inverts the logic level of the switching signal output from the flip-flop circuit, and an output signal of the inverter at one input terminal and an output signal of the delay circuit at the other input terminal. 2 inputs N that receive the signal and output the negative product as the trigger signal.
and an AND circuit, and the reset signal generation means receives the input control signal at one of the plurality of input terminals and outputs the two input NA of the other switching signal generation circuit at the other input terminal.
The configuration may include a multi-input NAND circuit that receives an output signal from an ND circuit and outputs a negative product as the reset signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which switching signal generating circuits 11, 21, 31 generate switching signals C11, C21, C31 in response to input control signals C1, C2, C3. and switching signals C11, C21, C
31 to turn on and off the input signals S1, S2, S.
3 to the bus line 40, and an output buffer 41 that receives signals from the bus line 40 and outputs them.

[0008] Furthermore, the switching signal generation circuits 11, 21, 31
are the delay circuits 12, 22, 32 and the switching signals C11, C
D-type flip-flop circuit 13 outputting 21, C31
, 23, 33 and 3-input NAND circuits 14, 24, 34
, inverters 15, 25, and 35, and two-input NAND circuits 16, 26, and 36, respectively. here,
The delay circuits 12, 22, 32 receive input control signals C1,
By giving a predetermined delay to C2 and C3 respectively, the signals C10,
C20, C30, D type flip-flop circuit 13,
The signals are sent to input terminals C of 23 and 33, respectively. 3 inputs N
The AND circuits 14, 24, and 34 receive control signals C1, C2, and C3 input to each switching signal generation circuit at one input terminal, and receive trigger signals from other switching signal generation circuits at the other two input terminals. Upon receiving C12, C22, and C32, reset signals C13, C23, and C33 are generated and sent to the reset terminal R of the D-type flip-flop circuit, respectively. 2 inputs N
The AND circuits 16, 26, 36 receive switching signals C11, C21 via inverters 15, 25, 35 at one input end.
, C31, and the other input terminal receives signals C10, C20.
, C30 and generates trigger signals C12, C22, C32, and 3-input NAND circuit 1 of the other switching signal generation circuit.
4, 24, and 34, respectively.

Next, the operation will be explained.

FIG. 2 is a timing chart for explaining the operation of the bus circuit shown in FIG.
, C2, and C3 change from logic "0" to "1" at times T1, T2, and T3, respectively. Here, the tristate buffers 10, 20, and 30 are in an on state and output an input signal when the switching signals C11, C21, and C31 are logic "1", but are in an off state and input an input signal when the switching signals C11, C21, and C31 are logic "0". Functions as a switch circuit that does not output signals.

First, until time T1, control signals C1 and C
2 and C3 are all logic “0”, so 2-input NAND
circuits 16, 26, 36 and 3-input NAND circuit 14,
The outputs of 24 and 34 are all logic "1". Therefore, the D-type flip-flop circuits 13, 23, and 33 enter the reset state upon receiving the logic "1" reset signal.
Since switching signals C11, C21, and C31 of logic "0" are output, tristate buffers 10, 20, and 30 are all turned off, and no input signal is sent to bus line 40.

Now, at time T1, the control signal C1 becomes logic "1" and all the inputs of the 3-input NAND circuit 14 become logic "1", so the reset signal C13 becomes logic "0".
becomes. Therefore, the D-type flip-flop circuit 13 enters the reset release state, and the signal C10 supplied to the input terminal C
When the switching signal C11 rises from logic "0" to "1"
is set to logic "1".

By the way, the two-input NAND circuits 16 and 26
, 36, when the signals C10, C20, C30 are respectively logic "0" and the switching signals C11, C21, C31
When each is logic "1", logic "1" is output. However, at time T1, the signal C10 input to the 2-input NAND circuit 16 and the output of the inverter 15 both become logic "1" until the output of the D-type flip-flop circuit 13 is set to logic "1". Therefore, 2
Input NAND circuit 16 sets the output level to logic "0" to generate trigger signal C12, and sends it to three-input NAND circuits 24 and 34. At this time, the 3-input NAND circuit 24
, 34 have already received the control signals C2, C3 of logic "0", so the outputs (reset signals C23, C33) remain logic "1" and do not change. Therefore, only the switching signal C11 becomes logic "1", so only the tri-state buffer 10 is turned on, and the input signal S1 is sent to the bus line 40.

At time T2, the control signal C2 changes to the logic "
Since all the inputs of the 3-input NAND circuit 24 become logic "1", a reset signal C23 of logic "0" is output, and the D-type flip-flop circuit 23 is brought into a reset release state. The D-type flip-flop circuit 23 receives the signal C
When 20 rises from logic "0" to "1", switching signal C
21 to logic "1". At this time, 2 input NA
The ND circuit 26 generates a trigger signal C22 with the output level set to instantaneous logic "0" as in the case of time T1, and sends it to the three-input NAND circuits 14 and 34. 3 input NA
The ND circuit 14 instantaneously sets the reset signal C13 to logic "1" in response to the logic "0" trigger signal C22, resets the D-type flip-flop circuit 13, and outputs the switching signal C11.
is set to logic "0". On the other hand, since the 3-input NAND circuit 34 has already received the control signal C3 of logic "0", even if it receives the trigger signal C22 of logic "0", the output signal C33
remains at logic "1". Therefore, the switching signal C11 changes from logic "1" to "0", the switching signal C21 changes from logic "0" to "1", and the switching signal C31 remains logic "0", so the tri-state buffer 10
, 30 are in the off state, only the tri-state buffer 20 is in the on state, and only the input signal S2 is sent to the bus line 40.

At time T3, the control signal C3 becomes logic "1".
'' and operates in the same manner as at time T2, the tri-state buffer 20 is turned off, only the tri-state buffer 30 is turned on, and only the input signal S3 is sent to the bus line 40.

Furthermore, at time T4, the control signal C3 becomes logic "0" and the reset signal C33 from the 3-input NAND circuit 34 becomes logic "1", so the D-type flip-flop circuit 33 is reset and the switching signal is C31 becomes logic "0". Therefore, the tristate buffer 30 is turned off and the transmission of the input signal S3 is stopped.

As described above, when a plurality of control signals corresponding to a plurality of input signals sequentially change from logic "0" to "1", priority is given to the control signal that changes to logic "1" later. A switching signal can be generated to turn on one of the plurality of tri-state buffers.

In this embodiment, the case where there are three input signals and three control signals has been described, but by providing a tri-state buffer and a switching signal generation circuit according to the input signals and control signals, it is possible to generate three or more input signals and three control signals. Can handle input signals and control signals. Further, instead of the D-type flip-flop circuit, an S-R type flip-flop circuit provided with a differentiating circuit can be used to operate in the same manner.

[0019]

As explained above, according to the present invention, a plurality of flip-flop circuits are provided corresponding to a plurality of control signals, and a plurality of switch circuits are controlled by switching signals generated by the flip-flop circuits. By generating a trigger signal and resetting other flip-flop circuits when changing this switching signal, only one of the multiple switch circuits is turned on, giving priority to the control signal that changed later. A switching signal can be generated. Therefore,
Signals from a plurality of switch circuits do not compete on the bus line, and different signals do not compete with each other, making the state of the bus line unstable and causing malfunctions, unlike in the past. Furthermore, when a tri-state buffer is used as a switch circuit, it is possible to prevent excessive current from flowing to the output section of the tri-state buffer and causing it to burn out.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the bus circuit of this embodiment.

FIG. 3 is a block diagram showing an example of a conventional bus circuit.

[Explanation of symbols]

10, 20, 30 tri-state buffer 11
, 21, 31 switching signal generation circuit 12, 22, 3
2 Delay circuits 13, 23, 33 D-type flip-flop circuit 1
4, 24, 34 3-input NAND circuit 15, 25
,35 inverter

Claims (2)

[Claims] 1. A bus circuit that receives a plurality of input signals and a plurality of control signals corresponding to each input signal, selects one of the plurality of input signals according to the plurality of control signals, and sends it to a bus line. a plurality of switch circuits provided corresponding to each of the input signals and operating on and off in response to a switching signal to send the input signal to the bus line; and a plurality of switch circuits provided corresponding to each of the switch circuits and configured to send the input signal to the bus line. a plurality of switching signal generation circuits that generate the switching signals according to the input control signal; When the received reset signal instructs reset, outputs the switching signal to turn off the switch circuit, and when the reset signal instructs reset cancellation, outputs the switching signal according to the output signal of the delay circuit. A flip-flop circuit outputs the switching signal to turn on the switch circuit, and when the switching signal from the flip-flop circuit changes to turn the switch circuit on, the output logic level is inverted for a predetermined period of time to generate a trigger signal. and means for generating the reset signal by receiving the input control signal and the trigger signal generated by another switching signal generation circuit. 2. The trigger signal generating means includes an inverter that inverts the logic level of the switching signal output from the flip-flop circuit, and an inverter that receives the output signal of the inverter at one input terminal and the delay circuit at the other input terminal. and a two-input NAND circuit that receives the output signal of the input terminal and outputs the negative product as the trigger signal, and the reset signal generating means receives the input control signal at one of the plurality of input terminals and outputs the negative product as the trigger signal. The two inputs N of the other switching signal generation circuit are connected to the input terminal.
2. The bus circuit according to claim 1, further comprising a multi-input NAND circuit that receives an output signal from an AND circuit and outputs a negative product as the reset signal.