JPH07182075A - Bus enable control circuit provided with bus state monitoring function - Google Patents

Abstract

PURPOSE:To reduce loads connected to a bus by providing a specific transfer gate means and an enable control signal generation means. CONSTITUTION:This bus enable control circuit 5 is composed of an enable control signal generation circuit 6 and a transfer gate circuit 7. Then, a transfer gate 8 is in an on state at the point of time when enable signals E fall from a high level to a low level, the output of a NAND gate 11 becomes the high level when bus level signals BL are logical '0', a bus driver circuit 1 is turned to bus disable and the transfer gate 8 maintains the on state. Also, when the bus level signals BL are logical '1' at the point of time when the enable signals E fall from the high level to the low level, enable control signals EC are turned to the low level, the bus driver circuit 1 is turned to bus enable (output enable), also the transfer gate 8 is turned to an off state and the bus enable control circuit 5 is cut off from the bus 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus enable control circuit for controlling output enable of a bus driver circuit, and more particularly to a bus enable control circuit having a bus state monitoring function for avoiding a bus fight.

[0002]

2. Description of the Related Art In a multi-bus type device in which a plurality of tri-state bus drivers and a plurality of tri-state bus receivers are connected to the same bus to transmit and receive data in a time division process, bus control is usually performed by bus enable. This is performed by an output enable signal (enable control signal) generated by the control circuit, and the data output from different bus drivers is controlled so as not to collide on the bus. Therefore, the device timing is designed such that only one of the bus drivers is in the output enable state at any time.

In such a multi-bus type device, the higher the operating speed of the device, the more difficult it becomes to design the device timing for enabling only one of the plurality of bus drivers. As a result, Multiple bus drivers are enabled at the same time on the bus, resulting in a bus fight phenomenon in which data output from different bus drivers collide on the bus, which causes device malfunction and bus driver damage. .

In recent years, many inventions have been made in order to prevent the bus fight phenomenon, and a typical invention is described in Japanese Patent Laid-Open No. 1-117541.

In the bus fight prevention circuit described in this publication, the output enable signal is either 1) the bus is in a floating state (high impedance state), or 2) the data signal on the bus is the output enable signal. When it is detected that it is a signal output from the bus driver controlled by (not a signal output from another bus driver), it becomes active and enables the bus driver. this house,
In order to detect 2), the data signal before input to the bus driver is delayed by a time corresponding to the propagation delay time of the bus driver, and the delayed data signal (hereinafter referred to as a delayed data signal). ) Is compared with the current logic state of the bus, and when they match, the signal currently on the bus is the data output by that bus driver, and thus other bus drivers are currently output enabled. Judge not to. Hereinafter, a period in which two or more bus drivers are simultaneously output-enabled is referred to as a multiple enable period.

If the logical state of the delayed data signal is different from the logical state of the bus, it is determined that the multiple enable period is currently set, and the bus driver is disabled for output. Therefore, the output of the bus driver is enabled only during the period other than the multiple enable period of the period designated as the period for which the bus driver should use the bus (hereinafter, referred to as the bus use period). Is prevented.

[0007]

The above-described conventional bus enable control circuit (bus fight prevention circuit) has the following features: 1) When the bus is in the floating state during the bus use period, 2) When the bus is in the floating state, When not in the floating state, the bus driver is configured to enable output only when the data signal on the bus matches the delayed data signal of the bus driver. As a result, during the output enable period of the bus driver, even if the bus driver is outputting the data signal, the bus driver outputs the data signal on the bus output by itself and the delay data corresponding to the data signal. The output enable state cannot be maintained unless a match with the signal is detected.

As described above, while the bus enable control circuit controls the bus driver so as to output the data signal on the bus on the one hand, the data signal on the bus is output from the bus driver on the other hand. There is a problem in that unnecessary monitoring of monitoring whether or not the signal is a data signal must be performed. Further, such unnecessary monitoring causes a problem that the load connected to the bus becomes unnecessarily large.

Further, there is a problem that the above-mentioned conventional bus enable control circuit cannot be used for the multi-bus in the electronic exchange. As is well known, according to the multi-bus standard used in electronic exchanges, the bus assumes a potential corresponding to a logical one in the floating state. Therefore, the device that detects the floating state of the bus at the intermediate potential between the logic 1 and the logic 0, like the bus fight prevention circuit, cannot be used in the electronic exchange.

An object of the present invention is to provide a bus enable control circuit having a bus state monitoring function for avoiding a bus fight, which can be used for controlling a multi-bus in an electronic exchange, has a small load connected to the bus. To do.

[0011]

In order to achieve the above object, a bus enable control circuit with a bus state monitoring function of the present invention comprises a plurality of tristate bus drivers connected to the same bus in a multibus format. A control circuit for controlling the output of each of the
A bus enable control circuit that enables an output of a bus driver by an enable control signal of a second logic level and sets an output of the bus driver to a high impedance state by an enable control signal of a first logic level, which corresponds to a logical state of a bus. Transfer gate means for inputting the bus level signal, outputting the bus level signal when the enable control signal is at the first logic level, and interrupting transmission of the bus level signal when the enable control signal is at the second logic level; An enable signal for instructing the use of the bus and the output of the transfer gate means are input, and when the enable signal is at the first logic level, and the enable signal is at the second logic level, and the transfer gate means If the output is at the second logic level, the Output enable control signal of the second logic level when the enable signal is the second logic level and the output of the transfer gate means is the first logic level. It has enable control signal generation means for outputting a signal.

[0012]

The operation of the bus enable control circuit of the present invention is as follows.
(A) If the enable signal is at the first logic level,
(B) If the enable signal is at the second logic level and the bus level signal is at the second logic level, (c) the enable signal is at the second logic level and the bus level signal is at the first logic level. It can be divided into three cases of the logical level.

In the case of (a), the enable control signal generating means sets the enable control signal to the first logic level. As a result, the output of the bus driver is set to a high impedance state (output disabled) and the transfer gate means is turned on to transmit the bus level signal to the bus enable control circuit. In this way, the bus enable control circuit monitors the logical state of the bus during the output disable period of the bus driver.

At the time when the enable signal transits from the first logic level to the second logic level, the transfer gate means is still in the on state and transmits the bus level signal to the enable control signal generating means. At this time, if the bus level signal is at the second logic level, it corresponds to the case of (b). In this case, the enable signal is the first
Then, the bus driver is disabled, and the transfer gate means continues to be in the ON state. Therefore, the second level of the bus level signal
When the logic level of is set in correspondence with the non-floating state of the bus, a bus fight between another bus driver and the bus driver can be avoided.

When the enable signal transits from the first logic level to the second logic level, the bus level signal becomes the first level.
The case of the logic level of (c) is the case of (c). In this case, the bus driver is output enabled and the transfer gate means is turned off. In this way, while the bus driver is outputting the data signal,
The bus enable control circuit is decoupled from the bus level signal to avoid the bus enable control circuit from performing unnecessary bus status monitoring. When the first logic level of the bus level signal is made to correspond to the floating state of the bus,
When the enable signal transitions from the first logic level to the second logic level, the bus driver is output enabled and the data signal is normally output on the bus. At this time, the transfer gate means is turned off, and the bus level signal is not input thereafter, so the transfer gate means continues to be turned off until the enable signal next becomes the first logic level.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment of a bus enable control circuit with a bus state monitoring function of the present invention and a bus driver circuit whose output enable is controlled by the bus enable control circuit.

The bus driver circuit 1 is a tri-state output bus driver circuit. When the enable control signal EC is at a low level, the bus driver circuit 1 outputs a data signal of logic 1 or logic 0 having a low output impedance to enable the control signal. When EC is high level, the output part of the bus driver circuit 1 is in a high impedance state. The data signal is input to the bus driver circuit 1 from the bus input terminal 2 and is output to the bus 4 from the bus output terminal 3.

The bus enable control circuit 5 comprises an enable control signal generation circuit 6 and a transfer gate circuit 7. The enable control signal generation circuit 6 includes a 2-input NAND gate 11 and an inverter 10. Inverter 1
0 inverts and outputs the enable signal E input from the enable signal input terminal 9. NAND gate 11
Inputs the inverted enable signal output from the inverter 10 to the first input terminal, and the transfer gate circuit 7
Is input to the second input terminal, an inverted logical product (NAND) of these two input signals is generated and output as the enable control signal EC.

The transfer gate circuit 7 includes a transfer gate 8. The bus level signal BL is input to the data input terminal of the transfer gate 8, and its output terminal is connected to the second input terminal of the NAND gate 11. The bus level signal BL is a signal indicating the logical state of the bus. In this embodiment, the data input terminal of the transfer gate 8 is directly connected to the bus. Therefore, the logical value of the bus is the logical value of the bus level signal BL as it is. Also, in the present embodiment, the floating state of the bus is set to logic 1.

The transfer gate 8 is on / off controlled by the enable control signal EC, is turned on when the enable control signal EC is at a high level, and transmits the bus level signal BL to the second input terminal of the NAND gate 11. . Further, when the enable control signal EC is low level, it is turned off and the bus enable control circuit 5 is disconnected from the bus 4.

The enable signal E is a signal for designating the bus use right of the bus driver circuit 1, and its low level period indicates a period in which the bus use right belongs to the bus driver circuit 1. When the enable signal E is at high level ((a)
In the case of), the enable control signal EC output from the NAND gate 11 becomes the high level regardless of the logical value of the output of the transfer gate circuit 7. As a result, the output of the bus driver circuit 1 is in a high impedance state, and the bus is disabled (output disabled). At the same time, the transfer gate 8 is turned on, and the bus level signal BL is input to the bus enable control circuit 5 via the transfer gate 8 and monitored by the bus enable control circuit 5.

At the time when the enable signal E falls from the high level to the low level, the transfer gate 8
Is still on. At this time, if the bus level signal BL sent through the transfer gate 8 is logic 0 (in the case of (b)), the NAND gate 1
The output of 1 goes high, and as a result, the bus driver circuit 1 is disabled and the transfer gate 8 remains on, as when the enable signal E is high. As described above, in the present embodiment, the bus is in the logic 1 state when floating, so that the logic 0 of the bus level signal BL is generated by other bus driver circuits (bus driver circuits other than the bus driver circuit 1). This means that a logic 0 data signal is being output on the bus. Therefore, in this case, the bus driver circuit 1 is disabled to avoid a bus fight between the bus driver circuit 1 and the other bus driver circuit outputting the data signal on the bus. be able to.

At the time when the enable signal E falls from the high level to the low level, if the bus level signal BL transmitted through the transfer gate 8 is logic 1 (case (c)), the enable control is performed. Signal EC
Becomes low level, the bus driver circuit 1 becomes bus enable (output enable), the transfer gate 8 becomes off state, and the bus enable control circuit 5 is disconnected from the bus 4. In this way, while the bus driver circuit 1 is outputting the data signal 1, unnecessary bus state monitoring is stopped to reduce the load connected to the bus.

In this embodiment, since the data input terminal of the transfer gate is connected to the bus, the logical value of the bus becomes the logical value of the bus level signal as it is. Therefore, the logic 1 of the bus level signal corresponds to both the floating state of the bus and the state in which the data signal of the logic 1 is output from the other bus driver, and the two cannot be distinguished. . Therefore, in the case of (c), when the bus driver circuit 1 outputs a data signal in response to the state of the logic 1 of the bus level signal BL, if the logic 1 of the bus is a signal indicating the floating state of the bus. In this case, normal data transmission is performed, but if the logic 1 of the bus is the logic 1 of the data signal output by another bus driver circuit, the bus fight cannot be avoided. However, the above (b)
When the enable signal E falls from the high level to the low level as in the case of, the bus level signal BL is set to logic 0.
In this case, since the bus fight can be avoided, the circuit of this embodiment statistically halves the bus fight.

Next, a second embodiment of the present invention will be described. The bus enable control circuit of this embodiment is the same as that of the first embodiment, but the bus level signal BL is not used as the logical value of the bus as it is, but is generated by the bus level signal generation circuit separated from the bus. Bus level signal B
The difference from the first embodiment is that L is generated.

The bus level signal generating circuit of this embodiment includes a logical product gate circuit of the enable control signals EC of all the bus driver circuits connected to the bus.
Therefore, all enable control signals EC are logic 1
, That is, when the outputs of all the bus driver circuits become high impedance, and as a result, the bus becomes a floating state, the logical product gate circuit outputs a logical 1
Output the bus level signal of. Further, if even one of the enable control signals EC is a logic 0, the AND gate circuit outputs a bus level signal of a logic 0. By this bus level signal BL, bus fight can be completely avoided without connecting a load to the bus.

[0027]

As described above, the present invention controls the input of the bus level signal indicating the bus state to the bus enable control circuit by the enable control signal for controlling the output enable function of the bus driver circuit, When the enable control signal indicates output disable of the bus driver circuit, the bus enable control circuit monitors the bus state, and when the enable control signal indicates output enable of the bus driver circuit, bus enable control The circuit stops monitoring the bus state, and the bus enable control circuit controls the bus driver circuit from the output disable state to the output enable state by avoiding the bus fight based on the monitored bus state. In addition, the bus enable control circuit During the output enable period screwdriver, it has the effect of that can reduce the load of the circuit to avoid unnecessary bus status monitoring.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a bus enable control circuit with a bus state monitoring function of the present invention and a bus driver circuit whose output enable is controlled by the bus enable control circuit.

[Explanation of symbols]

 1 bus driver circuit 2 bus input terminal 3 bus output terminal 4 bus 5 bus enable control circuit 6 enable control signal generation circuit 7 transfer gate circuit 8 transfer gate 9 enable signal input terminal 10 inverter 11 NAND gate E enable signal EC enable control signal BL Bus level signal

Claims (4)

[Claims] 1. A plurality of tri-state bus drivers connected to the same bus in a multi-bus form,
A control circuit for controlling output by an enable control signal, wherein a bus driver output is enabled by a second logic level enable control signal, and a bus driver output is set to a high impedance state by a first logic level enable control signal. In the bus enable control circuit, a bus level signal corresponding to the logical state of the bus is input, and when the enable control signal is at the first logical level,
A bus level signal is output, and transfer gate means for interrupting transmission of the bus level signal when the enable control signal is at the second logic level; and an enable signal for instructing use of the bus and an output of the transfer gate means are input, A first logic if the enable signal is at a first logic level and if the enable signal is at a second logic level and the output of the transfer gate means is at a second logic level. A level enable control signal is output, and when the enable signal is at the second logic level and the output of the transfer gate means is at the first logic level, the enable control for the second logic level is performed. A bus enable control circuit having enable control signal generating means for outputting a signal. 2. The enable control signal generating means has a logical product gate circuit for inputting the enable signal and the output signal of the transfer gate means to the first and second input terminals, respectively. When the first input terminal is at the first logic level, the enable control signal of the first logic level is output regardless of the logic state of the second input terminal, and the first input terminal is at the second logic level. In the case of the level, when the second input terminal is the first logic level, the enable control signal of the second logic level is output, and when the second input terminal is the second logic level, the first logic level The bus enable control circuit according to claim 1, which outputs an enable control signal. 3. The floating state of the bus corresponds to the first logic level of the bus level signal, and the second logical level of the bus level signal corresponds to the non-floating state of the bus. Bus enable control circuit. 4. The bus enable control according to claim 1, wherein the bus level signal is generated by an AND circuit that receives all enable control signals for controlling a bus driver connected to the bus. circuit.