JPH04207238A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction for clock switching and to improve the operability by providing a frequency comparing circuit and automatically discriminating frequencies of a reference clock and a clock input to perform switching. CONSTITUTION:When a frequency f1 of the reference clock is lower than a frequency f2 of the clock input, a frequency comparing circuit 6 outputs the high level. When a reset input is asserted, a timer 4 is reset and outputs OUT1 and OUT2 go to the low level. An FF circuit 5 is reset by the output OUT1, and a selector 2 selects the clock input side. When the reset input is negated, the timer 4 starts counting, and the output of the comparator 6 is latched in the circuit 5 at the timing of the output OUT1. The selector selects the clock input side by the output of the circuit 5. When the frequency f1 is higher than the frequency f2, the circuit 6 outputs the low level to select the reference clock side. Thus, clocks are automatically switched to prevent the malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock switching circuit for selecting and using a clock when the clocks combined for each system are different.

(Prior Art) Fig. 2 is a circuit diagram of a conventional clock switching circuit. In the figure, (1) is a changeover switch, (2) is a reference clock and a clock input, and a selector for selecting one based on the switching signal;
(3) is a pull-up resistor connected to the select terminal of the selector (2).

Next, the operation will be explained. When the selector switch (1) is turned off, the select terminal of the selector (2) is brought to a high level by the pull-up resistor (3). As a result, the selector (2) selects the clock input at the B input terminal and outputs the clock to the output Y.

On the other hand, when the changeover switch (1) is turned on, the selector (2
) select terminal becomes low level, selector (2)
selects the reference clock on the A input side and outputs the clock to output Y.

[Problem to be Solved by the Invention] Since the conventional clock switching circuit is configured as described above, when it is desired to output either the clock input or the reference clock, whichever is faster or slower, as the clock output, it is necessary to switch between the clock input and the reference clock. It is necessary to compare the clock frequencies and switch manually.When switching, in order to avoid malfunctions due to noise that appears on the clock output, it is necessary to reset the circuit using the clock output or turn off the power. Is there a problem such as whether it is necessary to turn on the power after switching the switch while it is running?

Also, JP-A-60-105937 and JP-A-61-1
Publication No. 05938 discloses a technique for selecting a clock by using a circuit configuration such as a flip-flop, a selection circuit, and a timer. Nothing has been done.

This invention was made to solve the above-mentioned problems, and it is possible to automatically determine the frequency of the reference clock and clock input and output it to the clock output, and also prevents erroneous operation when switching, improves operability, The purpose of this invention is to obtain a clock switching circuit that prevents malfunction.

(Means for Solving the Problems) A clock switching circuit according to the present invention includes a frequency comparison circuit that compares the frequencies of a reference clock and another clock, a timer that is activated by inputting a reset signal, and an output of the frequency comparison circuit. It is equipped with a flip-flop that latches the clock using the output of a timer, and a selector that uses the output of this flip-flop to switch between the reference clock and other clocks.

(Function) In this invention, the clock input is compared with the reference clock by the frequency comparison circuit, and at the time of reset, the clock switching timing is generated by the timer, the output of the frequency comparison circuit is held, and the clock output of the selector is switched. .

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1, in which the same parts as in FIG. 2 are denoted by the same reference numerals. In Figure 1, (6) is a frequency comparison circuit that compares the clock input and the reference clock, (4) is a timer, and (5) is a flip-flop that holds the output of the frequency comparison circuit (6) as the output of timer (4). (2) is a selector that selects the clock input and reference clock using the output of this flip-flop (2);
(7) is an OR gate that ORs the reset input and the output of timer (4).

Next, the operation will be explained. The frequency of the reference clock is f
1, and the frequency of the clock input is 12. When the frequency fl of the reference clock is slower than the frequency 12 of the clock input, that is, when f2>fl, the frequency comparison circuit (6) outputs a high level. When the reset input is asserted in the reset operation, the timer (4) is reset, and its outputs 01JTI and 0UT2 become low level. The flip-flop (5) is reset at 0LITI, and the selector (2) selects the reference clock side. When the reset input is negated, timer (4) starts counting. The reset output remains at a low level due to the output 01172 of the timer (4) input to the OR gate (7). Also, the output 0UTI of the timer (4) is output in a shorter time than 0OT2, and at the timing of this output 0UTI, the output of the frequency comparator (6) is output from the flip-flop (5).
) latches. The output of the flip-flop (5) is sent to the selector (2), which selects the clock input side and outputs it to the clock output. After that, timer (4) output 0
LIT2 becomes high level and the reset output is negated via the OR gate (7).

Next, when the frequency f1 of the reference clock is faster than the frequency f2 of the clock input, that is, when f2≦f1, the frequency comparison circuit (6) outputs a low level. When the reset input is asserted in the reset operation, the timer (4) is reset, and its outputs 0[JTl, 0LIT2 become low level. The flip-flop (5) is reset at 0IITI, and the selector (2) selects the reference clock side. When the reset input is negated, the timer (4
) starts counting. The reset output is an OR gate (
It remains at a low level due to the output OυD2 of the timer (4) inputted to 7). The flip-flop (5) latches the output of the frequency comparator (6) at the timing of the output 0UTI of the timer (4).

The output of the flip-flop (5) is sent to the selector (2), and the reference clock side is selected and output to the clock output. Thereafter, the output 0UT2 of the timer (4) becomes high level and the reset output is negated via the OR gate (7).

In the above embodiment, the case where the faster one of the reference clock and the clock input is selected is explained, but the same effect can be obtained even if the slower one is selected.

(Effects of the Invention) As described above, according to the present invention, since the frequency of the reference clock and the clock input is automatically switched at the reset timing, even if the clock input is changed, the frequency remains unchanged. Correspondingly, the clock output can be automatically switched, which has the effect of eliminating the possibility of malfunction of subsequent circuits that use the clock output.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clock switching circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional clock switching circuit. (1) is a changeover switch, (2) is a selector, (3) is a pull-up resistor, (4) is a timer, (5) is a flip-flop, (6) is a frequency comparison circuit, and (7) is a selector. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A frequency comparison circuit that compares the frequency of the reference clock and other clocks, a timer that is started by inputting a reset signal, a flip-flop that latches the output of the frequency comparison circuit with the output of the timer, and a reference clock that uses the output of this flip-flop. A clock switching circuit with a selector that switches between one clock and another clock.