JPH04318921A - Manufacture of polycrystalline silicon film - Google Patents
Manufacture of polycrystalline silicon filmInfo
- Publication number
- JPH04318921A JPH04318921A JP8524991A JP8524991A JPH04318921A JP H04318921 A JPH04318921 A JP H04318921A JP 8524991 A JP8524991 A JP 8524991A JP 8524991 A JP8524991 A JP 8524991A JP H04318921 A JPH04318921 A JP H04318921A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gas
- poly
- substrate
- hydrogen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000007789 gas Substances 0.000 claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 23
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000001257 hydrogen Substances 0.000 claims abstract description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 24
- 230000004913 activation Effects 0.000 claims description 4
- 230000005284 excitation Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 32
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 14
- 239000011521 glass Substances 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 11
- 238000002844 melting Methods 0.000 abstract description 9
- 229910000077 silane Inorganic materials 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 6
- 229910052736 halogen Inorganic materials 0.000 abstract description 5
- 150000002367 halogens Chemical class 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 238000002156 mixing Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 239000012495 reaction gas Substances 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000007865 diluting Methods 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 230000008018 melting Effects 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 238000005755 formation reaction Methods 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 239000007790 solid phase Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- XPBBUZJBQWWFFJ-UHFFFAOYSA-N fluorosilane Chemical compound [SiH3]F XPBBUZJBQWWFFJ-UHFFFAOYSA-N 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910008045 Si-Si Inorganic materials 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 229910005096 Si3H8 Inorganic materials 0.000 description 1
- 229910006411 Si—Si Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Chemical Vapour Deposition (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は薄膜トランジスタ等の半
導体素子に応用できる多結晶シリコン薄膜の製造方法に
関し、特に低温で低融点ガラス等の基板上に形成できる
多結晶シリコン薄膜の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing polycrystalline silicon thin films that can be applied to semiconductor devices such as thin film transistors, and more particularly to a method for manufacturing polycrystalline silicon thin films that can be formed at low temperatures on substrates such as low-melting glass.
【0002】0002
【従来の技術】低融点ガラス基板上に、微結晶または多
結晶Si(poly−Si)を素子材とした高性能な薄
膜トランジスタ(TFT)を作成する試みが活発化して
いる。特に、基板としてコーニング社製7059基板等
の低融点ガラス基板を用い、プロセスの最高温度450
℃程度以下で、高易動度、高ON/OFF比のTFTを
作成するプロセスの実用化が待望されている。2. Description of the Related Art Attempts are being made to create high-performance thin film transistors (TFTs) using microcrystalline or polycrystalline Si (poly-Si) as element materials on low-melting point glass substrates. In particular, a low melting point glass substrate such as Corning's 7059 substrate is used as the substrate, and the maximum temperature of the process is 450°C.
The practical application of a process for producing TFTs with high mobility and a high ON/OFF ratio at temperatures below about 0.degree. C. is eagerly awaited.
【0003】従来poly−Siをガラス基板上に成膜
するには、減圧CVD法を用いて基板温度600℃程度
でモノシランガスを熱分解する方法が知られている。ま
た高性能なpoly−SiTFTを作成する従来の方法
は、非晶質Si(a−Si)を固相成長法によって大粒
径化したpoly−Siを形成し、TFTを作成する方
法や、a−Siやpoly−Siをレーザーアニーリン
グによって溶融再結晶化し、TFTを作成する方法等が
あった。Conventionally, in order to form a poly-Si film on a glass substrate, a method is known in which monosilane gas is thermally decomposed at a substrate temperature of about 600° C. using a low-pressure CVD method. In addition, conventional methods for creating high-performance poly-Si TFTs include forming TFTs by forming poly-Si in which amorphous Si (a-Si) is made large in size by solid-phase growth; There is a method of melting and recrystallizing -Si or poly-Si by laser annealing to create a TFT.
【0004】0004
【発明が解決しようとする課題】減圧CVD法でpol
y−Siを成膜する方法では、成膜温度上の要求から低
融点ガラスを基板に用いることはできない。また固相成
長法によって大粒径poly−Siを得るためには、6
00℃程度の温度で4〜70時間という長時間アニール
をしなければならず、低融点ガラスを基板に用いること
はできない。レーザーアニーリングは、レーザービーム
の不均一特性による素子特性ばらつきや、スループット
が低い等の問題点があった。[Problem to be solved by the invention] Pol
In the method of forming a y-Si film, low melting point glass cannot be used for the substrate due to the film forming temperature requirements. In addition, in order to obtain large grain size poly-Si by solid phase growth method, 6
This requires annealing for a long time of 4 to 70 hours at a temperature of about 0.000C, and low melting point glass cannot be used for the substrate. Laser annealing has problems such as variations in device characteristics due to non-uniform characteristics of the laser beam and low throughput.
【0005】このため、特開昭63−175417、特
開平2−177368、特開平2−202018、Ma
terials Research Society
Simposia Proceedings, Vo
lume95, p.225 (1987)等に見られ
るように、プラズマ化学気相成長法(PCVD)で、シ
ランガスと弗素、フロロシラン等のエッチング性ガスの
混合ガスをグロー放電分解することにより、低温で多結
晶シリコンを製造することのできる方法が注目されてい
る。[0005] For this reason, Japanese Patent Application Laid-Open No. 63-175417, Japanese Patent Application Publication No. 2-177368, Japanese Patent Application Publication No. 2-202018, Ma
terials Research Society
Symposia Proceedings, Vo
lume95, p. 225 (1987), polycrystalline silicon is produced at low temperatures by glow discharge decomposition of a mixed gas of silane gas and etching gases such as fluorine and fluorosilane using plasma chemical vapor deposition (PCVD). Methods that can be used to do this are attracting attention.
【0006】これらの成膜方法で得られたpoly−S
i薄膜は、エッチング性ガスとして弗素ガス等のハロゲ
ンガスやフロロシラン、ジクロルシラン等のハロゲン化
物を含むため、得られたpoly−Si中には弗素や塩
素などのハロゲン原子が不純物として含まれる。pol
y−SiTFTを作製するとき、これらの不純物は結晶
欠陥の原因となり、TFTのリーク電流の増大を引き起
こすので大きな問題となる。Poly-S obtained by these film-forming methods
Since the i-thin film contains a halogen gas such as fluorine gas and a halide such as fluorosilane and dichlorosilane as an etching gas, the obtained poly-Si contains halogen atoms such as fluorine and chlorine as impurities. pol
When manufacturing a y-Si TFT, these impurities pose a major problem because they cause crystal defects and increase leakage current of the TFT.
【0007】特開平2−248038に見られる多結晶
シリコン薄膜の製造方法は、エッチングガスとして水素
を用いているので、前述の不純物混入の問題はない。し
かし、水素の活性化状態を反応ガスとは別個の活性化室
を設けて制御しているため、装置が複雑化するという問
題点があった。また特公平3−8102に見られる半導
体薄膜の製造方法は、上記の問題点に加え、得られる薄
膜が非晶質シリコンと多結晶シリコンの混在状態であり
、TFTに応用するには適さないという問題点もあった
。The method for manufacturing a polycrystalline silicon thin film disclosed in Japanese Patent Application Laid-Open No. 2-248038 uses hydrogen as an etching gas, so there is no problem of impurity contamination as described above. However, since the activation state of hydrogen is controlled by providing an activation chamber separate from the reaction gas, there is a problem that the apparatus becomes complicated. In addition to the above-mentioned problems, the method for manufacturing semiconductor thin films described in Japanese Patent Publication No. 3-8102 has the disadvantage that the resulting thin film is a mixture of amorphous silicon and polycrystalline silicon, making it unsuitable for application to TFTs. There were also problems.
【0008】本発明は以上の問題点を解決するものでそ
の目的は、ハロゲンガス等の不純物を含まない高品質の
poly−Siを、簡易な装置で、低温で成膜できる方
法を提供することにある。The present invention solves the above problems, and its purpose is to provide a method for forming a film of high quality poly-Si, which does not contain impurities such as halogen gas, using a simple device at a low temperature. It is in.
【0009】[0009]
【課題を解決するための手段】本発明の多結晶シリコン
薄膜の製造方法は、シリコンを含有するガスをプラズマ
励起によりグロー放電分解し、基板上に多結晶シリコン
を形成させる方法において、基板上における水素の活性
状態を、グロー放電用電極間の距離を調整することによ
って制御することを特徴とする。[Means for Solving the Problems] The method for manufacturing a polycrystalline silicon thin film of the present invention is a method for forming polycrystalline silicon on a substrate by glow discharge decomposition of a silicon-containing gas by plasma excitation. It is characterized in that the activation state of hydrogen is controlled by adjusting the distance between the glow discharge electrodes.
【0010】0010
【実施例】以下、本発明の製造方法について詳述する。
使用する基板は単結晶Si以外の基板なら、低融点ガラ
スでもセラミック基板等でも、石英基板でもよい。単結
晶Siを基板に使用するとpoly−Siではなくエピ
タキシャルSi膜が得られる。本実施例ではコーニング
社製7059基板を使用した。PCVD装置は、平行平
板型電極を持つアネルバ社製PED−302型を使用し
た。図1に本発明で用いたPCVD装置の概略図を示す
。1は反応室、2は排気管、3は対抗電極、4はガス吹
き出し孔、5はガス導入部、6は高周波印加電極、7は
基板加熱ヒータ、8は基板、9は高周波電源である。
図1中のWは電極間距離を表す。成膜ガスにはSiH4
、Si2H6、Si3H8等と、H2の混合ガスを用い
る。本実施例ではシラン(SiH4)とH2の、混合ガ
スを用いた。EXAMPLES The manufacturing method of the present invention will be described in detail below. The substrate used may be a substrate other than single crystal Si, such as a low melting point glass, a ceramic substrate, or a quartz substrate. If single crystal Si is used for the substrate, an epitaxial Si film can be obtained instead of poly-Si. In this example, a 7059 substrate manufactured by Corning was used. The PCVD apparatus used was a PED-302 model manufactured by ANELVA, which has parallel plate electrodes. FIG. 1 shows a schematic diagram of the PCVD apparatus used in the present invention. 1 is a reaction chamber, 2 is an exhaust pipe, 3 is a counter electrode, 4 is a gas blowing hole, 5 is a gas introduction part, 6 is a high frequency application electrode, 7 is a substrate heater, 8 is a substrate, and 9 is a high frequency power source. W in FIG. 1 represents the distance between electrodes. SiH4 is used as the film forming gas.
, Si2H6, Si3H8, etc., and a mixed gas of H2 are used. In this example, a mixed gas of silane (SiH4) and H2 was used.
【0011】基本的な反応機構は次に示す式1に従う。
式1の反応において、R1が成膜反応で、R2がエッチ
ング反応である。The basic reaction mechanism follows Formula 1 shown below. In the reaction of Formula 1, R1 is a film forming reaction and R2 is an etching reaction.
【0012】0012
【化1】
(nは無次元数)式1において、水素濃度を増して行く
とR2の反応が優勢となるので、結合エネルギーの弱い
Si−H結合はR2のエッチング反応により選択的に切
られる。このためSi−Si結合だけが残ることになり
、このような条件のもとでは基板上にはpoly−Si
が成膜される。一方、シランガス濃度が増えると式1に
おけるR1の成膜反応が優勢となり、基板上には水素濃
度の大きい非晶質シリコン(a−Si)が成膜される。
このようなR1とR2の競合関係は、水素ガス濃度に対
するシランガス濃度の比を変えることによって容易に調
整することができる。[Formula 1] (n is a dimensionless number) In formula 1, as the hydrogen concentration increases, the reaction of R2 becomes dominant, so the Si-H bond with weak bond energy is selectively broken by the etching reaction of R2. . Therefore, only Si-Si bonds remain, and under these conditions, poly-Si bonds remain on the substrate.
is deposited. On the other hand, when the silane gas concentration increases, the film formation reaction of R1 in Equation 1 becomes dominant, and amorphous silicon (a-Si) with a high hydrogen concentration is formed on the substrate. Such a competitive relationship between R1 and R2 can be easily adjusted by changing the ratio of the silane gas concentration to the hydrogen gas concentration.
【0013】従ってpoly−Si薄膜を形成するには
、シランガスを大流量の水素ガスで希釈し、シラン濃度
/水素濃度比を少なくとも0.1以下にすることが必要
となる。実際にpoly−Siを成膜する場合、シラン
/水素ガス濃度比はガス流量比でSiH4/H2=0.
5〜5.0%、特に1.0〜3.0%が望ましい。0.
5%より小さいと水素ガスによるエッチング反応が優勢
になりすぎ、デポレートが極端に小さくなり、粒径も小
さいpoly−Siしか成膜されない。5.0%を越え
ると成膜反応が優勢となり、a−Siしか成膜されない
。[0013] Therefore, in order to form a poly-Si thin film, it is necessary to dilute the silane gas with a large flow of hydrogen gas and to make the silane concentration/hydrogen concentration ratio at least 0.1 or less. When actually forming a poly-Si film, the silane/hydrogen gas concentration ratio is the gas flow rate ratio: SiH4/H2=0.
5 to 5.0%, particularly 1.0 to 3.0% is desirable. 0.
If it is less than 5%, the etching reaction by hydrogen gas becomes too dominant, the deposit rate becomes extremely small, and only poly-Si with a small particle size is formed. When it exceeds 5.0%, the film forming reaction becomes dominant and only a-Si is formed.
【0014】反応室内の圧力は0.1〜10.0Tor
rで、特に0.3〜1.5Torrが好ましい。プラズ
マを発生させる高周波電力は、電力密度0.01〜5.
0W/cm2、好ましくは0.03〜0.06W/cm
2とする。
0.01W/cm2より小さいと、エッチング反応が弱
くなりすぎ、5W/cm2を越えると薄膜がプラズマダ
メージを受け、高品質の膜を形成できない。基板温度は
100〜600℃である。好ましくは200℃〜400
℃とする。基板温度が100℃より低いとa−Siが成
膜され、600℃より高いと低温成膜PCVDの利点を
生かせなくなる。[0014] The pressure inside the reaction chamber is 0.1 to 10.0 Torr.
r is particularly preferably 0.3 to 1.5 Torr. The high frequency power for generating plasma has a power density of 0.01 to 5.
0W/cm2, preferably 0.03-0.06W/cm
Set it to 2. If it is less than 0.01 W/cm2, the etching reaction becomes too weak, and if it exceeds 5 W/cm2, the thin film will suffer plasma damage, making it impossible to form a high quality film. The substrate temperature is 100-600°C. Preferably 200℃~400℃
℃. When the substrate temperature is lower than 100° C., a-Si is deposited, and when the substrate temperature is higher than 600° C., the advantages of low-temperature film formation PCVD cannot be utilized.
【0015】poly−Siを成膜するための重要な条
件は、平行平板型PCVD装置の対向電極間距離(以下
、電極間距離;図1のW)である。エッチング反応が進
むためには、電極間距離が十分に短く、水素が活性状態
で基板上に到達しなければならない。電極間距離が長い
と、エッチング反応は気相中で起こり、基板上には非晶
質シリコンが成膜される。このため、電極間距離Wは高
周波電力と圧力によって規定される。高周波電力が0.
03W/cm2で、圧力が1.2Torrの場合は、電
極間距離Wは45mm未満、好ましくは27mm以下、
更に好ましくは20mm以下である必要がある。成膜前
に1×10−6Torr以下の真空にした反応室内にS
iH4:H2=1.8:98.2の混合ガスを総流量2
00SCCMで供給し、内圧を表1に示す圧力に調整し
た。基板温度を表1に示した温度に設定した後、基板温
度が安定するまで約20分間成膜ガスを流した。次いで
13.56MHzの高周波電源を用いて、放電電力0.
03W/cm2で120分間放電し、ガラス基板上にシ
リコン薄膜を成長させた。成長速度は9〜22Å/分で
あった。得られたpoly−Siの平均粒径はX線回折
によって測定した。An important condition for forming a poly-Si film is the distance between opposing electrodes (hereinafter referred to as interelectrode distance; W in FIG. 1) of the parallel plate type PCVD apparatus. In order for the etching reaction to proceed, the distance between the electrodes must be sufficiently short and hydrogen must reach the substrate in an active state. When the distance between the electrodes is long, the etching reaction occurs in the gas phase, and amorphous silicon is deposited on the substrate. Therefore, the inter-electrode distance W is defined by high frequency power and pressure. High frequency power is 0.
When the pressure is 03 W/cm2 and 1.2 Torr, the distance W between the electrodes is less than 45 mm, preferably 27 mm or less,
More preferably, it needs to be 20 mm or less. Before film formation, S
iH4:H2 = 1.8:98.2 mixed gas at a total flow rate of 2
The internal pressure was adjusted to the pressure shown in Table 1. After setting the substrate temperature to the temperature shown in Table 1, the film forming gas was flowed for about 20 minutes until the substrate temperature stabilized. Next, using a 13.56 MHz high frequency power source, the discharge power was 0.
A silicon thin film was grown on the glass substrate by discharging at 0.3 W/cm2 for 120 minutes. The growth rate was 9-22 Å/min. The average particle size of the obtained poly-Si was measured by X-ray diffraction.
【0016】表1に本発明の製造方法によって作成した
poly−Siの諸特性を示す。表1に明らかなように
、膜厚が1000Åという比較的薄い膜厚でも、結晶粒
径が1000Å程度のpoly−Siが成膜されている
。また結晶方位は表1に示す全ての膜で(111)、(
220)方位のX線回折ピークを観測しており、特にN
o.3、No.4の膜では(220)方位が優先配向と
なるpoly−Si薄膜が得られている。エッチングガ
スにハロゲン系のガスを用いる場合は、膜厚が2500
Å以上から多結晶化が始まることが知られており、薄膜
化が困難だったが、本発明の製造方法によれば、pol
y−Siの薄膜化も可能となるためTFTの応用に際し
効果は大きい。Table 1 shows various properties of poly-Si produced by the production method of the present invention. As is clear from Table 1, even with a relatively thin film thickness of 1000 Å, a poly-Si film having a crystal grain size of about 1000 Å is formed. In addition, the crystal orientations of all the films shown in Table 1 are (111) and (
220) azimuthal X-ray diffraction peaks have been observed, especially N
o. 3.No. In the film of No. 4, a poly-Si thin film with preferential orientation in the (220) direction was obtained. When using a halogen gas as the etching gas, the film thickness is 2500 mm.
It is known that polycrystalization begins at a temperature of 1.5 Å or more, making it difficult to make a thin film. However, according to the manufacturing method of the present invention,
Since it is also possible to make the y-Si film thinner, it has a great effect when applied to TFTs.
【0017】[0017]
【表1】[Table 1]
【0018】表2に比較例として、電極間距離を45m
mとした場合に、表1と同様にして成膜したSi薄膜の
諸特性を示す。表2に明らかなように、比較例に示した
条件ではpoly−Siが得られず、a−Siが成膜さ
れる。Table 2 shows a comparative example in which the distance between the electrodes is 45 m.
Table 1 shows various properties of the Si thin film formed in the same manner as in Table 1, where m is the same. As is clear from Table 2, poly-Si was not obtained under the conditions shown in the comparative example, but a-Si was formed.
【0019】[0019]
【表2】[Table 2]
【0020】本発明において、成膜ガスに元素周期律表
第III族または第V族のドーピングガスを混入するこ
とにより、p型またはn型のpoly−Siを成膜する
ことができる。ドーピングガスには例えばジボラン、ホ
スフィン、アルシン等が挙げられる。In the present invention, a p-type or n-type poly-Si film can be formed by mixing a doping gas of Group III or V of the periodic table of elements into the film-forming gas. Examples of the doping gas include diborane, phosphine, arsine, and the like.
【0021】[0021]
【発明の効果】以上述べたように、本発明によれば高品
質のpoly−Siを200℃程度の低温で成膜するこ
とができる。このため基板ガラスに低融点のガラス基板
を用いることができ、TFT製造プロセスの低温化が可
能となる。従って本発明を用いれば、低価格のガラス基
板を用いることができるので、液晶ディスプレイ、密着
型イメージセンサ、太陽電池等のデバイスの低コスト化
に大きな効果がある。しかも必要な装置は通常のプラズ
マCVD装置で良く、水素ガスを活性化するための付加
的な装置は必要ない。As described above, according to the present invention, a high quality poly-Si film can be formed at a low temperature of about 200°C. Therefore, a glass substrate with a low melting point can be used as the substrate glass, and the temperature of the TFT manufacturing process can be lowered. Therefore, if the present invention is used, a low-cost glass substrate can be used, which has a great effect on reducing the cost of devices such as liquid crystal displays, contact image sensors, and solar cells. Furthermore, the necessary equipment is a normal plasma CVD equipment, and no additional equipment for activating hydrogen gas is required.
【0022】また本発明はハロゲン系のガスを全く用い
ていないため、弗素のようなTFTの特性に悪影響を及
ぼす不純物元素がpoly−Si膜中に混入することが
無いという大きな利点がある。Furthermore, since the present invention does not use any halogen-based gas, it has the great advantage that impurity elements such as fluorine that adversely affect the characteristics of TFTs are not mixed into the poly-Si film.
【0023】またLPCVD法、固相成長法、レーザー
アニーリング法等で得られたpoly−Si薄膜は、そ
の結晶粒界にダングリングボンドがあるため電気的特性
が劣化するという問題点があり、これを解決するために
poly−Siを成膜後、水素プラズマ等の手段によっ
てダングリングボンドをパッシベートする必要があった
。ところが本発明の方法では、poly−Si成膜時に
水素プラズマにさらされているので、水素パッシベーシ
ョンを後から施す必要はないという長所もある。[0023] Furthermore, poly-Si thin films obtained by LPCVD, solid-phase growth, laser annealing, etc. have a problem in that their electrical properties deteriorate due to dangling bonds at their grain boundaries. In order to solve this problem, it was necessary to passivate the dangling bonds by means such as hydrogen plasma after forming a poly-Si film. However, the method of the present invention has the advantage that since the poly-Si film is exposed to hydrogen plasma during film formation, there is no need to perform hydrogen passivation afterwards.
【0024】更に、LPCVD法、固相成長法、レーザ
ーアニーリング法等で得られるpoly−Si薄膜は{
111}の優先配向になるのに対し、本発明の方法で得
られたpoly−Si薄膜は{110}の優先配向とな
る。poly−Si薄膜の面内方向(水平方向)に対す
る電子移動度は、{111}配位よりも{110}配位
のpoly−Siの方が大きいことが知られている。
従って、本発明の方法で得られたpoly−Siを使え
ば、高電子移動度の高性能TFTを容易に作成できるよ
うになるという大きな長所も合わせもつ。また本発明は
4Mビット以上の高集積化SRAMの負荷素子用TFT
に代表される、IC、LSI、3次元SOI素子等の半
導体素子一般への応用にも効果は大きい。Furthermore, the poly-Si thin film obtained by the LPCVD method, solid phase growth method, laser annealing method, etc.
111}, whereas the poly-Si thin film obtained by the method of the present invention has a {110} preferential orientation. It is known that the electron mobility in the in-plane direction (horizontal direction) of a poly-Si thin film is larger in {110}-coordinated poly-Si than in {111}-coordinated poly-Si. Therefore, the use of poly-Si obtained by the method of the present invention also has the great advantage that high performance TFTs with high electron mobility can be easily produced. The present invention also provides TFTs for load elements of highly integrated SRAMs of 4M bits or more.
The present invention is also highly effective when applied to general semiconductor devices such as ICs, LSIs, and three-dimensional SOI devices.
【図1】 本発明で用いたPCVD装置の概略図。FIG. 1 is a schematic diagram of the PCVD apparatus used in the present invention.
1………反応室 2………排気管 3………対抗電極 4………ガス吹き出し孔 5………ガス導入部 6………高周波印加電極 7………基板加熱ヒータ 8………基板 9………高周波電源 1……Reaction chamber 2...Exhaust pipe 3……Counter electrode 4...Gas blowout hole 5...Gas introduction part 6...High frequency application electrode 7...Substrate heater 8......Substrate 9……High frequency power supply
Claims (1)
起によりグロー放電分解し、基板上に多結晶シリコンを
形成させる方法において、基板上における水素の活性状
態を、グロー放電用電極間の距離を調整することによっ
て制御することを特徴とする多結晶シリコン薄膜の製造
方法。Claim 1: In a method of decomposing silicon-containing gas by glow discharge by plasma excitation to form polycrystalline silicon on a substrate, the activation state of hydrogen on the substrate is adjusted by adjusting the distance between the glow discharge electrodes. 1. A method for producing a polycrystalline silicon thin film, the method comprising: controlling the production of a polycrystalline silicon thin film;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP03085249A JP3116403B2 (en) | 1991-04-17 | 1991-04-17 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03085249A JP3116403B2 (en) | 1991-04-17 | 1991-04-17 | Method for manufacturing thin film transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04318921A true JPH04318921A (en) | 1992-11-10 |
JP3116403B2 JP3116403B2 (en) | 2000-12-11 |
Family
ID=13853298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03085249A Expired - Lifetime JP3116403B2 (en) | 1991-04-17 | 1991-04-17 | Method for manufacturing thin film transistor |
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Country | Link |
---|---|
JP (1) | JP3116403B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0641018A1 (en) * | 1993-08-23 | 1995-03-01 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method of semiconductor device and thin film transistor with a recrystallized thin semiconductor film |
JPH07153702A (en) * | 1993-11-29 | 1995-06-16 | Nec Corp | Thin film forming method and device |
EP0933451A1 (en) * | 1998-01-29 | 1999-08-04 | Nissin Electric Co., Ltd. | Film forming apparatus and method of forming a crystalline silicon film |
EP1172457A1 (en) * | 2000-07-11 | 2002-01-16 | Canon Kabushiki Kaisha | Thin film formation method |
-
1991
- 1991-04-17 JP JP03085249A patent/JP3116403B2/en not_active Expired - Lifetime
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0641018A1 (en) * | 1993-08-23 | 1995-03-01 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method of semiconductor device and thin film transistor with a recrystallized thin semiconductor film |
JPH07153702A (en) * | 1993-11-29 | 1995-06-16 | Nec Corp | Thin film forming method and device |
EP0933451A1 (en) * | 1998-01-29 | 1999-08-04 | Nissin Electric Co., Ltd. | Film forming apparatus and method of forming a crystalline silicon film |
EP1172457A1 (en) * | 2000-07-11 | 2002-01-16 | Canon Kabushiki Kaisha | Thin film formation method |
JP2002030437A (en) * | 2000-07-11 | 2002-01-31 | Canon Inc | Thin film deposition method |
JP4510242B2 (en) * | 2000-07-11 | 2010-07-21 | キヤノン株式会社 | Thin film formation method |
Also Published As
Publication number | Publication date |
---|---|
JP3116403B2 (en) | 2000-12-11 |
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