JP3116403B2 - Method for manufacturing thin film transistor - Google Patents

Method for manufacturing thin film transistor

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Publication number
JP3116403B2
JP3116403B2 JP03085249A JP8524991A JP3116403B2 JP 3116403 B2 JP3116403 B2 JP 3116403B2 JP 03085249 A JP03085249 A JP 03085249A JP 8524991 A JP8524991 A JP 8524991A JP 3116403 B2 JP3116403 B2 JP 3116403B2
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JP
Japan
Prior art keywords
thin film
gas
poly
substrate
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP03085249A
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Japanese (ja)
Other versions
JPH04318921A (en
Inventor
正文 国井
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Seiko Epson Corp
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Seiko Epson Corp
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は薄膜トランジスタ等の半
導体素子に応用できる多結晶シリコン薄膜の製造方法に
関し、特に低温で低融点ガラス等の基板上に形成できる
多結晶シリコン薄膜の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film applicable to a semiconductor device such as a thin film transistor, and more particularly to a method for manufacturing a polycrystalline silicon thin film which can be formed on a substrate such as a low melting point glass at a low temperature.

【0002】[0002]

【従来の技術】低融点ガラス基板上に、微結晶または多
結晶Si(poly−Si)を素子材とした高性能な薄
膜トランジスタ(TFT)を作成する試みが活発化して
いる。特に、基板としてコーニング社製7059基板等
の低融点ガラス基板を用い、プロセスの最高温度450
℃程度以下で、高易動度、高ON/OFF比のTFTを
作成するプロセスの実用化が待望されている。
2. Description of the Related Art Attempts to fabricate a high-performance thin film transistor (TFT) using microcrystalline or polycrystalline Si (poly-Si) as an element material on a low-melting glass substrate have been activated. In particular, a low-melting glass substrate such as a Corning 7059 substrate is used as the substrate, and the maximum process temperature is 450
It is expected that a process for producing a TFT having a high mobility and a high ON / OFF ratio at a temperature of about ° C or less will be put to practical use.

【0003】従来poly−Siをガラス基板上に成膜
するには、減圧CVD法を用いて基板温度600℃程度
でモノシランガスを熱分解する方法が知られている。ま
た高性能なpoly−SiTFTを作成する従来の方法
は、非晶質Si(a−Si)を固相成長法によって大粒
径化したpoly−Siを形成し、TFTを作成する方
法や、a−Siやpoly−Siをレーザーアニーリン
グによって溶融再結晶化し、TFTを作成する方法等が
あった。
Conventionally, a method for thermally decomposing monosilane gas at a substrate temperature of about 600 ° C. using a low pressure CVD method has been known for forming poly-Si on a glass substrate. A conventional method of producing a high-performance poly-Si TFT includes a method of forming a poly-Si in which amorphous Si (a-Si) is increased in particle size by a solid phase growth method to produce a TFT, and a method of producing a TFT. There has been a method of producing a TFT by melting and recrystallizing -Si or poly-Si by laser annealing.

【0004】[0004]

【発明が解決しようとする課題】減圧CVD法でpol
y−Siを成膜する方法では、成膜温度上の要求から低
融点ガラスを基板に用いることはできない。また固相成
長法によって大粒径poly−Siを得るためには、6
00℃程度の温度で4〜70時間という長時間アニール
をしなければならず、低融点ガラスを基板に用いること
はできない。レーザーアニーリングは、レーザービーム
の不均一特性による素子特性ばらつきや、スループット
が低い等の問題点があった。
SUMMARY OF THE INVENTION In a low pressure CVD method, pol
In a method of forming a y-Si film, a low-melting glass cannot be used for a substrate due to a demand for a film forming temperature. In order to obtain poly-Si having a large particle size by the solid phase growth method, 6
Annealing must be performed at a temperature of about 00 ° C. for a long time of 4 to 70 hours, and a low melting point glass cannot be used for a substrate. Laser annealing has problems such as variations in device characteristics due to non-uniform characteristics of a laser beam and low throughput.

【0005】このため、特開昭63−175417、特
開平2−177368、特開平2−202018、Mate
rials Research Society Simposia Proceedings, Volu
me95, p.225 (1987)等に見られるように、プラズマ化学
気相成長法(PCVD)で、シランガスと弗素、フロロ
シラン等のエッチング性ガスの混合ガスをグロー放電分
解することにより、低温で多結晶シリコンを製造するこ
とのできる方法が注目されている。
For this reason, JP-A-63-175417, JP-A-2-177368, JP-A-2-202018, and Mate
rials Research Society Simposia Proceedings, Volu
As shown in me95, p.225 (1987) and the like, a mixed gas of a silane gas and an etching gas such as fluorine or fluorosilane is decomposed by glow discharge decomposition by plasma enhanced chemical vapor deposition (PCVD), so that it can be produced at a low temperature. Attention has been focused on methods that can produce crystalline silicon.

【0006】これらの成膜方法で得られたpoly−S
i薄膜は、エッチング性ガスとして弗素ガス等のハロゲ
ンガスやフロロシラン、ジクロルシラン等のハロゲン化
物を含むため、得られたpoly−Si中には弗素や塩
素などのハロゲン原子が不純物として含まれる。pol
y−SiTFTを作製するとき、これらの不純物は結晶
欠陥の原因となり、TFTのリーク電流の増大を引き起
こすので大きな問題となる。
The poly-S obtained by these film forming methods
Since the i-thin film contains a halogen gas such as fluorine gas and a halide such as fluorosilane and dichlorosilane as an etching gas, the obtained poly-Si contains halogen atoms such as fluorine and chlorine as impurities. pol
When manufacturing a y-Si TFT, these impurities cause crystal defects and cause an increase in the leak current of the TFT, which is a serious problem.

【0007】特開平2−248038に見られる多結晶
シリコン薄膜の製造方法は、エッチングガスとして水素
を用いているので、前述の不純物混入の問題はない。し
かし、水素の活性化状態を反応ガスとは別個の活性化室
を設けて制御しているため、装置が複雑化するという問
題点があった。また特公平3−8102に見られる半導
体薄膜の製造方法は、上記の問題点に加え、得られる薄
膜が非晶質シリコンと多結晶シリコンの混在状態であ
り、TFTに応用するには適さないという問題点もあっ
た。
In the method of manufacturing a polycrystalline silicon thin film disclosed in Japanese Patent Application Laid-Open No. 2-248038, since hydrogen is used as an etching gas, the problem of impurity contamination described above does not occur. However, since the activation state of hydrogen is controlled by providing an activation chamber separate from the reaction gas, there is a problem that the apparatus becomes complicated. In addition to the above problems, the method of manufacturing a semiconductor thin film disclosed in Japanese Patent Publication No. 3-8102 states that the obtained thin film is a mixed state of amorphous silicon and polycrystalline silicon, and is not suitable for application to a TFT. There were also problems.

【0008】本発明は以上の問題点を解決するものでそ
の目的は、ハロゲンガス等の不純物を含まない高品質の
poly−Siを、簡易な装置で、低温で成膜できる方
法を提供することにある。
An object of the present invention is to provide a method capable of forming high-quality poly-Si containing no impurities such as halogen gas at a low temperature with a simple apparatus. It is in.

【0009】[0009]

【課題を解決するための手段】本発明は、基板上に多結
晶シリコン薄膜を有する薄膜トランジスタの製造方法に
おいて、前記多結晶シリコン薄膜は、シランガスに対す
る水素ガス流量比を1.0〜5.0%であるガスを用い
て、プラズマを発生させるための電極間距離を45mm
以下で高周波電力を0.01〜5.0W/cm2で、反応
室内圧力を0.1〜10.0Torrで、プラズマ化学
気相堆積法により形成することを特徴とする。
According to the present invention, there is provided a method of manufacturing a thin film transistor having a polycrystalline silicon thin film on a substrate, wherein the polycrystalline silicon thin film has a hydrogen gas flow ratio to silane gas of 1.0 to 5.0%. The distance between electrodes for generating plasma is 45 mm using a gas of
Hereinafter, it is characterized by being formed by plasma enhanced chemical vapor deposition at a high frequency power of 0.01 to 5.0 W / cm 2 and a reaction chamber pressure of 0.1 to 10.0 Torr.

【0010】[0010]

【実施例】以下、本発明の製造方法について詳述する。
使用する基板は単結晶Si以外の基板なら、低融点ガラ
スでもセラミック基板等でも、石英基板でもよい。単結
晶Siを基板に使用するとpoly−Siではなくエピ
タキシャルSi膜が得られる。本実施例ではコーニング
社製7059基板を使用した。PCVD装置は、平行平
板型電極を持つアネルバ社製PED−302型を使用し
た。図1に本発明で用いたPCVD装置の概略図を示
す。1は反応室、2は排気管、3は対抗電極、4はガス
吹き出し孔、5はガス導入部、6は高周波印加電極、7
は基板加熱ヒータ、8は基板、9は高周波電源である。
図1中のWは電極間距離を表す。成膜ガスにはSi
4、Si26、Si38等と、H2の混合ガスを用い
る。本実施例ではシラン(SiH4)とH2の、混合ガス
を用いた。
The production method of the present invention will be described below in detail.
The substrate to be used may be a low melting point glass, a ceramic substrate, or a quartz substrate as long as it is a substrate other than single crystal Si. When single-crystal Si is used for the substrate, an epitaxial Si film can be obtained instead of poly-Si. In this embodiment, a Corning 7059 substrate was used. As the PCVD apparatus, a PED-302 type manufactured by Anelva having parallel plate type electrodes was used. FIG. 1 shows a schematic diagram of a PCVD apparatus used in the present invention. 1 is a reaction chamber, 2 is an exhaust pipe, 3 is a counter electrode, 4 is a gas outlet, 5 is a gas inlet, 6 is a high frequency application electrode, 7
Is a substrate heater, 8 is a substrate, and 9 is a high frequency power supply.
W in FIG. 1 represents the distance between the electrodes. The deposition gas is Si
A mixed gas of H 4 , Si 2 H 6 , Si 3 H 8, etc. and H 2 is used. In this embodiment, a mixed gas of silane (SiH 4 ) and H 2 was used.

【0011】基本的な反応機構は次に示す式1に従う。
式1の反応において、R1が成膜反応で、R2がエッチ
ング反応である。
The basic reaction mechanism complies with the following equation 1.
In the reaction of Formula 1, R1 is a film forming reaction and R2 is an etching reaction.

【0012】[0012]

【化1】 (nは無次元数)式1において、水素濃度を増して行く
とR2の反応が優勢となるので、結合エネルギーの弱い
Si−H結合はR2のエッチング反応により選択的に切
られる。このためSi−Si結合だけが残ることにな
り、このような条件のもとでは基板上にはpoly−S
iが成膜される。一方、シランガス濃度が増えると式1
におけるR1の成膜反応が優勢となり、基板上には水素
濃度の大きい非晶質シリコン(a−Si)が成膜され
る。このようなR1とR2の競合関係は、水素ガス濃度
に対するシランガス濃度の比を変えることによって容易
に調整することができる。
Embedded image (N is a dimensionless number) In the formula 1, the reaction of R2 becomes dominant as the hydrogen concentration is increased, so that the Si—H bond having weak binding energy is selectively cut off by the etching reaction of R2. For this reason, only the Si-Si bond remains, and under such conditions, poly-S
i is deposited. On the other hand, when the silane gas concentration increases, Equation 1
, The film formation reaction of R1 becomes dominant, and amorphous silicon (a-Si) having a high hydrogen concentration is formed on the substrate. Such a competitive relationship between R1 and R2 can be easily adjusted by changing the ratio of the silane gas concentration to the hydrogen gas concentration.

【0013】従ってpoly−Si薄膜を形成するに
は、シランガスを大流量の水素ガスで希釈し、シラン濃
度/水素濃度比を少なくとも0.1以下にすることが必
要となる。実際にpoly−Siを成膜する場合、シラ
ン/水素ガス濃度比はガス流量比でSiH4/H2=0.
5〜5.0%、特に1.0〜3.0%が望ましい。0.5%
より小さいと水素ガスによるエッチング反応が優勢にな
りすぎ、デポレートが極端に小さくなり、粒径も小さい
poly−Siしか成膜されない。5.0%を越えると
成膜反応が優勢となり、a−Siしか成膜されない。
Therefore, in order to form a poly-Si thin film, it is necessary to dilute the silane gas with a large flow rate of hydrogen gas so that the silane concentration / hydrogen concentration ratio is at least 0.1 or less. When actually forming a poly-Si film, the silane / hydrogen gas concentration ratio is SiH 4 / H 2 = 0.
5 to 5.0%, particularly preferably 1.0 to 3.0%. 0.5%
If the diameter is smaller, the etching reaction by the hydrogen gas becomes too dominant, the deposition rate becomes extremely small, and only poly-Si having a small particle diameter is formed. If it exceeds 5.0%, the film forming reaction becomes dominant, and only a-Si is formed.

【0014】反応室内の圧力は0.1〜10.0Torr
で、特に0.3〜1.5Torrが好ましい。プラズマを
発生させる高周波電力は、電力密度0.01〜5.0W/
cm2、好ましくは0.03〜0.06W/cm2とする。
0.01W/cm2より小さいと、エッチング反応が弱く
なりすぎ、5W/cm2を越えると薄膜がプラズマダメ
ージを受け、高品質の膜を形成できない。基板温度は1
00〜600℃である。好ましくは200℃〜400℃
とする。基板温度が100℃より低いとa−Siが成膜
され、600℃より高いと低温成膜PCVDの利点を生
かせなくなる。
The pressure in the reaction chamber is 0.1 to 10.0 Torr.
In particular, 0.3 to 1.5 Torr is preferable. The high frequency power for generating plasma has a power density of 0.01 to 5.0 W /
cm 2 , preferably 0.03 to 0.06 W / cm 2 .
If it is less than 0.01 W / cm 2 , the etching reaction becomes too weak, and if it exceeds 5 W / cm 2 , the thin film is damaged by plasma and a high quality film cannot be formed. Substrate temperature is 1
00-600 ° C. Preferably 200 ° C to 400 ° C
And When the substrate temperature is lower than 100 ° C., a-Si film is formed, and when the substrate temperature is higher than 600 ° C., the advantage of low temperature film forming PCVD cannot be utilized.

【0015】poly−Siを成膜するための重要な条
件は、平行平板型PCVD装置の対向電極間距離(以
下、電極間距離;図1のW)である。エッチング反応が
進むためには、電極間距離が十分に短く、水素が活性状
態で基板上に到達しなければならない。電極間距離が長
いと、エッチング反応は気相中で起こり、基板上には非
晶質シリコンが成膜される。このため、電極間距離Wは
高周波電力と圧力によって規定される。高周波電力が
0.03W/cm2で、圧力が1.2Torrの場合は、
電極間距離Wは45mm未満、好ましくは27mm以
下、更に好ましくは20mm以下である必要がある。成
膜前に1×10-6Torr以下の真空にした反応室内に
SiH4:H2=1.8:98.2の混合ガスを総流量20
0SCCMで供給し、内圧を表1に示す圧力に調整し
た。基板温度を表1に示した温度に設定した後、基板温
度が安定するまで約20分間成膜ガスを流した。次いで
13.56MHzの高周波電源を用いて、放電電力0.0
3W/cm2で120分間放電し、ガラス基板上にシリ
コン薄膜を成長させた。成長速度は9〜22Å/分であ
った。得られたpoly−Siの平均粒径はX線回折に
よって測定した。
An important condition for forming a poly-Si film is a distance between opposed electrodes (hereinafter, distance between electrodes; W in FIG. 1) of a parallel plate type PCVD apparatus. In order for the etching reaction to proceed, the distance between the electrodes must be sufficiently short and hydrogen must reach the substrate in an active state. If the distance between the electrodes is long, the etching reaction occurs in the gas phase, and amorphous silicon is formed on the substrate. Therefore, the distance W between the electrodes is defined by the high-frequency power and the pressure. When the high frequency power is 0.03 W / cm 2 and the pressure is 1.2 Torr,
The distance W between the electrodes must be less than 45 mm, preferably 27 mm or less, and more preferably 20 mm or less. Before the film formation, a mixed gas of SiH 4 : H 2 = 1.8: 98.2 was introduced into the reaction chamber evacuated to 1 × 10 −6 Torr or less at a total flow rate of 20: 1.
It was supplied at 0 SCCM, and the internal pressure was adjusted to the pressure shown in Table 1. After setting the substrate temperature to the temperature shown in Table 1, a film forming gas was flowed for about 20 minutes until the substrate temperature was stabilized. Then, using a 13.56 MHz high frequency power supply, discharge power of 0.0
Discharging was performed at 3 W / cm 2 for 120 minutes to grow a silicon thin film on a glass substrate. The growth rate was 9-22 ° / min. The average particle size of the obtained poly-Si was measured by X-ray diffraction.

【0016】表1に本発明の製造方法によって作成した
poly−Siの諸特性を示す。表1に明らかなよう
に、膜厚が1000Åという比較的薄い膜厚でも、結晶
粒径が1000Å程度のpoly−Siが成膜されてい
る。また結晶方位は表1に示す全ての膜で(111)、
(220)方位のX線回折ピークを観測しており、特に
No.3、No.4の膜では(220)方位が優先配向と
なるpoly−Si薄膜が得られている。エッチングガ
スにハロゲン系のガスを用いる場合は、膜厚が2500
Å以上から多結晶化が始まることが知られており、薄膜
化が困難だったが、本発明の製造方法によれば、pol
y−Siの薄膜化も可能となるためTFTの応用に際し
効果は大きい。
Table 1 shows various characteristics of poly-Si produced by the production method of the present invention. As is clear from Table 1, poly-Si having a crystal grain size of about 1000 ° is formed even with a relatively thin film thickness of 1000 °. The crystal orientation was (111) for all films shown in Table 1,
The X-ray diffraction peak of the (220) direction is observed. In particular, in the films of No. 3 and No. 4, a poly-Si thin film in which the (220) direction is the preferred orientation is obtained. When a halogen-based gas is used as the etching gas, the film thickness is 2,500.
Å It is known that polycrystallization starts from the above, and it was difficult to make a thin film. However, according to the manufacturing method of the present invention, pol
Since the thickness of y-Si can be reduced, the effect is large when TFT is applied.

【0017】[0017]

【表1】 [Table 1]

【0018】表2に比較例として、電極間距離を45m
mとした場合に、表1と同様にして成膜したSi薄膜の
諸特性を示す。表2に明らかなように、比較例に示した
条件ではpoly−Siが得られず、a−Siが成膜さ
れる。
Table 2 shows a comparative example in which the distance between the electrodes was 45 m.
When m is set, various characteristics of the Si thin film formed in the same manner as in Table 1 are shown. As is clear from Table 2, poly-Si was not obtained under the conditions shown in the comparative example, and a-Si was formed.

【0019】[0019]

【表2】 [Table 2]

【0020】本発明において、成膜ガスに元素周期律表
第III族または第V族のドーピングガスを混入するこ
とにより、p型またはn型のpoly−Siを成膜する
ことができる。ドーピングガスには例えばジボラン、ホ
スフィン、アルシン等が挙げられる。
In the present invention, a p-type or n-type poly-Si film can be formed by mixing a doping gas of Group III or Group V of the periodic table into the film forming gas. Examples of the doping gas include diborane, phosphine, arsine, and the like.

【0021】以上述べたように、本発明によれば高品質
のpoly−Siを200℃程度の低温で成膜すること
ができる。このため基板ガラスに低融点のガラス基板を
用いることができ、低価格のガラス基板を用いることが
できるので、液晶ディスプレイ、密着性イメージセン
サ、太陽電池等のデバイスの低コスト化に大きな効果が
ある。しかも必要な装置は通常のプラズマCVD装置で
よく、水素ガスを活性化するための付加的な装置は必要
ない。
As described above, according to the present invention, high quality poly-Si can be formed at a low temperature of about 200 ° C. For this reason, a glass substrate having a low melting point can be used as the substrate glass, and a low-cost glass substrate can be used, which has a great effect on reducing the cost of devices such as a liquid crystal display, an adhesive image sensor, and a solar cell. . In addition, the required device may be a normal plasma CVD device, and no additional device for activating hydrogen gas is required.

【0022】また本発明はハロゲン系のガスを全く用い
ていないため、弗素のようなTFTの特性に悪影響を及
ぼす不純物元素がpoly−Si膜中に混入することが
無いという大きな利点がある。
Further, since the present invention does not use any halogen-based gas, there is a great advantage that impurity elements such as fluorine which adversely affect the characteristics of the TFT are not mixed into the poly-Si film.

【0023】またLPCVD法、固相成長法、レーザー
アニーリング法等で得られたpoly−Si薄膜は、そ
の結晶粒界にダングリングボンドがあるため電気的特性
が劣化するという問題点があり、これを解決するために
poly−Siを成膜後、水素プラズマ等の手段によっ
てダングリングボンドをパッシベートする必要があっ
た。ところが本発明の方法では、poly−Si成膜時
に水素プラズマにさらされているので、水素パッシベー
ションを後から施す必要はないという長所もある。
Further, the poly-Si thin film obtained by the LPCVD method, the solid phase growth method, the laser annealing method, etc. has a problem that the electrical characteristics are deteriorated due to dangling bonds at the crystal grain boundaries. In order to solve the above problem, it is necessary to passivate dangling bonds by means of hydrogen plasma or the like after forming the poly-Si film. However, the method of the present invention has an advantage in that it is not necessary to perform hydrogen passivation later because the poly-Si film is exposed to hydrogen plasma during film formation.

【0024】更に、LPCVD法、固相成長法、レーザ
ーアニーリング法等で得られるpoly−Si薄膜は
{111}の優先配向になるのに対し、本発明の方法で
得られたpoly−Si薄膜は{110}の優先配向と
なる。poly−Si薄膜の面内方向(水平方向)に対
する電子移動度は、{111}配位よりも{110}配
位のpoly−Siの方が大きいことが知られている。
従って、本発明の方法で得られたpoly−Siを使え
ば、高電子移動度の高性能TFTを容易に作成できるよ
うになるという大きな長所も合わせもつ。また本発明は
4Mビット以上の高集積化SRAMの負荷素子用TFT
に代表される、IC,LSI、3次元SOI素子等の半
導体素子一般への応用にも効果は大きい。
Furthermore, the poly-Si thin film obtained by the LPCVD method, the solid phase growth method, the laser annealing method or the like has a preferred orientation of {111}, whereas the poly-Si thin film obtained by the method of the present invention is The preferred orientation is {110}. It is known that the electron mobility in the in-plane direction (horizontal direction) of the poly-Si thin film is larger in poly-Si of {110} coordination than in {111} coordination.
Therefore, the use of poly-Si obtained by the method of the present invention also has a great advantage that a high-performance TFT having high electron mobility can be easily produced. The present invention also provides a TFT for a load element of a highly integrated SRAM of 4 Mbits or more.
The present invention is also very effective for application to semiconductor devices such as ICs, LSIs, and three-dimensional SOI devices.

【発明の効果】以上述べたように、本発明によればグロ
ー放電用電極間の距離を45mm未満とすることによ
り、高品質の多結晶シリコン膜の成膜をすることが可能
である。
As described above, according to the present invention, a high-quality polycrystalline silicon film can be formed by setting the distance between the electrodes for glow discharge to less than 45 mm.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明で用いたPCVD装置の概略図。FIG. 1 is a schematic diagram of a PCVD apparatus used in the present invention.

【符号の説明】[Explanation of symbols]

1………反応室 2………排気管 3………対抗電極 4………ガス吹き出し孔 5………ガス導入部 6………高周波印加電極 7………基板加熱ヒータ 8………基板 9………高周波電源 DESCRIPTION OF SYMBOLS 1 ... Reaction chamber 2 ... Exhaust pipe 3 ... Counter electrode 4 ... Gas blowing hole 5 ... Gas introduction part 6 ... High frequency application electrode 7 ... Substrate heater 8 ... Substrate 9 High frequency power supply

フロントページの続き (56)参考文献 特開 平3−250624(JP,A) 特開 昭63−223180(JP,A) 特開 昭63−197329(JP,A) 特開 昭60−204880(JP,A) 特開 昭64−10617(JP,A) 特開 平3−219622(JP,A) 特開 平4−211115(JP,A) 特開 平4−318973(JP,A) 特開 平4−318974(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/205 H01L 21/31 C23C 16/00 H01L 21/336 H01L 29/786 H01L 31/04 Continuation of the front page (56) References JP-A-3-250624 (JP, A) JP-A-63-223180 (JP, A) JP-A-63-197329 (JP, A) JP-A-60-204880 (JP, A) JP-A-64-10617 (JP, A) JP-A-3-219622 (JP, A) JP-A-4-211115 (JP, A) JP-A-4-318973 (JP, A) 4-318974 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/205 H01L 21/31 C23C 16/00 H01L 21/336 H01L 29/786 H01L 31/04

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板上に多結晶シリコン薄膜を有する
薄膜トランジスタの製造方法において、前記多結晶シリ
コン薄膜は、シランガスに対する水素ガス流量比を1.
0〜5.0%であるガスを用いて、プラズマを発生させ
るための電極間距離を45mm以下で高周波電力を0.
01〜5.0W/cm2で、反応室内圧力を0.1〜1
0.0Torrで、プラズマ化学気相堆積法により形成
することを特徴とする薄膜トランジスタの製造方法。
1. A method for manufacturing a thin film transistor having a polycrystalline silicon thin film on a substrate, wherein the polycrystalline silicon thin film has a hydrogen gas flow ratio to silane gas of 1.
Using a gas of 0 to 5.0%, a distance between electrodes for generating plasma is set to 45 mm or less, and a high frequency power is set to 0 to 5.0%.
01-5.0 W / cm 2 , the pressure in the reaction chamber is 0.1-1
A method for manufacturing a thin film transistor, wherein the thin film transistor is formed at 0.0 Torr by a plasma enhanced chemical vapor deposition method.
JP03085249A 1991-04-17 1991-04-17 Method for manufacturing thin film transistor Expired - Lifetime JP3116403B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03085249A JP3116403B2 (en) 1991-04-17 1991-04-17 Method for manufacturing thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03085249A JP3116403B2 (en) 1991-04-17 1991-04-17 Method for manufacturing thin film transistor

Publications (2)

Publication Number Publication Date
JPH04318921A JPH04318921A (en) 1992-11-10
JP3116403B2 true JP3116403B2 (en) 2000-12-11

Family

ID=13853298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03085249A Expired - Lifetime JP3116403B2 (en) 1991-04-17 1991-04-17 Method for manufacturing thin film transistor

Country Status (1)

Country Link
JP (1) JP3116403B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766415A (en) * 1993-08-23 1995-03-10 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device and thin-film transistor
JP2978704B2 (en) * 1993-11-29 1999-11-15 日本電気株式会社 Thin film formation method
JP3027968B2 (en) * 1998-01-29 2000-04-04 日新電機株式会社 Film forming equipment
JP4510242B2 (en) * 2000-07-11 2010-07-21 キヤノン株式会社 Thin film formation method

Also Published As

Publication number Publication date
JPH04318921A (en) 1992-11-10

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