JPH04318973A - Thin film transistor and manufacture thereof - Google Patents
Thin film transistor and manufacture thereofInfo
- Publication number
- JPH04318973A JPH04318973A JP8525091A JP8525091A JPH04318973A JP H04318973 A JPH04318973 A JP H04318973A JP 8525091 A JP8525091 A JP 8525091A JP 8525091 A JP8525091 A JP 8525091A JP H04318973 A JPH04318973 A JP H04318973A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- poly
- film transistor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 37
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 abstract description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 8
- 238000002844 melting Methods 0.000 abstract description 8
- 230000008018 melting Effects 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 32
- 238000006243 chemical reaction Methods 0.000 description 15
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- 239000001257 hydrogen Substances 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 229910000077 silane Inorganic materials 0.000 description 7
- 238000005755 formation reaction Methods 0.000 description 6
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000002441 X-ray diffraction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- XPBBUZJBQWWFFJ-UHFFFAOYSA-N fluorosilane Chemical compound [SiH3]F XPBBUZJBQWWFFJ-UHFFFAOYSA-N 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 125000005843 halogen group Chemical group 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910008045 Si-Si Inorganic materials 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910006411 Si—Si Inorganic materials 0.000 description 1
- 238000000333 X-ray scattering Methods 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical group 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】 本発明は、薄膜トランジスタ
、特に多結晶シリコン薄膜トランジスタの製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing thin film transistors, particularly polycrystalline silicon thin film transistors.
【0002】0002
【従来の技術】低融点ガラス上に微結晶または多結晶シ
リコン(poly−Si)を素子材とした、薄膜トラン
ジスタ(TFT)を作成する試みが活発化している。特
に、基板としてコーニング社製7059基板等の低融点
ガラス基板を用い、プロセスの最高温度450℃で、高
移動度、高ON/OFF比のTFTを作成するプロセス
の実用化が待望されている。2. Description of the Related Art Attempts are being made to create thin film transistors (TFTs) using microcrystalline or polycrystalline silicon (poly-Si) as an element material on low-melting glass. In particular, the practical application of a process for producing TFTs with high mobility and a high ON/OFF ratio at a maximum process temperature of 450° C. using a low melting point glass substrate such as Corning's 7059 substrate as a substrate is eagerly awaited.
【0003】従来からpoly−Siをガラス基板上に
成膜するには、減圧CVD法を用いて基板温度600℃
程度でモノシランガスを熱分解する方法が知られている
。また高性能なpoly−SiTFTを作成する従来の
方法は、非晶質Si(a−Si)を固相成長法によって
大粒径化したpoly−Siを形成し、TFTを作成す
る方法や、a−Siやpoly−Siをレーザーアニー
リングによって溶融再結晶化し、TFTを作成する方法
等があった。Conventionally, in order to form a poly-Si film on a glass substrate, a low pressure CVD method is used to lower the substrate temperature to 600°C.
A method of thermally decomposing monosilane gas at a certain level is known. In addition, conventional methods for creating high-performance poly-Si TFTs include forming TFTs by forming poly-Si in which amorphous Si (a-Si) is made large in size by solid-phase growth; There is a method of melting and recrystallizing -Si or poly-Si by laser annealing to create a TFT.
【0004】0004
【発明が解決しようとする課題】 しかし減圧CVD
法によるpoly−Siは、成膜温度上の要求から低融
点ガラスを基板に用いることはできない。また固相成長
法によって大粒径poly−Siを得る方法でも、60
0℃程度の温度で4〜70時間という長時間アニールを
しなければならず、低融点ガラスを基板に用いることは
できない。レーザーアニーリングは、レーザービームの
不均一特性による素子特性ばらつきや、スループットが
低い等の問題点があった。[Problem to be solved by the invention] However, low pressure CVD
Poly-Si produced by the method cannot use low-melting point glass as a substrate due to film-forming temperature requirements. In addition, even in the method of obtaining large grain size poly-Si by solid phase growth method, 60
Annealing must be performed at a temperature of about 0° C. for a long time of 4 to 70 hours, and low melting point glass cannot be used for the substrate. Laser annealing has problems such as variations in device characteristics due to non-uniform characteristics of the laser beam and low throughput.
【0005】このため、特開昭63−175417、特
開平2−177368、特開平2−202018、Ma
terialsResearch Society S
imposia Proceedings, Vol
ume 95, p.225 (1987)等に見ら
れるように、プラズマ化学気相成長法(PCVD)で、
シランガスと弗素、フロロシラン等のエッチング性ガス
の混合ガスをグロー放電分解することにより、低温で多
結晶シリコンを製造することのできる方法が注目されて
いる。[0005] For this reason, Japanese Patent Application Laid-Open No. 63-175417, Japanese Patent Application Publication No. 2-177368, Japanese Patent Application Publication No. 2-202018, Ma
terialsResearch Society S
Imposia Proceedings, Vol.
ume 95, p. 225 (1987), etc., by plasma chemical vapor deposition (PCVD),
A method that can produce polycrystalline silicon at low temperatures by glow discharge decomposition of a mixed gas of silane gas and an etching gas such as fluorine or fluorosilane is attracting attention.
【0006】これらの成膜方法で得られたpoly−S
i薄膜は、エッチング性ガスとして弗素ガス等のハロゲ
ンガスやフロロシラン、ジクロルシラン等のハロゲン化
物を含むため、得られたpoly−Si中には弗素や塩
素などのハロゲン原子が不純物として含まれる。pol
y−SiTFTを作製するとき、これらの不純物は結晶
欠陥の原因となり、TFTのリーク電流の増大を引き起
こすので大きな問題となる。Poly-S obtained by these film-forming methods
Since the i-thin film contains a halogen gas such as fluorine gas and a halide such as fluorosilane and dichlorosilane as an etching gas, the obtained poly-Si contains halogen atoms such as fluorine and chlorine as impurities. pol
When manufacturing a y-Si TFT, these impurities pose a major problem because they cause crystal defects and increase leakage current of the TFT.
【0007】本発明は以上の問題点を解決するもので、
その目的は低融点ガラス上に作成する高性能のpoly
−SiTFT、及びその製造方法を提供することにある
。[0007] The present invention solves the above problems.
The purpose is to create high-performance poly on low-melting glass.
- An object of the present invention is to provide a SiTFT and a method for manufacturing the same.
【0008】[0008]
【課題を解決するための手段】本発明の薄膜トランジス
タは、非晶質基板上に形成した多結晶シリコンをその主
要部として用いた薄膜トランジスタにおいて、前記多結
晶シリコンは結晶方位が{110}方位の優先配向とな
っていることを特徴とする。[Means for Solving the Problems] A thin film transistor of the present invention uses polycrystalline silicon formed on an amorphous substrate as its main part, wherein the polycrystalline silicon has a preferential crystal orientation of {110} orientation. It is characterized by being oriented.
【0009】本発明の薄膜トランジスタの製造方法は、
前記非晶質基板上に薄膜トランジスタを形成する方法に
おいて、前記多結晶シリコンはプラズマ化学気相成長法
で作成することを特徴とする。The method for manufacturing a thin film transistor of the present invention includes:
In the method for forming a thin film transistor on the amorphous substrate, the polycrystalline silicon is formed by plasma chemical vapor deposition.
【0010】0010
【実施例】以下、本発明の製造方法について詳述する。
使用する基板は単結晶Si以外の基板なら、低融点ガラ
スでもセラミック基板等でも、石英基板でもよい。単結
晶Siを基板に使用するとpoly−Siではなくエピ
タキシャルSi膜が得られる。本実施例ではコーニング
社製7059基板を使用した。基板は7059基板に限
らず石英基板等、450℃程度までのプロセス温度に耐
えるものならなんでもよい。まず基板100上に、PC
VD法によりソース領域101及びドレイン領域102
となるドープトpoly−Si薄膜を2000〜300
0Å成膜する。成膜ガスはシランガスを水素ガスで希釈
したものににドーピングガスを添加したものを用いる。
例えばn型poly−Siの場合はドーピングガスとし
てホスフィン、アルシン等を用い、p型poly−Si
の場合はジボラン等を用いる。本実施例では、n型の場
合はホスフィン、p型の場合はジボランを用いた。ガス
流量比は、n型でSiH4:H2:PH3=1.800
:98.191:0.009、p型でSiH4:H2:
B2H6=1.800:98.164:0.036とし
た。ガス総流量はn、p型共に200SCCMである。
この成膜ガスを用い、以下に述べるチャネルpoly−
Si成膜時と同様にしてPCVDでドープトpoly−
Siを成膜した。得られたドープトpoly−Siは膜
厚2000Åでn型のシート抵抗が300Ω/□、p型
が膜厚3000Åで500Ω/□という低抵抗が得られ
た。ドープトpoly−Si成膜後、ソース領域101
及びドレイン領域102の形にパタニングする(図2−
(a))。EXAMPLES The manufacturing method of the present invention will be described in detail below. The substrate used may be a substrate other than single crystal Si, such as a low melting point glass, a ceramic substrate, or a quartz substrate. If single crystal Si is used for the substrate, an epitaxial Si film can be obtained instead of poly-Si. In this example, a 7059 substrate manufactured by Corning was used. The substrate is not limited to a 7059 substrate, but may be any substrate that can withstand process temperatures up to about 450° C., such as a quartz substrate. First, a PC is placed on the board 100.
A source region 101 and a drain region 102 are formed by VD method.
Doped poly-Si thin film with 2000 to 300
A film with a thickness of 0 Å is formed. The film-forming gas used is silane gas diluted with hydrogen gas to which doping gas is added. For example, in the case of n-type poly-Si, phosphine, arsine, etc. are used as the doping gas, and p-type poly-Si
In this case, use diborane etc. In this example, phosphine was used for n-type, and diborane was used for p-type. The gas flow ratio is n-type, SiH4:H2:PH3=1.800
:98.191:0.009, p-type SiH4:H2:
B2H6=1.800:98.164:0.036. The total gas flow rate is 200 SCCM for both n-type and p-type. Using this film-forming gas, the channel poly-
Doped poly-
A film of Si was formed. The resulting doped poly-Si had a sheet resistance of 300 Ω/□ for n-type and 500 Ω/□ for p-type at a thickness of 3000 Å with a thickness of 2000 Å. After doped poly-Si film formation, source region 101
and patterning in the shape of the drain region 102 (FIG. 2-
(a)).
【0011】続いて再びPCVD法によりチャネルpo
ly−Siを200〜1500Å成膜する。poly−
Siを成膜するPCVD装置は、平行平板型電極を持つ
アネルバ社製PED−302型を使用した。以下、po
ly−Siの成膜方法について詳述する。図1に本発明
で用いたPCVD装置の概略図を示す。1は反応室、2
は排気管、3は対抗電極、4はガス吹き出し孔、5はガ
ス導入部、6は高周波印加電極、7は基板加熱ヒータ、
8は基板、9は高周波電源である。図1中のWは電極間
距離を表す。成膜ガスにはSiH4、Si2H6、Si
3H8等と、H2の混合ガスを用いる。本実施例ではS
iH4とH2の、混合ガスを用いた。[0011] Next, the channel po
A ly-Si film is formed to a thickness of 200 to 1500 Å. poly-
As a PCVD apparatus for forming Si, a PED-302 model manufactured by Anelva Corporation having parallel plate electrodes was used. Below, po
The method for forming a ly-Si film will be described in detail. FIG. 1 shows a schematic diagram of the PCVD apparatus used in the present invention. 1 is a reaction chamber, 2
is an exhaust pipe, 3 is a counter electrode, 4 is a gas blowing hole, 5 is a gas introduction part, 6 is a high frequency application electrode, 7 is a substrate heating heater,
8 is a substrate, and 9 is a high frequency power source. W in FIG. 1 represents the distance between electrodes. The film forming gas contains SiH4, Si2H6, Si
A mixed gas of 3H8 etc. and H2 is used. In this example, S
A mixed gas of iH4 and H2 was used.
【0012】基本的な反応機構は次に示す式1に従う。
式1の反応において、R1が成膜反応で、R2がエッチ
ング反応である。The basic reaction mechanism follows Formula 1 shown below. In the reaction of Formula 1, R1 is a film forming reaction and R2 is an etching reaction.
【0013】[0013]
【化1】
(nは無次元数)式1において、水素濃度を増して行く
とR2の反応が優勢となるので、結合エネルギーの弱い
Si−H結合はR2のエッチング反応により選択的に切
られる。このためSi−Si結合だけが残ることになり
、このような条件のもとでは基板上にはpoly−Si
が成膜される。一方、シランガス濃度が増えると式1に
おけるR1の成膜反応が優勢となり、基板上には水素濃
度の大きい非晶質シリコン(a−Si)が成膜される。
このようなR1とR2の競合関係は、水素ガス濃度に対
するシランガス濃度の比を変えることによって容易に調
整することができる。従ってpoly−Si薄膜を形成
するには、シランガスを大流量の水素ガスで希釈し、シ
ラン濃度/水素濃度比を少なくとも0.1以下にするこ
とが必要となる。[Formula 1] (n is a dimensionless number) In formula 1, as the hydrogen concentration increases, the reaction of R2 becomes dominant, so the Si-H bond with weak bond energy is selectively broken by the etching reaction of R2. . Therefore, only Si-Si bonds remain, and under these conditions, poly-Si bonds remain on the substrate.
is deposited. On the other hand, when the silane gas concentration increases, the film formation reaction of R1 in Equation 1 becomes dominant, and amorphous silicon (a-Si) with a high hydrogen concentration is formed on the substrate. Such a competitive relationship between R1 and R2 can be easily adjusted by changing the ratio of the silane gas concentration to the hydrogen gas concentration. Therefore, in order to form a poly-Si thin film, it is necessary to dilute the silane gas with a large flow of hydrogen gas and to make the silane concentration/hydrogen concentration ratio at least 0.1 or less.
【0014】実際にpoly−Siを成膜する場合、シ
ラン/水素ガス濃度比はガス流量比でSiH4/H2=
0.5〜5.0%、特に1.0〜3.0%が望ましい。
0.5%より小さいと水素ガスによるエッチング反応が
優勢になりすぎ、デポレートが極端に小さくなり、粒径
も小さいpoly−Siしか成膜されない。5.0%を
越えると成膜反応が優勢となり、a−Siしか成膜され
ない。When actually forming a poly-Si film, the silane/hydrogen gas concentration ratio is the gas flow rate ratio, SiH4/H2=
0.5-5.0%, especially 1.0-3.0% is desirable. If it is less than 0.5%, the etching reaction due to hydrogen gas becomes too dominant, the deposit rate becomes extremely small, and only poly-Si with a small particle size is formed. When it exceeds 5.0%, the film forming reaction becomes dominant and only a-Si is formed.
【0015】反応室内の圧力は0.1〜10.0Tor
rで、特に0.3〜1.5Torrが好ましい。プラズ
マを発生させる高周波電力は、電力密度0.01〜5.
0W/cm2、好ましくは0.03〜0.06W/cm
2とする。
0.01W/cm2より小さいと、エッチング反応が弱
くなりすぎ、5W/cm2を越えると薄膜がプラズマダ
メージを受け、高品質の膜を形成できない。基板温度は
100〜450℃である。好ましくは200℃〜400
℃とする。基板温度が100℃より低いとa−Siが成
膜され、450℃より高いと本実施例で用いている70
59基板の耐熱温度を越えてしまい、低温成膜PCVD
の利点を生かせなくなる。[0015] The pressure inside the reaction chamber is 0.1 to 10.0 Torr.
r is particularly preferably 0.3 to 1.5 Torr. The high frequency power for generating plasma has a power density of 0.01 to 5.
0W/cm2, preferably 0.03-0.06W/cm
Set it to 2. If it is less than 0.01 W/cm2, the etching reaction becomes too weak, and if it exceeds 5 W/cm2, the thin film will suffer plasma damage, making it impossible to form a high quality film. The substrate temperature is 100-450°C. Preferably 200℃~400℃
℃. When the substrate temperature is lower than 100°C, a-Si is formed, and when the substrate temperature is higher than 450°C, the 70°C film used in this example is formed.
59 The heat-resistant temperature of the substrate was exceeded, so low-temperature film formation PCVD was performed.
You will not be able to take advantage of the advantages of
【0016】poly−Siを成膜するための重要な条
件は、平行平板型PCVD装置の対向電極間距離(以下
、電極間距離;図1のW)である。エッチング反応が進
むためには、電極間距離が十分に短く、水素が活性状態
で基板上に到達しなければならない。電極間距離が長い
と、エッチング反応は気相中で起こり、基板上には非晶
質シリコンが成膜される。このため、電極間距離Wは、
高周波電力と圧力によって規定される。高周波電力が0
.03 W/cm2で、圧力が1.2Torrの場合
は、電極間距離Wは45mm未満、好ましくは27mm
以下、更に好ましくは20mm以下である必要がある。
本実施例ではW=20mmとした。成膜前に1×10−
6Torr以下の真空にした反応室内にSiH4:H2
=1.8:98.2の混合ガスを総流量200SCCM
で供給し、内圧を1.2Torrに調整した。基板温度
を230℃に設定した後、基板温度が安定するまで約2
0分間成膜ガスを流した。次いで13.56MHzの高
周波電源を用いて、放電電力0.03W/cm2で44
分間放電し、7059基板上にシリコン薄膜を約100
0Å成長させた。また、従来からPCVD法ではa−S
i等の成膜時にパーティクルが発生し、これがTFTデ
バイスの歩留まりを低下させる大きな原因となっていた
。ところが本発明の製造方法ではパーティクルの発生が
殆どないため、TFTデバイスの歩留まり向上に大きな
効果がある。An important condition for forming a poly-Si film is the distance between opposing electrodes (hereinafter referred to as interelectrode distance; W in FIG. 1) of the parallel plate type PCVD apparatus. In order for the etching reaction to proceed, the distance between the electrodes must be sufficiently short and hydrogen must reach the substrate in an active state. When the distance between the electrodes is long, the etching reaction occurs in the gas phase, and amorphous silicon is deposited on the substrate. Therefore, the distance W between the electrodes is
Defined by high frequency power and pressure. High frequency power is 0
.. 03 W/cm2 and the pressure is 1.2 Torr, the distance W between the electrodes is less than 45 mm, preferably 27 mm.
Hereinafter, it is more preferably 20 mm or less. In this example, W=20 mm. 1×10− before film formation
SiH4:H2 is placed in a reaction chamber with a vacuum of 6 Torr or less.
= 1.8:98.2 mixed gas with a total flow rate of 200SCCM
The internal pressure was adjusted to 1.2 Torr. After setting the substrate temperature to 230℃, wait approximately 2 hours until the substrate temperature stabilizes.
The film forming gas was allowed to flow for 0 minutes. Next, using a 13.56 MHz high frequency power source, a discharge power of 0.03 W/cm2 was used for 44
Discharge for about 10 minutes and deposit a silicon thin film on the 7059 substrate.
It was grown to 0 Å. In addition, conventionally in the PCVD method, a-S
Particles are generated during the formation of films such as i, and this has been a major cause of lowering the yield of TFT devices. However, since the manufacturing method of the present invention generates almost no particles, it has a great effect on improving the yield of TFT devices.
【0017】本発明のPCVD法による成膜方法では、
poly−Siの膜厚が1000と比較的薄くても、平
均結晶粒径が1000Å程度のpoly−Siが成膜さ
れていることがX線回折の測定から明かとなった。また
結晶方位は(111)、(220)方位のX線回折ピー
クを観測しており、特に(220)方位が優先配向とな
るpoly−Si薄膜が得られている。尚、ここで言う
「(hkl)方位の優先配向」とは、式2で定義される
結晶配向因子O(hkl)において、O(hkl)>0
.5となるような場合を言う。In the film forming method using the PCVD method of the present invention,
X-ray diffraction measurements revealed that even though the poly-Si film thickness was relatively thin at 1000 Å, the poly-Si film had an average crystal grain size of about 1000 Å. In addition, X-ray diffraction peaks in the (111) and (220) crystal orientations have been observed, and in particular, poly-Si thin films in which the (220) orientation is preferentially oriented have been obtained. Note that the "preferred orientation of (hkl) orientation" referred to here means that in the crystal orientation factor O(hkl) defined by Equation 2, O(hkl)>0
.. This is a case where the value is 5.
【0018】[0018]
【化2】
O(hkl)=I(hkl)/ΣhklI
(hkl)
(式2)ここにI(hkl)は{hkl}
面からのX線回折強度を、試料膜厚とX線散乱角とで規
格化したものである。即ち、{hkl}面からのX線回
折強度をi(hkl)とし、2θを散乱角とすると、I
hklは式3で与えられる。[Chemical formula 2] O(hkl)=I(hkl)/ΣhklI
(hkl)
(Formula 2) where I(hkl) is {hkl}
The X-ray diffraction intensity from the surface is normalized by the sample film thickness and the X-ray scattering angle. That is, if the X-ray diffraction intensity from the {hkl} plane is i(hkl) and 2θ is the scattering angle, I
hkl is given by Equation 3.
【0019】[0019]
【化3】
I(hkl)=i(hkl)/(1−exp(
−2μt/sinθ)) (式3)ここにμは、シリ
コンのCuKα線の吸収係数の逆数、tは膜厚である。[Chemical formula 3] I(hkl)=i(hkl)/(1-exp(
−2 μt/sin θ)) (Formula 3) where μ is the reciprocal of the absorption coefficient of CuKα rays of silicon, and t is the film thickness.
【0020】エッチングガスにハロゲン系のガスを用い
る場合は、膜厚が2500Å以上から多結晶化が始まる
ことが知られており、薄膜化が困難だったが、本発明の
製造方法によれば、poly−Siの薄膜化が可能とな
るためTFTの応用に際し効果は大きい。When a halogen-based gas is used as an etching gas, it is known that polycrystalization begins when the film thickness exceeds 2500 Å, making it difficult to reduce the film thickness.However, according to the manufacturing method of the present invention, Since it is possible to make the poly-Si film thinner, it has a great effect when applied to TFTs.
【0021】このようにして成膜したpoly−Siを
チャネル領域103の形にパタニングする(図2−(b
))。続いてこの上にゲート絶縁膜のSiO2104を
約500〜1500Å成膜する(図2−(c))。
成膜方法はAr+O2混合ガス雰囲気中でのマグネトロ
ンスパッタ法が膜室の優れたSiO2が基板温度=20
0℃程度の低温で得られるので好ましい。ArとO2と
の混合比はO2/(Ar+O2)=0.3程度が好まし
い。電子サイクロトロン共鳴プラズマCVD法でも低温
で高品質のSiO2が得られる。またゲート絶縁膜はP
CVD法による窒化シリコン膜でも良い。The poly-Si thus formed is patterned into the shape of the channel region 103 (see FIG. 2-(b)).
)). Subsequently, a gate insulating film of SiO2104 is formed thereon to a thickness of about 500 to 1500 Å (FIG. 2-(c)). The film forming method is the magnetron sputtering method in an Ar+O2 mixed gas atmosphere.
It is preferable because it can be obtained at a low temperature of about 0°C. The mixing ratio of Ar and O2 is preferably about O2/(Ar+O2)=0.3. High quality SiO2 can also be obtained at low temperatures using the electron cyclotron resonance plasma CVD method. Also, the gate insulating film is P
A silicon nitride film formed by CVD may also be used.
【0022】次いでゲート電極105となるCr、Mo
/Ta、Al等の金属を室温〜300℃程度の温度で、
スパッタ等で成膜、パタニングする(図2−(d))。
ゲート電極はPCVD法によるドープトpoly−Si
でも良い。次いで層間絶縁膜のSiO2106を約50
00〜8000Å成膜する(図2−(e))。コンタク
トホールを空け、最後に配線電極の金属(Al等)を約
7000Å成膜し、ソース電極106、及びドレイン電
極107にパタニングしてTFTの完成となる(図2−
(f))。Next, the gate electrode 105 is made of Cr, Mo.
/Ta, Al, and other metals at a temperature of about room temperature to 300°C,
A film is formed and patterned by sputtering or the like (FIG. 2-(d)). The gate electrode is made of doped poly-Si by PCVD method.
But it's okay. Next, the interlayer insulating film of SiO2106 is deposited at about 50%
A film with a thickness of 00 to 8000 Å is formed (FIG. 2-(e)). A contact hole is made, and finally a metal (Al, etc.) for the wiring electrode is deposited to a thickness of approximately 7000 Å, and the source electrode 106 and drain electrode 107 are patterned to complete the TFT (Figure 2-
(f)).
【0023】本発明のpoly−SiTFTの電界効果
移動度μはnチャネルで40cm2/Vs、pチャネル
で20cm2/Vsであった。これに対し{110}方
位の結晶配向率が50%未満で平均結晶粒径が1000
Å程度の従来のpoly−SiTFTのμはnチャネル
で15cm2/Vs、pチャネルで10cm2/Vsで
ある。結晶配向を{110}方位に揃えることによりT
FTの移動度を増大できる。The field effect mobility μ of the poly-Si TFT of the present invention was 40 cm 2 /Vs for n-channel and 20 cm 2 /Vs for p-channel. On the other hand, when the crystal orientation rate of {110} direction is less than 50% and the average crystal grain size is 1000
The μ of a conventional poly-Si TFT of approximately Å is 15 cm 2 /Vs for n-channel and 10 cm 2 /Vs for p-channel. By aligning the crystal orientation to {110} direction, T
The mobility of FT can be increased.
【0024】[0024]
【発明の効果】本実施例のようにpoly−Siの結晶
方位が{110}方位に優先配向している膜でTFTを
作成すると、TFTの電界効果移動度を大きくすること
ができる。また、poly−Si成膜時に用いるエッチ
ング性ガスは水素であるためTFT特性に悪影響を及ぼ
すハロゲン原子が膜中に混入する心配はない。また従来
のLPCVD法、固相成長法、レーザーアニーリング法
等で得られたpoly−Siは、その結晶粒界にダング
リングボンドがあるため電気的特性が劣化するという問
題点があり、これを解決するためにpoly−Siを成
膜後、水素プラズマ等の方法によってダングリングボン
ドをパッシベートする必要があった。ところが本発明の
方法によるpoly−Si薄膜は、成膜時にすでに水素
プラズマにさらされているので、水素パッシベーション
を後から施す必要はないという利点がある。Effects of the Invention When a TFT is fabricated using a film in which the crystal orientation of poly-Si is preferentially oriented in the {110} direction as in this embodiment, the field effect mobility of the TFT can be increased. Further, since the etching gas used in forming the poly-Si film is hydrogen, there is no fear that halogen atoms, which have a negative effect on TFT characteristics, will be mixed into the film. In addition, poly-Si obtained by conventional LPCVD methods, solid phase growth methods, laser annealing methods, etc. has the problem of deteriorating electrical properties due to dangling bonds at the grain boundaries. In order to do this, after forming a poly-Si film, it was necessary to passivate the dangling bonds using a method such as hydrogen plasma. However, since the poly-Si thin film formed by the method of the present invention is already exposed to hydrogen plasma during film formation, it has the advantage that it is not necessary to perform hydrogen passivation afterwards.
【0025】以上のように本発明は大型・高精細が要求
される液晶パネル、駆動回路内蔵型密着型イメージセン
サ、4Mビット以上の高集積化SRAM用の負荷素子、
IC、LSIをはじめ、3次元SOI素子等、半導体素
子全般への応用に効果が大きい。As described above, the present invention is applicable to liquid crystal panels that require large size and high definition, contact type image sensors with built-in drive circuits, load elements for highly integrated SRAMs of 4 Mbits or more,
It is highly effective for application to general semiconductor devices such as ICs, LSIs, and three-dimensional SOI devices.
【図1】 本発明で用いたPCVD装置の概略図。FIG. 1 is a schematic diagram of the PCVD apparatus used in the present invention.
【図2】 本発明の薄膜トランジスタの製造工程を示
す工程図。FIG. 2 is a process diagram showing the manufacturing process of the thin film transistor of the present invention.
1………反応室 2………排気管 3………対抗電極 4………ガス吹き出し孔 5………ガス導入部 6………高周波印加電極 7………基板加熱ヒータ 8………基板 9………高周波電源 100………基板 101………ソース領域 102………ドレイン領域 103………チャネル領域 104………ゲート絶縁膜 105………ゲート電極 106………層間絶縁膜 107………ソース電極 108………ドレイン電極 1……Reaction chamber 2...Exhaust pipe 3……Counter electrode 4...Gas blowout hole 5...Gas introduction part 6...High frequency application electrode 7...Substrate heater 8......Substrate 9……High frequency power supply 100……Substrate 101……Source area 102……Drain area 103……Channel area 104...Gate insulating film 105……Gate electrode 106……Interlayer insulation film 107... Source electrode 108...Drain electrode
Claims (5)
ンをその主要部として用いた薄膜トランジスタにおいて
、前記多結晶シリコンは結晶方位が{110}方位の優
先配向となっていることを特徴とする薄膜トランジスタ
。1. A thin film transistor using polycrystalline silicon formed on an amorphous substrate as its main part, characterized in that the polycrystalline silicon has a preferential crystal orientation of {110} orientation. Thin film transistor.
を形成する方法において、前記多結晶シリコンはプラズ
マ化学気相成長法で作成することを特徴とする薄膜トラ
ンジスタの製造方法。2. A method of manufacturing a thin film transistor on the amorphous substrate, wherein the polycrystalline silicon is formed by plasma chemical vapor deposition.
徴とする請求項2記載の薄膜トランジスタの製造方法。3. The method for manufacturing a thin film transistor according to claim 2, wherein the temperature in the entire process is 450° C. or lower.
がプラズマ化学気相成長法で形成されることを特徴とす
る請求項2記載の薄膜トランジスタの製造方法。4. The method of manufacturing a thin film transistor according to claim 2, wherein the channel region of the thin film transistor is formed by plasma chemical vapor deposition.
イン領域がプラズマ化学気相成長法で形成されることを
特徴とする請求項2記載の薄膜トランジスタの製造方法
。5. The method of manufacturing a thin film transistor according to claim 2, wherein the source and drain regions of the thin film transistor are formed by plasma chemical vapor deposition.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8525091A JPH04318973A (en) | 1991-04-17 | 1991-04-17 | Thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8525091A JPH04318973A (en) | 1991-04-17 | 1991-04-17 | Thin film transistor and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04318973A true JPH04318973A (en) | 1992-11-10 |
Family
ID=13853326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8525091A Pending JPH04318973A (en) | 1991-04-17 | 1991-04-17 | Thin film transistor and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04318973A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999052013A1 (en) * | 1998-03-31 | 1999-10-14 | Matsushita Electric Industrial Co., Ltd. | Tft array substrate for liquid crystal display and method of producing the same, and liquid crystal display and method of producing the same |
KR100536523B1 (en) * | 1997-07-23 | 2006-02-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor thin film and semiconductor device |
KR100535164B1 (en) * | 1997-06-06 | 2006-03-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor Thin Films and Semiconductor Devices |
US7834356B2 (en) * | 2001-11-14 | 2010-11-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
US7998844B2 (en) | 1993-10-29 | 2011-08-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
-
1991
- 1991-04-17 JP JP8525091A patent/JPH04318973A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7998844B2 (en) | 1993-10-29 | 2011-08-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
KR100535164B1 (en) * | 1997-06-06 | 2006-03-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor Thin Films and Semiconductor Devices |
KR100536523B1 (en) * | 1997-07-23 | 2006-02-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor thin film and semiconductor device |
WO1999052013A1 (en) * | 1998-03-31 | 1999-10-14 | Matsushita Electric Industrial Co., Ltd. | Tft array substrate for liquid crystal display and method of producing the same, and liquid crystal display and method of producing the same |
US6472297B1 (en) | 1998-03-31 | 2002-10-29 | Matsushita Electric Industrial Co., Ltd. | Method of producing TFT array substrate for liquid crystal display device |
US7834356B2 (en) * | 2001-11-14 | 2010-11-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
US8043905B2 (en) | 2001-11-14 | 2011-10-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
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