JPH04318903A - Laminated varistor - Google Patents

Abstract

PURPOSE:To provide a laminated varistor which can reduce leak currents while lowering voltage. CONSTITUTION:A laminated varistor 1, which gets voltage nonlinear property at the interfaces between semiconductor ceramic layers 2 and inner electrodes 3 by piling the semiconductor ceramic layers 2 and inner electrodes 3 alternately to make a sintered body, is constituted. And glass layers 7 are interposed between the above ceramic layers 2 and the inner electrodes 3. Moreover, these glass layers 7 contain B, Si, and at least two kinds out of Pb, Bi, and Zn, and the thickness of the above glass layer is 0.3mum or below.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a multilayer varistor that functions as a voltage nonlinear resistor, and particularly to a multilayer varistor that functions as a voltage nonlinear resistor, and in particular, when a voltage nonlinear resistance characteristic is obtained at the interface between an internal electrode and a semiconductor ceramic layer, a low voltage varistor is used. This invention relates to a structure that can reduce leakage current while achieving a high level of performance.

0002

2. Description of the Related Art Generally, voltage nonlinear resistors (hereinafter referred to as varistors) whose resistance value changes nonlinearly in accordance with applied voltage are widely used as surge absorbing elements and voltage stabilizing elements. The electrical characteristics of such a varistor are I
/i=(V/Vi)a. Above, I is the current flowing through the element, V is the applied voltage, and Vi is the voltage between the terminals when a current of iA flows through the element, usually 1 m
It takes the value of A and is called the varistor voltage V1mA. Further, the above a is a voltage nonlinear coefficient, which indicates how the voltage is controlled when the varistor is incorporated into an electric circuit, and the larger the a value, the better the voltage control. Furthermore, in a low current region, the higher the resistance value, the better the performance. If this leakage current value is large, power consumption increases and causes thermal runaway. In addition, in the field of electronic devices used in communication equipment and other devices in recent years, miniaturization and lower drive voltages are rapidly progressing, and with this, varistors are also undergoing efforts to improve packaging density. There is a growing demand for ultra-miniaturization and lower voltage. In order to meet such requirements, a multilayer varistor has been proposed (see, for example, Japanese Patent Publication No. 58-23921). This multilayer varistor has a structure in which semiconductor ceramic layers and internal electrodes are alternately stacked to form a laminate, and external electrodes are formed on both end surfaces of the laminate to which one end surface of each of the internal electrodes is connected. be. By the way, the varistor voltage in the multilayer varistor described above depends on the number of grain boundaries in the thickness direction of the ceramic layer between the internal electrodes, so in order to lower the varistor voltage, it is necessary to shorten the distance between the internal electrodes. , the number of grain boundaries is reduced by increasing the grain size of the ceramic particles.

0003

[Problems to be Solved by the Invention] However, in the conventional multilayer varistor described above, when the number of ceramic grain boundaries is reduced in order to lower the voltage, pores are likely to occur at the interface between the internal electrode and the semiconductor ceramic layer. As a result, discharge occurs between the internal electrodes and current flows on the surface of the ceramic grain boundaries, resulting in an increase in leakage current.

The present invention has been made in view of the above-mentioned conventional situation, and an object of the present invention is to provide a multilayer varistor that can reduce leakage current while lowering the voltage.

[0005]

[Means for Solving the Problems] The inventors of the present invention have studied to improve the above leakage current, and found that by filling the pores that occur at the interface between the internal electrodes and the ceramic layer with an insulating material, the discharge between the internal electrodes can be improved. The inventors discovered that it is possible to avoid current flowing through ceramic grain boundaries and ceramic grain boundaries, and came to the conclusion that glass is most suitable as such an insulator, leading to the present invention. Therefore, the invention of claim 1 forms a laminate by alternately stacking semiconductor ceramic layers and internal electrodes,
The multilayer varistor is characterized in that a nonlinear voltage characteristic is obtained at the interface between the semiconductor ceramic layer and the internal electrode, in which a glass layer is interposed at the interface between the semiconductor ceramic layer and the internal electrode. Further, the invention of claim 2 provides that the glass layer contains B, Si, and Pb, Bi, Z.
The glass layer is characterized in that at least two types of n are added, and the thickness of the glass layer is 0.3 μm or less. Here, the reason why the thickness of the glass layer is set to 0.3 μm or less is because if the thickness exceeds this, the limiting voltage increases and the surge resistance deteriorates, and the characteristics deteriorate on the contrary.

[0006]

[Function] According to the multilayer varistor of the present invention, since the glass layer is interposed at the interface between the internal electrode and the semiconductor ceramic layer, the glass layer fills the pores that occur at the interface between the internal electrode and the ceramic layer, and As a result, discharge between internal electrodes and current flowing through ceramic grain boundaries can be avoided, reducing leakage current while lowering voltage, which in turn solves the problems of power consumption and thermal runaway. can.

[0007]

Embodiments Hereinafter, embodiments of the present invention will be explained with reference to the drawings. 1 to 3 are diagrams for explaining a multilayer varistor according to an embodiment of the present invention. In the figure, numeral 1 indicates a multilayer varistor of this embodiment. This varistor 1 has a rectangular parallelepiped shape, and is made by alternately laminating semiconductor ceramic layers 2 mainly composed of ZnO and internal electrodes 3 made of Pt, and integrally firing the laminated body to form a sintered body 4. It is configured. Further, one end surface 3a of each of the internal electrodes 3 is led out alternately to the left and right end surfaces 4a and 4b of the sintered body 4, and the other end surfaces are located inside the ceramic layer 2 and are drawn out inside the sintered body 4. is enclosed in. Furthermore, the left and right end surfaces 4a of the sintered body 4
, 4b are formed with an external electrode 5 made of Ag/Pd, and the external electrode 5 is electrically connected to one end surface 3a of the internal electrode 3. Note that ceramic layers 6 as dummy are provided on the upper and lower surfaces of the sintered body 4.

A glass layer 7 is inserted between each of the internal electrodes 3 and the semiconductor ceramic layer 2 exhibiting varistor characteristics. This glass layer 7 has a size that covers the internal electrodes 3, and is disposed on the inner surface of the uppermost and lowermost internal electrodes 3, and on both sides of the two central internal electrodes 3. ing. Further, the glass layer 7 is doped with B, Si, and at least two kinds selected from Pb, Bi, and Zn, and the thickness of the glass layer 7 is 0.1 to 0.3 μm. It is within the range. Thereby, the interface between each of the internal electrodes 3 and the ceramic layer 2 is insulated.

Next, a method for manufacturing the multilayer varistor 1 of this embodiment will be explained. First, ZnO (98.2 mol
%), Bi2 O3 (0.5 mol %), Mn
O2 (0.5mol%), Co2 CO3 (0.5mol%)
1%), Sb2O3 (0.3 mol%), B2O3, SiO2
, PbO, and ZnO at 1.0
wt% is added as a raw material, and an organic binder is mixed therein. After forming a green sheet with a thickness of 20 μm using a doctor blade method, the green sheet is cut into rectangular shapes to form a large number of ceramic layers 2.

On the other hand, an electrode paste is prepared by mixing Pt with an organic vehicle. Further, a glass paste is prepared by mixing an organic vehicle with a glass powder made of B2 O3 and SiO2. Then, on the upper surface of the ceramic layer 2, a glass layer 7 is first formed by screen printing a glass paste. In this case, the glass layer 7 is formed at a position corresponding to the internal electrode 3. Next, an electrode paste is screen printed on the top surface of the glass layer 7 to form the internal electrodes 3. As a result, one end surface 3a of the internal electrode 3 is located at the outer edge of the ceramic layer 2, and the remaining end surfaces are located inside the ceramic layer 2. Next, the glass paste is screen printed on the upper surfaces of both internal electrodes 3 in the center except for the top and bottom to form a glass layer 7. As a result, each of the internal electrodes 3 is sandwiched between the glass layers 7.

Next, as shown in FIG. 3, the ceramic layers 2 and the internal electrodes 3 are alternately overlapped, and the internal electrodes 3
The ceramic layer 2 is laminated so that only one end surface 3a thereof is exposed alternately on the left and right end surfaces of the ceramic layer 2, and a dummy ceramic layer 6 is provided on the upper and lower surfaces thereof. Next, this is pressed in the stacking direction with a press to form a laminate, which is then cut into a predetermined size. As a result, only one end surface 3a of each internal electrode 3 is exposed alternately on both end surfaces of the laminate, and the glass layer 7 is interposed between each internal electrode 3 and the ceramic layer 2.

[0012] Then, the above laminate was heated in air for 900 min.
The sintered body 4 is heated and fired at a temperature of ~1300°C for a predetermined time.
get. During this firing, the glass component softens and fills the pores present near the interface of the ceramic layer 2.

Finally, a conductive paste made of Ag with Pb added is applied to the left and right end surfaces 4a and 4b of the sintered body 4 where one end surface 3a of the internal electrode 3 is exposed, and then baked to form the external surface. Electrode 5 is formed. In this way, the laminated varistor 1 of this example is manufactured.

As described above, according to this embodiment, the internal electrode 3
Since the glass layer 7 is arranged between the inner electrode 3 and the ceramic layer 2, the pores existing near the interface between the internal electrode 3 and the ceramic layer 2 are filled, and as a result, the leakage current is reduced while lowering the voltage. Therefore, an increase in power consumption can be avoided, and thermal runaway can be avoided.

[0015]

[Table 1]

[0016]

[Table 2]

Next, the results of tests conducted to confirm the effects of the multilayer varistor 1 of this embodiment will be explained. This test was performed using B2 O3 -SiO2 as shown in Table 1.
-PbO system (first column A), B2 O3 -SiO2
-Bi2O3 system (second column B), B2O3 -Si
O2 -PbO-Bi2 O3 system (third column C), B2
A glass paste was prepared by mixing four types of glass powder consisting of O3 -SiO2 -ZnO system (fourth column D) with an organic vehicle, and the thickness of each glass layer was 0.1 to 0.
．． A multilayer varistor was fabricated using the above manufacturing method so that the thickness was 5 μm. Note that the above film thickness is the thickness when printed on a green sheet. Then, V1mA, V3A (voltage value required to flow 3A of current), a (voltage nonlinear coefficient), and surge withstand capacity (8/2) of each multilayer varistor.
An impulse current of 0 μS was applied twice at 5 minute intervals,
The maximum current value at which the rate of change of the varistor voltage was within ±10%) and the leakage current (current value flowing when DC 2V was applied) were measured. For comparison, similar measurements were also performed on a conventional multilayer varistor without a glass layer. Table 2 shows the results. As is clear from the same table, in the conventional sample, V1mA
, α have the original characteristics, but the leakage current is as large as 10 μA. On the other hand, samples A to D of this example all satisfy the characteristics such as V1mA, α, and surge resistance, and the leakage current is significantly reduced to 0.01 to 0.3 μA. I understand that. On the other hand, the glass layer is 0.4μ
In the comparison sample exceeding 20 m, although the leakage current reduction effect was obtained, V3A became a high voltage and the surge resistance deteriorated, and from this result, the thickness of the glass layer was 0.3
It is desirable that it is less than μm.

[0018]

[Effects of the Invention] As described above, according to the multilayer varistor of the present invention, since the glass layer is interposed at the interface between the internal electrode and the ceramic layer, the leakage current can be reduced while lowering the voltage. be.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining a multilayer varistor according to an embodiment of the present invention.

FIG. 2 is a perspective view of the multilayer varistor of the above embodiment.

FIG. 3 is an exploded perspective view for explaining the method of manufacturing the multilayer varistor of the above embodiment.

[Explanation of symbols]

1. Multilayer varistor 2 Semiconductor ceramic layer 3 Internal electrode 4 Sintered body (laminate) 7 Glass layer

Claims (2)

[Claims] 1. A multilayer varistor comprising a laminate formed by alternately stacking semiconductor ceramic layers and internal electrodes to obtain non-linear voltage characteristics at the interface between the semiconductor ceramic layers and the internal electrodes, wherein the semiconductor A multilayer varistor characterized by having a glass layer interposed at the interface between the ceramic layer and the internal electrode. 2. In claim 1, the glass layer comprises:
B, Si, and at least two of Pb, Bi, and Zn are contained, and the thickness of the glass layer is 0.
A multilayer varistor characterized by having a thickness of 3 μm or less.