JPH04314356A - Semiconductor device mounting device and fabrication thereof - Google Patents

Abstract

PURPOSE:To prevent the migration of copper for providing a semiconductor mounting device with an improved insulting resistance characteristic in the semiconductor device mounting device where a copper wiring is wired in high density. CONSTITUTION:In a semiconductor device mounting device 10 where an organic insulating base material 1, an adhesive sheet, and a copper wiring layer 2 are laminated into multilayer, a surface not in contact with the insulating base material 1 of the copper wiring 2 is covered with a nickel layer or a nickel alloy layer 3 excellent in migration resistance.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for mounting semiconductor elements such as a pin grid array package or a leadless chip carrier, and a method for manufacturing the same.

0002

[Prior Art] Conventionally, devices for mounting semiconductor elements using an organic insulating base material and copper wiring include pin grid array type packages and leadless chip carriers. The structure is such that the copper wiring is directly covered with a resin film such as a solder resist, or the copper wiring is embedded in an insulating base material.

Furthermore, as disclosed in Japanese Patent Application Laid-open No. 59-161850, in a semiconductor device in which parts of the lead wire other than the external connection portion are sealed with resin, at least a portion of the copper lead wire is made of iron. The structure is coated with a binary nickel material.

0004

[Problems to be Solved by the Invention] As described above, in conventional devices for mounting semiconductor elements, the structure in which the copper wiring is covered with a resin film or the copper wiring is buried in an insulating base material is different from the recent one. As the density of copper interconnects increases and the distance between interconnects becomes shorter, copper migration becomes more likely to occur and deterioration of insulation resistance becomes a problem.

Furthermore, in a semiconductor device disclosed in Japanese Patent Laid-Open No. 59-161850 in which a part of the lead wire is coated with a binary iron-nickel material and sealed with resin, the pin grid array is There was a problem in that it could not be applied to mold packages, leadless chip carriers, etc., and the product applications were severely limited.

The present invention has been made in view of these circumstances, and an object of the present invention is to provide a semiconductor device mounting material comprising a multilayer stack of an organic insulating base material, an adhesive sheet, and a copper wiring layer. An object of the present invention is to provide a device for mounting a semiconductor element, which prevents migration of copper ions from occurring even when copper-based wiring layers are wired at high density in the device, and has significantly improved resistance characteristics, and a method for manufacturing the same. .

[0007]

Means for Solving the Problems In order to achieve the above object, the present invention provides a device for mounting a semiconductor element in which an organic insulating base material, an adhesive sheet, and a copper-based wiring layer are laminated in multiple layers. It is characterized in that the surface of the wiring layer that is not in contact with the insulating base material is covered with a nickel layer or a nickel-based alloy layer.

The organic insulating base material and the copper wiring layer include epoxy resin glass cloth base copper clad laminates, polyimide resin glass cloth base copper clad laminates, bismaleimide triazine resin glass cloth base copper clad laminates. Selectively use from among the boards.

Furthermore, adhesive sheets include epoxy films, acrylic films, polyimide films, epoxy resin glass cloth base prepregs, polyimide resin glass cloth base prepregs, bismaleimide triazine resin glass cloth base prepregs, etc. Use selectively from

The nickel layer or nickel-based alloy layer covering the copper-based wiring layer may be formed by plating using an electrolytic nickel plating bath such as a Watt bath, a hypophosphorous acid bath, or a nickel-based alloy layer.
Electroless nickel plating using a plating bath such as a boron bath can be used. At this time, a nickel coating is formed from the Watt bath, a nickel-phosphorus coating is formed from the hypophosphorous acid bath, and a nickel-boron coating is formed from the boron bath.

Next, in the method of manufacturing a semiconductor device mounting device according to the present invention, a desired wiring pattern is formed on a copper-clad laminate, and the surface of the wiring pattern is coated with a nickel layer or a nickel alloy layer by plating. A process of forming a multilayer laminate by heating and pressing nickel-plated wiring boards with an adhesive sheet in between, and drilling a hole to form a through hole in the multilayer laminate. It is characterized by comprising a step of plating the inner conductor layer, through-holes and land portions inside the plate, and a step of covering the outermost conductor layer with an overcoat resin.

[0012] The thickness of the plating film in the nickel plating process is preferably about 1 to 10 μm. In addition, in the nickel plating treatment and copper plating treatment of through holes and land parts, the film thickness of nickel plating is 1 to 10 μm.
The thickness of the copper plating is 5 to 20 μm.

[0013] At this time, it is possible to use both electroless copper plating and electrolytic copper plating for the copper plating treatment.

In addition, in the overcoat resin coating step, epoxy resins, polyimide resins, dosmaleimide triazine resins, etc. can be used as the overcoat resin, and the resin can be formed using printing methods or ultraviolet rays. Either curing method can be selected, and the resin film thickness is 5.
~30 μm is suitable.

Furthermore, the wiring board manufactured by the above method has the following characteristics:
If necessary, nickel plating or gold plating can be applied to support wire bonding, and solder bumps can be formed to form TAB (tape carrier type semiconductor mounting equipment, Tape Automated Bo)
It is also possible to connect a nding).

[0016] Furthermore, as for the external processing, it is divided by cutting with a diamond saw or punching with a press. If the through-hole section is cut with a diamond saw, it can be used as a leadless chip carrier, and if input/output pins for external connections are driven into the through-hole, it can also be used as a pin grid array type package. be.

[0017] Also, the shape of the input/output pin is a header pin,
Either type of middle brim pin may be used.The pin can be fixed by forming a yoke on the pin itself, and then fixed to the connecting land by soldering.The composition of the solder varies depending on the operating temperature.
b/Sn=90/10, 80/20, eutectic solder, etc. can be used.

[0018]

[Function] As is clear from the above structure, even when the copper-based wiring layer is set at high density, the surface of the copper-based wiring layer that does not come into contact with the insulating base material is covered with a nickel layer or nickel layer with excellent migration resistance. Since it is coated with an alloy layer, the elution of copper ions can be reliably suppressed, and insulation deterioration due to copper migration can be reliably prevented.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view of an apparatus for mounting a semiconductor element according to an embodiment of the present invention before external processing, and FIGS. 2 and 3 show intermediate steps in the method for manufacturing the apparatus for mounting a semiconductor element according to the present invention. 4 is a perspective view showing a leadless chip carrier to which the present invention is applied, and FIG. 5 is a perspective view showing a pin grid array type package to which the present invention is applied.

First, the manufacturing process of the leadless chip carrier shown in FIG. 4 will be explained.

First, using the epoxy resin glass cloth base copper-clad laminate MCL-E-679 (trade name manufactured by Hitachi Chemical Co., Ltd.) double-sided copper foil base material 1, the copper surface was polished using an ACL polishing machine (
After preparing the surface with a UV-curable resist film PHT-145F (product name manufactured by Hitachi Chemical Co., Ltd.), a negative mask was placed on the surface, exposed to ultraviolet light, and a 132-pin wiring pattern was printed. Ta.

This was developed with 1.1.1-trichloroethane and etched with a cupric chloride-hydrochloric acid based etching solution. This was applied to a methylene chloride resist stripping machine to obtain wiring pattern 2. The surface of this wiring board was pickled with a 10% hydrochloric acid solution, and then nickel plating 3 (film thickness 2 to 5 μm) was applied in a Watt bath (electro nickel plating bath) as shown in Figure 2. An adhesive sheet 5 was sandwiched between the printed wiring boards 4 and 4', and the printed wiring boards 4 and 4' were laminated together.

As the adhesive sheet 5, an acrylic adhesive sheet Pyralux LF-0200 (trade name manufactured by DuPont) was used, and a press pressure of 19.6×10
90 at 5Pa (20Kgf/cm2) and temperature 180℃
The mixture was heated and pressurized for a minute.

A protective film L-3 is applied to this laminated wiring board.
380 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was laminated, and after drilling a through hole, the inner wall of the through hole was treated with a cedar to adhere a Pd catalyst. HS-201B (trade name, manufactured by Hitachi Chemical Co., Ltd.) was used as the catalyst liquid, and ADP-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was used as the accelerator liquid.

[0026] This was immersed in electroless nickel plating solution Bluesumer S-680 (trade name, manufactured by Nippon Kanigen Co., Ltd.) for 20 minutes, and nickel plated (plating film thickness of 2 to 3 μm).
m) is deposited to produce a nickel-coated multilayer laminate 6 shown in FIG.
I got it.

[0027] Overcoating resin 7 was printed on the wiring board 6 other than the land portions and wire bonding portions, and was cured in a hot air dryer. As the overcoat resin 7, epoxy resin CCR-2200 (trade name, manufactured by Asahi Chemical Research Institute) was used and heated at 130° C. for 20 minutes.

[0028] Plating resist 2990T (trade name manufactured by Nippon Gesco Co., Ltd.) is printed on the wire bonding part, and 140
After drying at ℃ for 20 minutes, electrolytic copper plating was applied to the through-hole and land parts to form a copper plating layer 8 (plating film thickness 1).
0 to 15 μm).

Thereafter, the plating resist was peeled off, and then nickel plating and gold plating were applied to the wire bonding portions, through-hole portions, and land portions to produce a wiring board 10 for mounting a semiconductor element.

At this time, the nickel plating treatment is as follows:
Using a Watts bath, deposit a nickel film with a thickness of 2 to 5 μm,
Temperex 40, which is a cyan bath, is used for gold plating.
1 (product name manufactured by EEJA), gold plating film thickness 1 to 2
μm was deposited.

This wiring board 10 was cut with a diamond saw along the connection through holes to produce a leadless chip carrier 11 shown in FIG. The blade used for cutting was Metal Blade NBC-ZB111.
0 (trade name manufactured by DISCO) was used.

Next, a method for manufacturing a pin grid array type package 13 shown in FIG. 5 as another embodiment of the present invention will be described. The steps up to manufacturing the wiring board 10 for mounting semiconductor elements are the same as in the above embodiment. It is.

After the wiring board 10 was shaped using a router processing machine, the middle collar pins 12 with yoke were driven into the through holes, and the pins and lands were soldered.

The material of the pin is iron-nickel 52 alloy, and the surface is tin-plated. Note that a press was used for driving.

For soldering, Pb/Sn=90/10 was used, and HF-301 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was used as a flux. After soldering, the flux was cleaned with a trichloroethane solvent Soltol 565 (trade name, manufactured by Nippon Alpha Metal Co., Ltd.) to produce a pin grid array type package 13 shown in FIG. 5.

[0036]

[Effects of the Invention] As explained above, the semiconductor element mounting device according to the present invention has a structure in which the surface of the copper-based wiring layer that is not in contact with the organic insulating base material is coated with a nickel layer or a nickel alloy layer. Since the nickel layer or nickel alloy layer has excellent migration resistance, it can prevent copper migration as much as possible, suppress deterioration of insulation resistance between copper wiring, ensure good insulation resistance characteristics, and CAF (Conduct) between halls
It has various effects such as being able to suppress ive Anodic Firament.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the configuration of a semiconductor element mounting device according to an embodiment of the present invention before external processing.

FIG. 2 is a cross-sectional view showing one step in the manufacturing process of the semiconductor element mounting apparatus shown in FIG. 1;

FIG. 3 is a cross-sectional view showing one step in the manufacturing process of the semiconductor element mounting apparatus shown in FIG. 1;

FIG. 4 is a perspective view showing a leadless chip carrier to which a semiconductor device mounting apparatus according to the present invention is applied.

FIG. 5 is a perspective view showing a pin grid array type package to which the semiconductor element mounting apparatus according to the present invention is applied.

[Explanation of symbols]

1 Organic insulating base material 2 Copper wiring 3 Nickel layer 4, 4' Nickel coated printed wiring board 5 Adhesive sheet 6 Coated multilayer wiring board 7 Resin for overcoat 8 Copper plating layer 9 Gold plating for wire bonding 10 Wiring for mounting semiconductor elements Plate 11 Leadless chip carrier 12 Pin

Claims (2)

[Claims] 1. A device for mounting a semiconductor element in which an organic insulating base material, an adhesive sheet, and a copper-based wiring layer are laminated in multiple layers, wherein the surface of the copper-based wiring layer that is not in contact with the insulating base material is a nickel layer or A semiconductor element mounting device characterized by being coated with a nickel-based alloy layer. 2. Forming a desired wiring pattern on a copper-clad laminate, coating the surface of the wiring pattern with a nickel layer or nickel alloy layer by plating, and bonding the nickel-plated wiring boards together with an adhesive sheet. After the process of forming a multilayer laminate by heating and pressurizing the multilayer laminate and drilling the holes to form through holes in the multilayer laminate, the inner conductor layer, through holes, and lands inside the multilayer laminate are plated. 1. A method of manufacturing a device for mounting a semiconductor element, comprising a step of performing a treatment and a step of coating an outermost conductor with an overcoat resin.