JPH04312932A - Semiconductor device and brazing method thereof - Google Patents
Semiconductor device and brazing method thereofInfo
- Publication number
- JPH04312932A JPH04312932A JP990191A JP990191A JPH04312932A JP H04312932 A JPH04312932 A JP H04312932A JP 990191 A JP990191 A JP 990191A JP 990191 A JP990191 A JP 990191A JP H04312932 A JPH04312932 A JP H04312932A
- Authority
- JP
- Japan
- Prior art keywords
- brazing
- semiconductor
- package
- semiconductor device
- brazing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005219 brazing Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 32
- 239000008188 pellet Substances 0.000 claims abstract description 27
- 238000005476 soldering Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 abstract description 15
- 230000017525 heat dissipation Effects 0.000 abstract description 8
- 239000011800 void material Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- 239000000945 filler Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000009736 wetting Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910020658 PbSn Inorganic materials 0.000 description 1
- 101150071746 Pbsn gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体ペレットのろう付
け技術、特に、パッケージ内に配設された半導体ペレッ
トの一主面をパッケージ内面にろう付けして熱伝導路を
形成する構成の半導体装置に用いて効果のある技術に関
するものである。[Industrial Application Field] The present invention relates to a technique for brazing semiconductor pellets, and more particularly, to a semiconductor device having a structure in which one principal surface of a semiconductor pellet disposed in a package is brazed to the inner surface of the package to form a heat conduction path. It concerns techniques that can be used effectively.
【0002】0002
【従来の技術】従来、半導体ペレットのろう付けにおい
ては、例えば、株式会社工業調査会発行、「IC化実装
技術」99頁〜101頁に記載のように、半導体ペレッ
トのパッケージに対する機械的保持、電気的接続、熱放
散などを目的として、ワイヤボンディングに先行して半
導体ペレットをパッケージの所定の位置にフェイスアッ
プに固定するボンディング工程を備えている。BACKGROUND OF THE INVENTION Conventionally, in brazing semiconductor pellets, mechanical holding of semiconductor pellets to a package, For purposes such as electrical connection and heat dissipation, the package includes a bonding process in which the semiconductor pellet is fixed face-up in a predetermined position in the package prior to wire bonding.
【0003】ところで、本発明者は、大型の半導体ペレ
ットのろう付けに伴うボイド発生について検討した。By the way, the present inventor has studied the generation of voids accompanying the brazing of large semiconductor pellets.
【0004】以下は、本発明者によって検討された技術
であり、その概要は次の通りである。[0004] The following are the techniques studied by the present inventor, and the outline thereof is as follows.
【0005】すなわち、WSI(ウェハ・スケール・イ
ンテグレーション:Wafer Scale In
tegration)などのように半導体ペレットサイ
ズが大型化した場合、回路パターンが形成されたベース
上にバンプ電極を有する半導体ペレットを搭載し、上面
がメタライズされた半導体ペレットに天井面が接した状
態で“コ”の字型断面を有するキャップを覆蓋し、キャ
ップとベースの接続部及び半導体ペレットの上面とキャ
ップの内面との接触面をろう付けにより固定している。
このような構成により、使用時の半導体ペレットから発
する熱をろう付け面を介してキャップに逃がし、さらに
大気に熱放散を行うことができる。[0005] That is, WSI (wafer scale integration)
When the size of semiconductor pellets becomes larger, such as in the case of tegration, a semiconductor pellet with bump electrodes is mounted on a base on which a circuit pattern is formed, and the ceiling surface is in contact with the semiconductor pellet whose upper surface is metallized. A cap having a U-shaped cross section is covered, and the connecting portion between the cap and the base and the contact surface between the upper surface of the semiconductor pellet and the inner surface of the cap are fixed by brazing. With such a configuration, heat generated from the semiconductor pellet during use can be released to the cap via the brazing surface, and further heat can be dissipated to the atmosphere.
【0006】[0006]
【発明が解決しようとする課題】ところが、前記の如く
キャップを介して熱放散を行う半導体装置においては、
ろう付け面積が広くなる大型の半導体ペレットのろう付
け部のボイド増大について配慮がされておらず、ろう付
け部のボイド増大によってLSIのPN接合部からの熱
放散性が低下するという問題のあることが本発明者によ
って見い出された。[Problems to be Solved by the Invention] However, in the semiconductor device that dissipates heat through the cap as described above,
No consideration was given to the increase in voids in the brazed part of large semiconductor pellets, which increase the brazing area, and there is a problem that heat dissipation from the PN junction of LSI decreases due to the increase in voids in the brazed part. was discovered by the present inventor.
【0007】そこで、本発明の目的は、ボイドの増大を
防止し、熱放散性の低下を防止することのできる技術を
提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a technique that can prevent an increase in voids and a decrease in heat dissipation performance.
【0008】本発明の前記目的と新規な特徴は、本明細
書の記述及び添付図面から明らかになるであろう。The above objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
【0009】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.
【0010】すなわち、半導体ペレットの放熱面をパッ
ケージにろう付けする半導体装置であって、ろう材の載
置部から外側に向かって延伸するように配列された溝を
前記半導体ペレットまたは前記パッケージの少なくとも
一方のろう付け面に設けるようにしたものである。That is, in a semiconductor device in which a heat dissipating surface of a semiconductor pellet is brazed to a package, grooves arranged so as to extend outward from a brazing material mounting portion are formed on at least one of the semiconductor pellet or the package. It is provided on one brazing surface.
【0011】[0011]
【作用】上記した手段によれば、ろう付け面に設けた溝
は、溶融されたろう材に対し、その溝長さ方向に毛細管
の如くに機能し、ろう材の濡れ広がりを良好にし、ろう
付け面にろう材が緻密に浸透する。したがって、ボイド
の発生を低減できると共に接合表面積を増大させること
ができ、熱放散性の向上及びペレットクラックの発生を
低減することができる。[Operation] According to the above-mentioned means, the groove provided on the brazing surface functions like a capillary tube in the longitudinal direction of the groove for the molten brazing material, and improves the wetting and spreading of the brazing material. The filler metal penetrates into the surface densely. Therefore, it is possible to reduce the occurrence of voids, increase the bonding surface area, improve heat dissipation properties, and reduce the occurrence of pellet cracks.
【0012】0012
【実施例】本発明は図1に示すように、半導体基板1(
半導体ペレット)のろう付け面及び熱伝導材2(パッケ
ージ)のろう付け面に溝加工部3を形成し、この両面を
ろう材4によって接合するところに特徴がある。溝加工
部3は、ろう付け時の溶融したろう材4が流れやすい形
状に加工されている。ここで、半導体基板1には、例え
ばシリコン単結晶基板が用いられ、熱伝導材2には、例
えば窒化アルミニウムが用いられ、ろう材4には、例え
ばPbSn系はんだ材料が用いられる。[Embodiment] As shown in FIG. 1, the present invention has a semiconductor substrate 1 (
The feature is that a grooved portion 3 is formed on the brazing surface of the semiconductor pellet (semiconductor pellet) and the brazing surface of the thermally conductive material 2 (package), and these both surfaces are joined by a brazing material 4. The grooved portion 3 is processed into a shape that allows the melted brazing material 4 to easily flow during brazing. Here, the semiconductor substrate 1 is, for example, a silicon single crystal substrate, the thermally conductive material 2 is, for example, aluminum nitride, and the brazing material 4 is, for example, a PbSn-based solder material.
【0013】なお、図1では半導体基板1と熱伝導材2
の両方に溝加工部3を設けるものとしたが、図2に示す
ように半導体基板1のみにろう材4を設けて熱伝導材2
のろう付け面を平滑面5にすることも、図3に示すよう
に熱伝導材2のみにろう材4を設けて半導体基板1のろ
う付け面を平滑面5にすることもできる。In FIG. 1, a semiconductor substrate 1 and a thermally conductive material 2 are shown.
However, as shown in FIG.
The brazing surface of the semiconductor substrate 1 may be a smooth surface 5, or the brazing surface of the semiconductor substrate 1 may be a smooth surface 5 by providing a brazing material 4 only on the thermally conductive material 2, as shown in FIG.
【0014】図4及び図5は溝加工部3の形状の詳細を
示し、図4は鋸歯状もしくはV字状の溝6を形成した例
を示し、図5はU字形に溝7を形成した例を示している
。この溝6及び溝7を形成するに際しては、ホトエッチ
ング、機械研削、レーザ加工などの手段を用いることが
できる。さらに、溝6及び溝7の表面にはメタライズ層
8が形成されている。メタライズ層8はろう材4の濡れ
を良好にする目的で設けられ、例えば、下地を金にし、
その表面に順次、クロム、銅、金を多層に施したもの、
或いは、下層よりクロム、チタン、タングステンを多層
にした接着層、ニッケル、銅、白金、パラジウム、モリ
ブデンなどからなるバリア層、及びこのバリア層の上に
設けられる金、銀などの酸化防止層の組合せからなるも
のを用いることができる。4 and 5 show details of the shape of the grooved portion 3, FIG. 4 shows an example in which a sawtooth or V-shaped groove 6 is formed, and FIG. 5 shows an example in which a U-shaped groove 7 is formed. An example is shown. When forming the grooves 6 and 7, methods such as photoetching, mechanical grinding, laser processing, etc. can be used. Further, a metallized layer 8 is formed on the surfaces of the grooves 6 and 7. The metallized layer 8 is provided for the purpose of improving wetting of the brazing material 4. For example, the metallized layer 8 is made of gold as a base,
The surface is coated with multiple layers of chrome, copper, and gold,
Alternatively, a combination of an adhesive layer made of multiple layers of chromium, titanium, and tungsten from the bottom, a barrier layer made of nickel, copper, platinum, palladium, molybdenum, etc., and an oxidation prevention layer made of gold, silver, etc. provided on this barrier layer. can be used.
【0015】図6及び図7は半導体基板1上の溝加工部
3の平面図を示し、図6は溝を平行に形成した場合であ
り、図7は中心から外側に放射状に形成した場合を示し
ている。6 and 7 show plan views of the grooved portion 3 on the semiconductor substrate 1. FIG. 6 shows the case where the grooves are formed in parallel, and FIG. 7 shows the case where the grooves are formed radially outward from the center. It shows.
【0016】以上のように、溝6または溝7の形状を有
する溝加工部3を設けたことにより、水平面上の溝は、
その長さ方向に対しては毛細管のように働く。一方、長
さ方向に垂直な溝は、その接触角が閾値になるような位
置が見出されるため、障壁のように振る舞う。溝を横切
る方向への広がりは、溝の間の山の部分が鋭い縁を有す
る場合には、特に抑制される。したがって、図5よりも
図4の方がろう材4の広がりの指向性は良い。このよう
に、ろう材4が溝6(または溝7)を伝って溝加工部3
の全域に浸透するため、ボイドの発生を低減させ、熱放
散性を改善することができる。As described above, by providing the grooved portion 3 having the shape of the groove 6 or the groove 7, the groove on the horizontal plane becomes
It acts like a capillary tube along its length. On the other hand, a groove perpendicular to its length behaves like a barrier because a position is found such that its contact angle is a threshold value. Spreading across the grooves is particularly suppressed if the crests between the grooves have sharp edges. Therefore, the directionality of the spread of the brazing filler metal 4 is better in FIG. 4 than in FIG. 5. In this way, the brazing material 4 travels along the groove 6 (or groove 7) to the grooved part 3.
Since it permeates throughout the entire area, it is possible to reduce the occurrence of voids and improve heat dissipation.
【0017】なお、ろう材4の濡れ広がりを左右する溝
の垂直方向の深さyは、溶融ろう材の表面張力をγl、
溶融ろう材の密度をρ、重力加速度をg、溶融ろう材表
面の曲率半径を等価半径に置き換えた値をRe とする
と、数1で表わされる。Note that the vertical depth y of the groove, which determines the wetting and spreading of the brazing filler metal 4, is determined by the surface tension of the molten brazing filler metal γl,
If the density of the molten brazing material is ρ, the gravitational acceleration is g, and the radius of curvature of the surface of the molten brazing material is replaced by an equivalent radius, Re is expressed by Equation 1.
【0018】[0018]
【数1】y= 2γl/ρgRe
また、半円形断面の溝、あるいは90°の底角度を有す
る矩形断面の溝に対しては、Re ≒2.5yとし、溝
の形がさらに鋭い場合には、Re はより小さくする。
この他、底角度60°に対してはRe ≒y、底角度3
0°に対してはRe ≒0.35yにする。しかし、実
際上、溝により上記効果が得られるのは、溝の凹凸を表
面粗さとして取り扱った場合、150μm(60Ru)
以下の値である。[Equation 1] y= 2γl/ρgRe Furthermore, for a groove with a semicircular cross section or a groove with a rectangular cross section with a base angle of 90°, Re ≒2.5y, and if the groove shape is even sharper, , Re is made smaller. In addition, for a base angle of 60°, Re ≒y, base angle 3
For 0°, Re≈0.35y. However, in reality, the above effect can be obtained by using grooves at 150 μm (60 Ru) when the unevenness of the grooves is treated as surface roughness.
The value is as follows.
【0019】次に、本発明による半導体装置のろう付け
方法について、図8〜図11を参照して説明する。Next, a method for brazing a semiconductor device according to the present invention will be explained with reference to FIGS. 8 to 11.
【0020】図8の(a) 図に示すように、熱伝導材
2の上に所定の大きさに加工されたプリフォームろう材
9を載置し、このプリフォームろう材9の上に溝加工部
3を下にして半導体基板1を載置する。この状態で設置
雰囲気(例えば、O2 が10ppm以下の不活性ガス
、あるいはこれらに10〜20%のH2 を添加したガ
スを含む雰囲気)を加熱すると共に荷重10を付与する
と、図8の(b) 図に示すようにプリフォームろう材
9が溶融し、上記したように溝加工部3内の中央部から
外側に濡れ広がり、ろう材4による接合層が得られる。As shown in FIG. 8(a), a preform brazing material 9 processed to a predetermined size is placed on the thermally conductive material 2, and a groove is formed on the preform brazing material 9. The semiconductor substrate 1 is placed with the processing section 3 facing down. In this state, when the installation atmosphere (for example, an atmosphere containing an inert gas with O2 of 10 ppm or less, or a gas containing 10 to 20% H2 added thereto) and a load of 10 is applied, the result is shown in FIG. 8(b). As shown in the figure, the preform brazing material 9 melts and spreads from the center of the grooved portion 3 to the outside as described above, so that a bonding layer of the brazing material 4 is obtained.
【0021】図9及び図10はプリフォームろう材9の
形状及び載置状態を示す平面図である。ここでは、半導
体基板1が四角形の例を示している。図9は図6の溝配
列に対応するもので、角棒形にし、かつ半導体基板1の
幅相当の長さを有するプリフォームろう材9を半導体基
板1の中央部に溝の長さ方向に直交させて配設している
。また、図10は図7の溝配列に対応するものであり、
角砂糖形のプリフォームろう材9を溝加工部3の中心に
配設している。FIGS. 9 and 10 are plan views showing the shape and placement of the preform brazing filler metal 9. Here, an example is shown in which the semiconductor substrate 1 is square. 9 corresponds to the groove arrangement in FIG. 6, and a preform brazing material 9 having a rectangular bar shape and a length corresponding to the width of the semiconductor substrate 1 is placed in the center of the semiconductor substrate 1 in the longitudinal direction of the grooves. They are arranged orthogonally. Further, FIG. 10 corresponds to the groove arrangement in FIG. 7,
A sugar cube-shaped preform brazing material 9 is arranged at the center of the grooved part 3.
【0022】さらに、図11及び図12は、半導体基板
1が短辺11aと長辺11bを有する長方形の場合であ
り、短辺11a方向の中央でかつ長辺11b間にプリフ
ォームろう材9を載置する。この状態でリフローすると
、プリフォームろう材9の濡れ広がり距離を短縮するこ
とができる。Furthermore, FIGS. 11 and 12 show the case where the semiconductor substrate 1 is a rectangle having a short side 11a and a long side 11b, and a preform brazing material 9 is placed at the center in the direction of the short side 11a and between the long side 11b. Place it. When reflowing is performed in this state, the wetting and spreading distance of the preform brazing material 9 can be shortened.
【0023】以上のように、上記した実施例によれば、
ろう付け面に形成した溝の毛細管効果により、ろう材の
濡れ広がりならびにその方向を制御することができ、更
に、ろう付け面中央よりろう材を供給することによりボ
イドの発生を低減することができる。この結果、LSI
の大型化にも対応できるようになる。また、見掛け上の
固体表面積よりもろう接合に寄与する表面積が大きくな
るので、熱放散性及び接合強度を向上させることができ
る。As described above, according to the above embodiment,
Due to the capillary effect of the grooves formed on the brazing surface, it is possible to control the wetting and spreading of the brazing material as well as its direction, and furthermore, by supplying the brazing material from the center of the brazing surface, the generation of voids can be reduced. . As a result, LSI
It will also be possible to cope with larger sizes. Furthermore, since the surface area contributing to solder bonding is larger than the apparent solid surface area, heat dissipation and bonding strength can be improved.
【0024】[0024]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記の通りである。[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.
【0025】すなわち、半導体ペレットの放熱面をパッ
ケージにろう付けする半導体装置であって、ろう材の載
置部から外側に向かって延伸するように配列された溝を
前記半導体ペレットまたは前記パッケージの少なくとも
一方のろう付け面に設けるようにしたので、ボイドの発
生を低減できると共に接合表面積を増大させることがで
き、熱放散性の向上及びペレットクラックの発生を低減
することができる。That is, in a semiconductor device in which a heat dissipating surface of a semiconductor pellet is brazed to a package, grooves arranged so as to extend outward from a brazing material mounting portion are formed on at least one of the semiconductor pellet or the package. Since it is provided on one brazing surface, it is possible to reduce the generation of voids and increase the bonding surface area, thereby improving heat dissipation and reducing the occurrence of pellet cracks.
【図1】本発明による半導体装置の主要部を示す断面図
である。FIG. 1 is a sectional view showing the main parts of a semiconductor device according to the present invention.
【図2】本発明による溝加工部の他の形状例を示す断面
図である。FIG. 2 is a sectional view showing another example of the shape of the grooved portion according to the present invention.
【図3】本発明による溝加工部の更に他の形状例を示す
断面図である。FIG. 3 is a sectional view showing still another example of the shape of the grooved portion according to the present invention.
【図4】溝加工部の溝形状の一例を示す断面図である。FIG. 4 is a cross-sectional view showing an example of the groove shape of the grooved portion.
【図5】溝加工部の溝形状の他の例を示す断面図である
。FIG. 5 is a cross-sectional view showing another example of the groove shape of the grooved portion.
【図6】溝配列の一例を示す平面図である。FIG. 6 is a plan view showing an example of groove arrangement.
【図7】溝配列の他の例を示す平面図である。FIG. 7 is a plan view showing another example of groove arrangement.
【図8】本発明のろう付け方法を示す説明図である。FIG. 8 is an explanatory diagram showing the brazing method of the present invention.
【図9】図6の溝配列に対応するプリフォームろう材の
形状及び載置状態を示す平面図である。9 is a plan view showing the shape and placement state of the preform brazing material corresponding to the groove arrangement of FIG. 6; FIG.
【図10】図7の溝配列に対応するプリフォームろう材
の形状及び載置状態を示す平面図である。10 is a plan view showing the shape and placement state of a preform brazing material corresponding to the groove arrangement of FIG. 7; FIG.
【図11】長方形の半導体基板形状に対応するプリフォ
ームろう材の形状及び載置状態を示す平面図である。FIG. 11 is a plan view showing the shape and placement state of a preform brazing material corresponding to a rectangular semiconductor substrate shape.
1 半導体基板 2 熱伝導材 3 溝加工部 4 ろう材 5 平滑面 6 溝 7 溝 8 メタライズ層 9 プリフォームろう材 10 荷重 11a 短辺 11b 長辺 1 Semiconductor substrate 2 Thermal conductive material 3 Groove processing section 4 Brazing filler metal 5 Smooth surface 6 Groove 7 Groove 8 Metallized layer 9 Preform brazing filler metal 10 Load 11a Short side 11b Long side
Claims (4)
にろう付けする半導体装置であって、ろう材の載置部か
ら外側に向かって延伸するように配列された溝を前記半
導体ペレットまたは前記パッケージの少なくとも一方の
ろう付け面に設けたことを特徴とする半導体装置。1. A semiconductor device in which a heat dissipating surface of a semiconductor pellet is brazed to a package, wherein grooves arranged so as to extend outward from a brazing material placement part are formed in at least one of the semiconductor pellet or the package. A semiconductor device characterized in that it is provided on one brazing surface.
う付け面の中央から周縁へ放射状に形成することを特徴
とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the groove is V-shaped or U-shaped and is formed radially from the center of the brazing surface to the periphery.
う付け面の対向辺間に一定間隔に平行に形成することを
特徴とする請求項1記載の半導体装置。3. The semiconductor device according to claim 1, wherein the grooves are V-shaped or U-shaped and are formed parallel to each other at regular intervals between opposing sides of the brazing surface.
にろう付けする半導体装置であって、前記半導体ペレッ
トまたは前記パッケージの一方のろう付け面の少なくと
も1つの対向辺間の中央に、その表面積がろう付け面積
より小さいプリフォームろう材を載置し、この状態でリ
フローすることによりろう付けを行うことを特徴とする
半導体装置のろう付け方法。4. A semiconductor device in which a heat dissipating surface of a semiconductor pellet is brazed to a package, wherein the surface area of the soldering surface of one of the semiconductor pellet or the package is located in the center between at least one opposing side of the soldering surface of the semiconductor pellet or the package. A method for brazing semiconductor devices, characterized in that brazing is performed by placing a preform brazing material smaller than the area and reflowing in this state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP990191A JPH04312932A (en) | 1991-01-30 | 1991-01-30 | Semiconductor device and brazing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP990191A JPH04312932A (en) | 1991-01-30 | 1991-01-30 | Semiconductor device and brazing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04312932A true JPH04312932A (en) | 1992-11-04 |
Family
ID=11733018
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP990191A Pending JPH04312932A (en) | 1991-01-30 | 1991-01-30 | Semiconductor device and brazing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04312932A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0710939U (en) * | 1993-07-28 | 1995-02-14 | サンケン電気株式会社 | Semiconductor device having circuit board |
JP2006120993A (en) * | 2004-10-25 | 2006-05-11 | Toppan Forms Co Ltd | Ic chip, and sheet with ic chip mounted thereon |
US7601625B2 (en) | 2004-04-20 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device having solder layer |
JP2010245227A (en) * | 2009-04-03 | 2010-10-28 | Nissan Motor Co Ltd | Semiconductor device and method of manufacturing the same |
-
1991
- 1991-01-30 JP JP990191A patent/JPH04312932A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0710939U (en) * | 1993-07-28 | 1995-02-14 | サンケン電気株式会社 | Semiconductor device having circuit board |
US7601625B2 (en) | 2004-04-20 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device having solder layer |
JP2006120993A (en) * | 2004-10-25 | 2006-05-11 | Toppan Forms Co Ltd | Ic chip, and sheet with ic chip mounted thereon |
JP2010245227A (en) * | 2009-04-03 | 2010-10-28 | Nissan Motor Co Ltd | Semiconductor device and method of manufacturing the same |
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