JPH04307942A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electrode and an interconnection which are extended on the upper surface of a gate electrode and source region from being broken due to the step between the surface of the gate electrode and the surface of the source region by reducing the step and making it the gently-sloping surface in a vertical MISFET which has the thick gate electrode, concerning the method for manufacturing the semiconductor device MISFET which has the surface having reduced unevenness or step. CONSTITUTION:On a one conductivity-type substrate (2), a polycrystalline silicon gate electrode (5) having an oxidation-resistant mask film (6) in the upper part is formed through a gate insulated film (4). With the gate electrode (5) used as a mask, impurities are selectively injected into the substrate (2) by ion implantation. Then, the substrate is heat-treated in an oxidizing atmosphere and the injected impurities are activated and redistributed to form an opposite conductivity-type impurity diffusion region (3). At the same time, on the side face of the gate electrode (5) which is not covered with the oxidation-resistant mask film (6) and on the impurity diffusion region (3), a silicon oxide film (7) is so formed as to reduce the step in the electrode formation surface which is constituted of the surface of the gate electrode (5) and the surface of the impurity diffusion region (3).

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device,
In particular, MIS type field effect transistor (hereinafter MISFET)
The present invention relates to a manufacturing method for reducing surface unevenness (referred to as "Difference in height").

In MIS type semiconductor devices, the aspect ratio of the uneven steps formed on the surface is increasing due to miniaturization and higher density of MISFETs as the degree of integration increases. On the other hand, due to the scale law associated with the miniaturization of devices, electrodes,
As the thickness (and width) of interconnections has also been reduced, disconnections in electrodes and interconnections at step portions with large aspect ratios have become apparent.Especially in vertical MISFETs, deep channel regions Because the gate electrode used as a mask during formation is formed thickly, the step formed between the gate electrode and the source region surface becomes large, and the tendency for the source electrode to be drawn out on the gate electrode to break off is reduced. This is particularly noticeable and improvements are desired.

0003

2. Description of the Related Art FIG. 4 is a schematic diagram of an example of a conventional vertical MISFET, in which (a) is a plan view, and (b) is a sectional view taken along the line A-A. In the figure, 50 is an n+ type silicon substrate, 51 is an n- type drain layer, 52 is a p+ type channel region, 53 is an n+ type source region, 54 is a gate oxide film, 55 is a gate electrode, 57 is an oxide film, and 58 is a An interlayer insulating film, 59 an aluminum (Al) source electrode, and 61 a contact hole.

Conventionally, such a vertical MISFET has been formed by the method described below with reference to the drawings. Refer to FIG. 5(a). In other words, after a gate oxide film 54 is formed on an n- type drain layer 51 formed on an n+-type silicon substrate 50 (not shown), a polycrystalline silicon layer is formed on this substrate. Then, patterning is performed to form a gate electrode 55 made of this polycrystalline silicon.

Referring to FIG. 5(b), boron ions are implanted using the gate 55 as a mask, and then heat treatment is performed to form a p+ type channel region 52 having a predetermined depth. At this time, an oxide film 57' is formed on the surfaces of the p+ type channel region 52 and the gate electrode 55.

Referring to FIG. 5C, a resist pattern 60 is then formed to selectively cover the contact hole formation region, and using this resist pattern 60 as a mask, the oxide film 57' outside the contact hole formation region is removed by etching.

FIG. 5(d) Refer to the above resist pattern 6
After the resist pattern is removed, heat treatment is performed to form an n+ type source region 53 that extends below the gate electrode 55 leaving a predetermined channel length (Lch). . At this time, an oxide film 57 is formed on the surfaces of the source region 53, the gate electrode 55, and the channel region 52, and the oxide film 57 on the contact hole formation region is covered with the oxide film 57' (not shown).
It is formed thicker by the amount of

Referring to FIG. 4(b), after forming an interlayer insulating film 58 on the substrate, a part of the n+ type source region 53 and p+ type channel region 52 is exposed in the contact hole forming region by ordinary photolithography. A contact hole 61 is formed to expose the n+ type source region 53 in the contact hole 61 on this substrate.
In this method, an Al source electrode 59 made of Al or an Al alloy is formed in contact with the p+ type channel region 52.

[0009]

[Problem to be solved by the invention] The above vertical MISFET
In the gate electrode 55, the p+ type channel region 5
In the ion implantation of boron during the formation of the source region 53, the penetration of boron into the active channel formation region (ch) and the penetration of phosphorus into the active channel formation region (ch) during the formation of the source region 53.
) Active channel formation region (ch) by penetrating into
In order to avoid fluctuations in impurity concentration, the thickness is formed to be approximately 5000 Å.

Therefore, according to the above conventional manufacturing method,
There is a high step (h
) is formed, and the Al source electrode 59 formed extending from the contact hole 61 portion onto the interlayer insulating film 58 becomes extremely thin as shown at 59' on the stepped portion. Therefore, the element is miniaturized, and the thickness of the source electrode 59 is 5000~
When formed as thin as about 6000 Å, the source electrode 59 is formed at the extremely thin portion 59' due to electromigration or stress migration during operation.
A so-called "stage break" phenomenon occurs in which the wire breaks.

Therefore, the present invention reduces the step formed between the upper part of the gate electrode, which is formed thickly, and the upper part of the source region, and makes the slope more gentle, thereby reducing the step discontinuity of the metal electrode extending above the step. It is an object of the present invention to prevent the above problems and improve the reliability of a MIS type semiconductor device including a vertical MISFET.

0012

[Means for Solving the Problems] The above object is to provide a method for manufacturing an MIS type semiconductor device, which includes one conductivity type semiconductor substrate (one
) A polycrystalline silicon gate electrode (
5) step of forming an impurity, selectively ion-implanting an opposite conductivity type impurity into the semiconductor substrate (1) using the gate electrode (5) as a mask, and performing heat treatment in an oxidizing atmosphere to complete the implantation. While activating and redistributing impurities to form an opposite conductivity type impurity diffusion region (2) in the semiconductor substrate (1), the side surface of the gate electrode (5) that is not covered by the oxidation-resistant mask film (6) and the impurity diffusion region (
2) Above, a silicon oxide film (
7) The problem is solved by the method for manufacturing a semiconductor device according to the present invention, which includes the step of forming.

[0013]

[Operation] FIG. 1 is a schematic process sectional view for explaining the principle of the method of the present invention. That is, the method of the present invention, as shown in FIG.
) A polycrystalline silicon gate electrode (5) having an oxidation-resistant mask film such as a silicon nitride film (6) on top is formed via a gate insulating film (4), and then this gate electrode (5) is used as a mask. p-type semiconductor substrate (1)
Ion implantation (II) of an impurity of the opposite conductivity type, such as phosphorus (P+), is carried out into the source region.
+) After forming the implanted region (103), high-temperature heat treatment is performed in an oxidizing atmosphere to activate and redistribute the implanted impurities.
As shown in FIG. 2, the activation and redistribution of phosphorus (P+) forms an opposite conductivity type impurity diffusion region, for example, an n+ type source region (3), and at the same time, the silicon nitride film (
6) Perform selective oxidation of the silicon exposed surface using the oxidation-resistant mask to remove the n+ impurity diffusion region of the opposite conductivity type.
A thick silicon oxide film (7) having a predetermined thickness is selectively formed on the upper surface of the type source region (3) and the side surface of the polycrystalline silicon gate electrode (5).

[0014] By doing this, the figure (c)
As shown in FIG. 2, the interlayer insulating film 8 formed on the main surface on which the silicon oxide film (7) is formed is formed on the semiconductor substrate, that is, on the source region (3), on the upper surface A1, and on the gate electrode (5).
The level difference (hS) with the upper surface A2 is reduced to a low level by the thick silicon oxide film (7A) formed on the source region (3), and the level difference (S) is formed on the side surface of the gate electrode (5). The silicon oxide film (7B) gradually thickens at the bottom to form a gentle slope.

Therefore, as shown in FIG. 2D, for example, an electrode or wiring formed extending from the source region (3) through the contact hole (10) onto the stepped portion of the interlayer insulating film (8). For example, the Al source electrode (9) is no longer formed extremely thin on the stepped portion (S), and breakage of the electrode or wiring due to electromigration or stress migration effects is prevented.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention for forming a vertical MOSFET will be specifically described below with reference to process cross-sectional views shown in FIGS. 2 and 3. Note that the same objects are indicated by the same reference numerals throughout the figures.

Refer to FIG. 2(a) When forming an n-channel vertical MOSFET using the method of the present invention, for example, 10
n+ having an impurity concentration of about 18 to 1020 cm-3
10-100 mm thick on a mold silicon substrate (not shown)
μm, n with an impurity concentration of about 1013 to 1015 cm-3
- Using a substrate to be processed on which a - type drain layer 11 is formed, first, a gate oxide film 14 with a thickness of about 500 Å is formed on the n- type drain layer 11 by thermal oxidation, and then a vapor phase film is formed on this substrate. A polycrystalline silicon layer with a thickness of about 5,000 Å is formed by growth, a silicon nitride film with a thickness of about 1,000 Å is formed on the polycrystalline silicon layer by vapor phase growth, and patterning is performed by ordinary photolithography to form the gate. A polycrystalline silicon gate electrode 15 with a thickness of about 5000 Å is formed on the oxide film 14, and has a silicon nitride film 16 with a thickness of about 1000 Å on top, which serves as an oxidation-resistant mask film.

Referring to FIG. 2(b), boron (B+) is ion-implanted into the n- type drain layer 11 at a predetermined dose using the gate electrode 15 as a mask.
℃ for about 60 minutes and 1000℃ in an oxidizing atmosphere for 10 minutes.
Heat treatment for activation and redistribution is performed for about 10 minutes, and the impurity concentration is 1017 to 1018c in the n- type drain layer 11.
P+ of a predetermined depth having a depth of about 3 μm at about m−3
A mold channel region 12 is formed. At this time, a first silicon oxide (SiO2) film 17' having a thickness of about 1000 Å or less is formed on the p+ type channel region 12 not covered by the silicon nitride film 16 and on the side surfaces of the gate electrode 15.

Referring to FIG. 2(c), a first SiO2 layer is then formed on the p+ type channel region 12.
After forming a resist pattern 20 covering the contact hole formation region through the film 17' and selectively etching the first SiO2 film 17' that is not covered by the resist pattern 20, this resist pattern 20 and the gate electrode 15 are then etched. Using a mask, phosphorus (P+) is ion-implanted into the p+ type channel region 12 at a predetermined dose. 11
3 indicates the p+ implanted region.

Referring to FIG. 2(d), after removing the resist pattern 20, a heat treatment is performed at 1000° C. for about 60 minutes in an oxidizing atmosphere such as humidified oxygen to activate and reactivate the p+ implanted region 113. A channel forming region (ch) having a channel length (Lch) of, for example, about 1 μm is left at the end of the p+ type channel region 12, and an n+ type source region having a predetermined width is formed under the gate electrode 15. form 13. Note that by performing this heat treatment in an oxidizing atmosphere, the silicon nitride film 1 serving as the oxidation-resistant mask is
The surface of the n+ type source region 13 and the side surface of the gate electrode 15 that are not covered by the oxide film 6 are selectively thermally oxidized, and a second SiO2 film with a thickness of about 2000 to 3000 Å is deposited on those parts.
A film 17 is formed. At this time, the second SiO2 film 17 on the contact hole formation region is
The thickness is increased by the presence of the film 17'.

After referring to FIG. 3, an interlayer insulating film 18 such as PSG with a thickness of about 3000 to 5000 Å is formed on the entire surface of the substrate by CVD as usual, and then the contact hole forming area is formed by normal photolithography. Then, a contact hole 21 is formed that penetrates the interlayer insulating film 18 and the second SiO2 film 17 and exposes a part of the p+ type channel region 12 and the n+ type source region 13, and then the contact hole 21 is formed on the entire surface of this substrate. An Al or Al alloy layer with a thickness of about 5000 Å is formed on the substrate, and then this Al or Al alloy layer is patterned by ordinary photolithography to form the Al or Al alloy layer.
Alternatively, the contact hole 21 is made of Al alloy.
An n-channel vertical MOSFET using the present invention is formed by forming an Al source electrode 19 that extends widely and is led out onto the interlayer insulating film 18 from above the p+ type channel region 12 and the n+ type source region 13 exposed inside. Complete.

As shown in the embodiments above, according to the method of the present invention, impurity diffusion regions, for example, the source region 1 are formed on the semiconductor substrate surface, for example, the source region 13 surface and the side surface of the gate electrode 15.
At the same time, the surface of the source region 13 and the gate electrode 1 are
5 is selectively oxidized to form a thick oxide film 17 on those parts.
By forming the gate electrode 15, the unevenness level difference on the upper surface of the substrate caused by the gate electrode 15 is reduced and moderated. Therefore, in a vertical MOSFET or the like in which the gate electrode is formed thickly, the metal electrode, for example, the Al electrode 19, which is widely formed on the gate electrode placement surface, will not become extremely thin at the stepped portion, and this will prevent electromigration that occurs during operation. Breaking of the Al electrode due to stress migration is prevented.

The present invention is of course applicable not only to vertical MOSFETs but also to ordinary horizontal MOSFETs, and is effective in preventing disconnection of wiring.

[0024]

[Effects of the Invention] As explained above, according to the present invention, MO
A semiconductor device having an SFET, especially a vertical MOSFET,
Since the unevenness level difference on the electrode/wiring forming surface is low and moderated, breakage of the electrode/wiring is prevented and reliability thereof is improved.

[Brief explanation of drawings]

[Figure 1] Schematic process cross-sectional diagram for explaining the principle of the present invention

[Figure 2
] Process cross-sectional diagram of one embodiment of the method of the present invention (Part 1)

[Figure 3] Process cross-sectional diagram of one embodiment of the method of the present invention (Part 2)

[Figure 4] Schematic diagram of conventional vertical MOSFET

[Figure 5]
Process cross-sectional diagram of conventional manufacturing method

[Explanation of symbols]

2 P-type silicon substrate 3 n+ type source region 4 Gate insulating film 5 Polycrystalline silicon gate electrode 6 Silicon nitride film 7 Silicon oxide film 8 Interlayer insulation film 9 Al source electrode 103 P+ injection area A1 Upper surface of source region A2 Upper surface of gate electrode S Step part h　s　　step

Claims (1)

[Claims] 1. A method for manufacturing an MIS type semiconductor device, comprising: forming a gate insulating film (1) on a semiconductor substrate (1) of one conductivity type;
4) Forming a polycrystalline silicon gate electrode (5) having an oxidation-resistant mask film (6) on top of the semiconductor substrate (1) using the gate electrode (5) as a mask.
A process of selectively ion-implanting impurities of opposite conductivity type into the semiconductor substrate (1) and heat treatment in an oxidizing atmosphere to activate and redistribute the implanted impurities to form an impurity diffusion region of opposite conductivity type within the semiconductor substrate (1). (2) At the same time, a layer is formed on the side surface of the gate electrode (5) that is not covered by the oxidation-resistant mask film (6) and on the impurity diffusion region (2). A method for manufacturing a semiconductor device, comprising the step of forming a silicon oxide film (7) that reduces the level difference between the surface of the impurity diffusion region (2) and the upper surface and makes the level difference part a gentle slope.