JPH04307796A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH04307796A
JPH04307796A JP7133891A JP7133891A JPH04307796A JP H04307796 A JPH04307796 A JP H04307796A JP 7133891 A JP7133891 A JP 7133891A JP 7133891 A JP7133891 A JP 7133891A JP H04307796 A JPH04307796 A JP H04307796A
Authority
JP
Japan
Prior art keywords
inner layer
pattern
patterns
holes
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7133891A
Other languages
Japanese (ja)
Other versions
JP2630097B2 (en
Inventor
Masatoshi Ito
雅敏 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7133891A priority Critical patent/JP2630097B2/en
Publication of JPH04307796A publication Critical patent/JPH04307796A/en
Application granted granted Critical
Publication of JP2630097B2 publication Critical patent/JP2630097B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent remaining of non-etchant part by providing through holes at four corners of an inner layer board, further providing copper foil patterns for printing pilots at the same positions as those of the holes on front and rear surfaces, and using a distance between the circumference of the hole and the outer periphery of the pattern as an index of aligning front and rear inner layer patterns on, the front and rear surfaces. CONSTITUTION:Through holes 5 are formed at four corners of an inner layer board 1 as printing pilots by drilling. Pilot patterns 6 or an inner layer pattern film in which a circuit pattern region 4 corresponding to the center of the board 1, a plurality of dot patterns 3 corresponding to peripheral edge regions 2 and the patterns 6 are arranged, are provided on the surface of the board 1 to match the holes 5. The film is so aligned that the holes 4 formed at the four corners fall within the inner circumference of the patterns 6 to align the front and rear surfaces. Thus, remaining of non-etchant part is eliminated to prevent a short-circuit between wirings.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、多層印刷配線板の製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing multilayer printed wiring boards.

【0002】0002

【従来の技術】従来の多層印刷配線板は、図2(a),
(b)に示すように、中央部に回路パターン領域4を設
けた内層基板1の回路パターン領域4を取囲む周縁領域
2に多層化成形後の板厚精度を向上し、積層ボイドの発
生を防いで、反りを低減するために銅箔のドットパター
ン3を配列して設けている。
[Prior Art] A conventional multilayer printed wiring board is shown in FIG.
As shown in (b), the peripheral region 2 surrounding the circuit pattern region 4 of the inner layer substrate 1 with the circuit pattern region 4 provided in the center improves the thickness accuracy after multilayer molding and prevents the occurrence of lamination voids. A dot pattern 3 of copper foil is arranged in order to prevent warpage and reduce warpage.

【0003】このような、内層基板1では、回路パター
ン領域4に回路を形成する時に、表裏の合わせ精度(ず
れ量)を確認する指標がないために、回路パターンの表
裏の合わせ精度が低下し、多層化成形後の全体のパター
ン位置精度を低下させるという問題点がある。そこで内
層基板1の周縁領域2に設ける一部のドットパターン3
のパターン中心に合わせて、あらかじめドリル加工によ
り、ドットパターン3よりも小さい貫通孔5を設ける事
が提案されている。この場合、貫通孔5に合わせてエッ
チングレジスト膜のドットパターン3を設ける際に貫通
孔5の円周とドットパターン3の円周の距離の大小によ
り内層基板の表裏の回路パターンの合わせ精度を制御す
る事ができる為、内層パターンの位置精度を向上させる
事ができる。
[0003] In such an inner layer substrate 1, when a circuit is formed in the circuit pattern area 4, there is no index to confirm the alignment accuracy (amount of deviation) between the front and back sides, so the alignment accuracy between the front and back sides of the circuit pattern decreases. However, there is a problem in that the overall pattern position accuracy after multilayer molding is reduced. Therefore, some dot patterns 3 provided in the peripheral area 2 of the inner layer substrate 1
It has been proposed that a through hole 5 smaller than the dot pattern 3 be provided in advance by drilling in accordance with the center of the pattern. In this case, when providing the dot pattern 3 of the etching resist film in alignment with the through hole 5, the alignment accuracy of the circuit patterns on the front and back sides of the inner layer substrate is controlled by the distance between the circumference of the through hole 5 and the circumference of the dot pattern 3. Therefore, the positional accuracy of the inner layer pattern can be improved.

【0004】0004

【発明が解決しようとする課題】しかしながら、上述し
た従来の多層印刷配線板では、ドットパターンが図2(
b)に示すように、内層基板1の表側のドットパターン
3aと裏側のドットパターン3bが交互に設けてあり、
内層基板1の表裏同一箇所にドットパターンが重なって
いない為、回路形成時にドットパターンのない部分のエ
ッチングレジスト膜が貫通孔を介して裏面より貫通穴の
大きさのパターンが露光され、貫通孔の周囲にかろうじ
て付着していたエッチングレジスト膜が次のエッチング
工程で剥れエッチングレジスト膜のチップとなって浮遊
し、不要な箇所に付着してエッチング残りを生じるとい
う欠点がある。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional multilayer printed wiring board, the dot pattern is as shown in FIG.
As shown in b), the dot patterns 3a on the front side of the inner layer substrate 1 and the dot patterns 3b on the back side are alternately provided,
Since the dot patterns do not overlap at the same location on the front and back sides of the inner layer substrate 1, when forming the circuit, the etching resist film in the area without the dot pattern is exposed from the back side through the through hole, and a pattern of the size of the through hole is exposed through the through hole. There is a drawback that the etching resist film that has barely adhered to the surrounding area peels off in the next etching process, becomes floating chips of the etching resist film, and adheres to unnecessary locations, resulting in etching residue.

【0005】[0005]

【課題を解決するための手段】本発明の多層印刷配線板
の製造方法は、内層基板に印刷用パイロットとして貫通
孔を形成する工程と、前記貫通孔の位置に対応して位置
整合用のパイロットパターンを有する内層パターンフィ
ルムの前記パイロットパターンを前記貫通孔に整合して
前記内層基板の表裏両面に形成する工程と、前記内層パ
ターンフィルムをマスクとして前記内層基板の導電層を
パターニングし、回路配線及び前記回路配線の周囲にド
ットパターンを形成する工程とを含んで構成される。
[Means for Solving the Problems] The method for manufacturing a multilayer printed wiring board of the present invention includes the steps of forming through holes as printing pilots in an inner layer substrate, and forming pilots for positional alignment corresponding to the positions of the through holes. A step of aligning the pilot pattern of the inner layer pattern film having a pattern with the through hole and forming it on both the front and back surfaces of the inner layer substrate, and patterning the conductive layer of the inner layer substrate using the inner layer pattern film as a mask, and patterning the conductive layer of the inner layer substrate to form circuit wiring and forming a dot pattern around the circuit wiring.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【0007】図1(a),(b)は本発明の一実施例を
説明するための内層基板の模式的平面図及びA部拡大図
である。
FIGS. 1(a) and 1(b) are a schematic plan view and an enlarged view of part A of an inner layer substrate for explaining one embodiment of the present invention.

【0008】まず、内層基板1の四隅に、ドリル加工に
より、印刷用パイロットとして貫通孔5を形成する。貫
通孔5は、直径1.5mmの真円を有している。次に、
内層基板1の中央部に対応する回路パターン領域4と、
周縁領域2に対応する複数個のドットパターン3及び印
刷用パイロットパターン6を配置した内層パターンフィ
ルム(図省略)のパイロットパターン6を貫通孔5に合
わせて内層基板1の表面に設ける。
First, through holes 5 are formed as printing pilots at the four corners of the inner layer substrate 1 by drilling. The through hole 5 has a perfect circle with a diameter of 1.5 mm. next,
a circuit pattern area 4 corresponding to the center of the inner layer substrate 1;
A pilot pattern 6 of an inner layer pattern film (not shown) in which a plurality of dot patterns 3 corresponding to the peripheral area 2 and a printing pilot pattern 6 are arranged is provided on the surface of the inner layer substrate 1 in alignment with the through hole 5.

【0009】ここで、ドットパターン3は直径2.4m
mのドットで2.54mmの対角距離に、且つ各内層基
板1の表裏に交互に配置されている。印刷用パイロット
パターン6は直径1.8mmの真円で、貫通孔5と対応
する位置の内層基板1の表裏に夫々配置されている。
[0009] Here, dot pattern 3 has a diameter of 2.4 m.
m dots are arranged at a diagonal distance of 2.54 mm and alternately on the front and back sides of each inner layer substrate 1. The printing pilot patterns 6 are perfect circles with a diameter of 1.8 mm, and are arranged on the front and back sides of the inner layer substrate 1 at positions corresponding to the through holes 5, respectively.

【0010】ここで、四隅に設けた貫通孔5がパイロッ
トパターン6の円周内に収まるように内層パターンフィ
ルムの位置を合わせることにより150μm以内の精度
で内層パターンの表裏合わせを行なう事ができる。この
ように、内層パターンの表裏合わせを行ない、エッチン
グにより回路形成を行なった複数枚の内層基板1を複数
枚のプリプレグを介して重ね合わせ、積層プレスにより
、多層化成形して多層印刷配線板を構成する。
By aligning the inner layer pattern film so that the through holes 5 provided at the four corners are within the circumference of the pilot pattern 6, the front and back sides of the inner layer pattern can be aligned with an accuracy of within 150 μm. In this way, a plurality of inner layer substrates 1 on which the inner layer patterns are aligned, a circuit is formed by etching, and a plurality of inner layer substrates 1 are stacked together via a plurality of prepregs, and multilayer molding is performed using a lamination press to form a multilayer printed wiring board. Configure.

【0011】また、多層印刷配線板の内層基板1の周縁
領域2内の四隅に設ける貫通孔5を各隅毎に複数設けて
対応するパイロットパターン6を直径1.8mmと直径
1.6mmの2種類設けることにより、内層パターンの
表裏合わせ精度を50μm以内の精度で位置精度を向上
させる事ができる。
In addition, a plurality of through holes 5 are provided at each corner in the four corners of the peripheral area 2 of the inner layer substrate 1 of the multilayer printed wiring board, and two corresponding pilot patterns 6 are formed, one with a diameter of 1.8 mm and the other with a diameter of 1.6 mm. By providing different types, it is possible to improve the positional accuracy of the front and back alignment of the inner layer pattern to within 50 μm.

【0012】0012

【発明の効果】以上説明したように本発明は、内層基板
の四隅に貫通孔を設け、更にその貫通孔と同一位置の表
裏面に各々印刷用パイロット用の銅箔パターンを設け、
貫通孔の円周と銅箔パターンの外周との間の距離を内層
パターンの表裏合わせ精度の指標にする事により、内層
パターン位置精度が向上し、更に回路形成時のエッチン
グレジスト膜のチップ付着によるエッチング残りを阻止
して配線間短絡を防止できるという効果を有する。
As explained above, the present invention provides through holes at the four corners of the inner layer substrate, and further provides copper foil patterns for printing pilots on the front and back surfaces at the same position as the through holes, respectively.
By using the distance between the circumference of the through hole and the outer periphery of the copper foil pattern as an indicator of the accuracy of front-to-back alignment of the inner layer pattern, the inner layer pattern position accuracy is improved, and furthermore, the distance between the circumference of the through hole and the outer circumference of the copper foil pattern is improved. This has the effect of preventing etching residue and preventing short circuits between wirings.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例を説明するための内層基板の
模式的平面図及びA部拡大図である。
FIG. 1 is a schematic plan view and an enlarged view of part A of an inner layer substrate for explaining an embodiment of the present invention.

【図2】従来の多層印刷配線板の一例を説明するための
内層基板の模式的平面図及びB部拡大図である。
FIG. 2 is a schematic plan view and an enlarged view of part B of an inner layer substrate for explaining an example of a conventional multilayer printed wiring board.

【符号の説明】[Explanation of symbols]

1    内層基板 2    周縁領域 3,3a,3b    ドットパターン4    回路
パターン領域 5    貫通孔 6    パイロットパターン
1 Inner layer substrate 2 Peripheral area 3, 3a, 3b Dot pattern 4 Circuit pattern area 5 Through hole 6 Pilot pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  内層基板に印刷用パイロットとして貫
通孔を形成する工程と、前記貫通孔の位置に対応して位
置整合用のパイロットパターンを有する内層パターンフ
ィルムの前記パイロットパターンを前記貫通孔に整合し
て前記内層基板の表裏両面に形成する工程と、前記内層
パターンフィルムをマスクとして前記内層基板の導電層
をパターニングし、回路配線及び前記回路配線の周囲に
ドットパターンを形成する工程とを含むことを特徴とす
る多層印刷配線板の製造方法。
1. A step of forming a through hole as a printing pilot in an inner layer substrate, and aligning the pilot pattern of an inner layer pattern film having a pilot pattern for positional alignment corresponding to the position of the through hole with the through hole. and forming a conductive layer on the inner layer substrate using the inner layer pattern film as a mask to form a circuit wiring and a dot pattern around the circuit wiring. A method for manufacturing a multilayer printed wiring board characterized by:
JP7133891A 1991-04-04 1991-04-04 Method for manufacturing multilayer printed wiring board Expired - Fee Related JP2630097B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7133891A JP2630097B2 (en) 1991-04-04 1991-04-04 Method for manufacturing multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7133891A JP2630097B2 (en) 1991-04-04 1991-04-04 Method for manufacturing multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH04307796A true JPH04307796A (en) 1992-10-29
JP2630097B2 JP2630097B2 (en) 1997-07-16

Family

ID=13457621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7133891A Expired - Fee Related JP2630097B2 (en) 1991-04-04 1991-04-04 Method for manufacturing multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP2630097B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110650586B (en) * 2019-08-12 2021-09-14 珠海杰赛科技有限公司 Processing method of PCB

Also Published As

Publication number Publication date
JP2630097B2 (en) 1997-07-16

Similar Documents

Publication Publication Date Title
JP3230953B2 (en) Multilayer thin film wiring board
JPH0766552A (en) Manufacture of wiring board
JP2630097B2 (en) Method for manufacturing multilayer printed wiring board
KR20020050720A (en) Processes for manufacturing multilayer flexible wiring boards
JP2943767B2 (en) Method for manufacturing multilayer wiring board
JPH10200234A (en) Printed wiring board with fine pattern and manufacturing method thereof
JPH04346492A (en) Manufacture of hybrid integrated circuit board
JPH11307890A (en) Printed wiring board
JPH06334346A (en) Pattern forming method of thick film - thin film hybrid multilayered wiring board
JPH08222859A (en) Multilayered printed board
JP2010135461A (en) Method of manufacturing film carrier tape for electronic component mounting
JPH07336000A (en) Printed circuit board
JP2886697B2 (en) Method of manufacturing flexible circuit board
JPH0697634A (en) Printed wiring board for flip chip
JP3065008B2 (en) Printed wiring board and method of manufacturing the same
JPH11121930A (en) Manufacture of multilayered printed wiring board
GB2307352A (en) Manufacture of multi-layer printed circuit boards
JP2004079703A (en) Multilayer substrate and manufacturing method of same
JPH10163631A (en) Multi-layer printed circuit board and its manufacturing method
JP2005189462A (en) Method for manufacturing printed wiring board
JP3067168B2 (en) Manufacturing method of printed wiring board
JPS61264783A (en) Printed wiring board and manufacture thereof
JPH08167760A (en) Collective printed wiring board and its manufacture
JP2550781B2 (en) Method for manufacturing printed wiring board
JPH06333797A (en) Method of aligning mask in transfer step

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19970304

LAPS Cancellation because of no payment of annual fees