JPH04306885A - Semiconductor light emitting element - Google Patents

Semiconductor light emitting element

Info

Publication number
JPH04306885A
JPH04306885A JP3070727A JP7072791A JPH04306885A JP H04306885 A JPH04306885 A JP H04306885A JP 3070727 A JP3070727 A JP 3070727A JP 7072791 A JP7072791 A JP 7072791A JP H04306885 A JPH04306885 A JP H04306885A
Authority
JP
Japan
Prior art keywords
light emitting
electrode
layer
type sic
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3070727A
Other languages
Japanese (ja)
Inventor
Yukio Watanabe
幸雄 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3070727A priority Critical patent/JPH04306885A/en
Publication of JPH04306885A publication Critical patent/JPH04306885A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To enable a semiconductor light emitting element to be enhanced in outward light emission efficiency by a method wherein a barrier section is provided to a second electrode, a first electrode, and a part of a light emitting region to serve as a barrier to carriers injected into a light emitting region of a first carrier. CONSTITUTION:After a growth substrate is subjected to a surface treatment, SiN is deposited on a P-type SiC contact layer 13 and formed into a pattern. At this point, this SiN 17 is made to serve as a barrier layer. Furthermore, a P-side Al primary electrode 14 is formed in a radial manner starting from the center of the SiN layer 17 through a photoresist process. In succession, an N-side Ni electrode 15 is formed all the surface of an N-type SiC crystal substrate 11, which is thermally treated. The thermally treated body is separated into elements conforming to a forming pattern, the body concerned is mounted on a stem making the N-type SiC crystal substrate 11 confront the stem with a conductive adhesive agent as another resistive layer, and an Au bonding wire 16 is bonded to the patterned Al electrode on the SiN insulating section 17.

Description

【発明の詳細な説明】[Detailed description of the invention]

[発明の目的] [Purpose of the invention]

【0001】0001

【産業上の利用分野】本発明は、電極構造の適正化によ
り特性向上を図った半導体発光素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device whose characteristics are improved by optimizing its electrode structure.

【0002】0002

【従来の技術】従来の技術をSiC青色発光ダイオード
を例に説明する。SiC青色発光ダイオードは、6H型
もしくは4H型のSiC単結晶基板上に6H型の結晶を
成長させることにより作製される。続いて液相エピタキ
シャル成長によりn型のSiC結晶基板71上に、Al
とNをドープしたn型SiC発光層72を成長し、続い
てAlをドープしたp型SiCコンタクト層73を成長
する(図7(a))。
2. Description of the Related Art Conventional technology will be explained using a SiC blue light emitting diode as an example. A SiC blue light emitting diode is manufactured by growing a 6H type crystal on a 6H type or 4H type SiC single crystal substrate. Subsequently, Al was grown on the n-type SiC crystal substrate 71 by liquid phase epitaxial growth.
An n-type SiC light emitting layer 72 doped with N is grown, and subsequently a p-type SiC contact layer 73 doped with Al is grown (FIG. 7(a)).

【0003】次いで斯る成長基板をウエットエッチング
等で表面処理した後、1985年春季応用物理学会予稿
集、29a−W−1,P586に記載されているが如く
p型SiCコンタクト層73側にAl層とSi層が順次
積層されたP側電極74,n型SiC結晶基板71側に
n側Ni電極に75を形成する。若しくは、特開平2−
196421号公報に記載されているようにp型SiC
コンタクト層73側にTi層とAl層が順次積層された
P側電極、n型SiC結晶基板71側にn側Ni電極7
5を形成する(図7(b))。
Next, after surface-treating the growth substrate by wet etching or the like, Al is applied to the p-type SiC contact layer 73 side as described in 1985 Spring Proceedings of the Japan Society of Applied Physics, 29a-W-1, P586. A P-side electrode 74 and an n-side Ni electrode 75 are formed on the n-type SiC crystal substrate 71 side, in which a layer and a Si layer are sequentially laminated. Or, JP-A-2-
p-type SiC as described in Publication No. 196421
A P-side electrode in which a Ti layer and an Al layer are successively laminated on the contact layer 73 side, and an n-side Ni electrode 7 on the n-type SiC crystal substrate 71 side.
5 (FIG. 7(b)).

【0004】ついで光取り出し側のワイアボンディング
される部分及びステム側の導電性接着剤などをつける部
分を残しホトレジスト工程を用いてパターニング除去し
高温で熱処理する。その後パターニングに沿って200
〜300μm角の素子に分離し、ステムに導電性接着剤
を用いたマウント及びAu線76を用いてワイアボンデ
ィングを行う(図7(c))。この場合n型SiCは光
の吸収が少ないためn型SiC結晶基板71側を上にマ
ウントすることにより効率良く光を取り出すことができ
る。しかし、p型SiCコンタクト層73の厚みを十分
厚くしないとステム側につける導電性接着剤がp−n接
合まで這い上がり短絡故障を起こす。p型SiC層の厚
みを厚くするには結晶成長の時間を長くしなければなら
ず、生産性が悪くなる。また、p型SiCコンタクト層
73の厚みを厚くすると下の電極面から反射してくる分
の光の吸収が増え、外部発光効率が悪くなる。
[0004] Next, the pattern is removed using a photoresist process, leaving a part on the light extraction side to be wire bonded and a part on the stem side to which a conductive adhesive is applied, and then heat treated at a high temperature. Then 200 steps along the patterning
The elements are separated into ~300 μm square elements, and the stem is mounted using a conductive adhesive and wire bonded using an Au wire 76 (FIG. 7(c)). In this case, since n-type SiC absorbs less light, light can be extracted efficiently by mounting the n-type SiC crystal substrate 71 side upward. However, if the thickness of the p-type SiC contact layer 73 is not made sufficiently thick, the conductive adhesive applied to the stem side will creep up to the p-n junction, causing a short circuit failure. Increasing the thickness of the p-type SiC layer requires increasing the crystal growth time, resulting in poor productivity. Furthermore, if the thickness of the p-type SiC contact layer 73 is increased, the absorption of light reflected from the lower electrode surface will increase, and the external light emission efficiency will deteriorate.

【0005】このようなn型SiC結晶基板71側を上
にマウントする方法に代わって、p−n接合まで十分な
距離がとれるp型SiCコンタクト層73上にマウント
する方法が考えられる(図7(d)(e))。不純物濃
度を5×1018/cm3 程度まで低くし、1〜6μ
m程度に薄くすることによってp型SiCコンタクト層
73による光の吸収を少なくすることができる。しかし
、ここで新たな問題が生じた。p型SiCコンタクト層
73において、不純物濃度を10×18/cm3 程度
以下(抵抗率で0.05Ω・cm程度以上)に低くした
り、厚さを1〜6μm程度に薄くすると、電極74から
の電流の広がりが少なくなり、電極74直下及び電極周
辺部での発光が主となる。従って発光が電極74に遮ら
れるため、外部発光効率は向上しなかった。電極74の
うち特にワイアボンディング部は、ワイアボンディング
に必要十分な大きさを要求されるため、この部分による
外部発光効率低下は避けられなかった。
Instead of such a method of mounting the n-type SiC crystal substrate 71 side upward, a method of mounting it on the p-type SiC contact layer 73 that can provide a sufficient distance to the p-n junction can be considered (FIG. 7). (d)(e)). Reduce the impurity concentration to about 5 x 1018/cm3, and
By making it as thin as approximately m, absorption of light by the p-type SiC contact layer 73 can be reduced. However, a new problem arose. In the p-type SiC contact layer 73, if the impurity concentration is lowered to about 10×18/cm3 or less (resistivity is about 0.05 Ω·cm or more) or the thickness is reduced to about 1 to 6 μm, the The current spreads less, and the light is emitted mainly directly below the electrode 74 and around the electrode. Therefore, since the light emission was blocked by the electrode 74, the external light emission efficiency was not improved. Particularly, the wire bonding portion of the electrode 74 is required to have a size necessary and sufficient for wire bonding, so a decrease in external light emission efficiency due to this portion was unavoidable.

【0006】[0006]

【発明が解決しようとする課題】このように従来の半導
体発光素子は、不純物濃度が低く,層厚が薄いコンタク
ト層を光取出し面とする場合、電極直下及び電極周辺部
での発光が主となるため、発光が電極、特にワイアボン
ディング部より阻害され、外部発光効率が悪くなるとい
う問題があった。本発明は、この様な点を考慮したもの
で外部発光効率の高い半導体素子を提供することを目的
とする。 [発明の構成]
[Problems to be Solved by the Invention] As described above, in conventional semiconductor light emitting devices, when a contact layer with a low impurity concentration and a thin layer is used as a light extraction surface, light emission is mainly performed directly under the electrode and around the electrode. Therefore, there was a problem in that light emission was inhibited from the electrodes, especially the wire bonding portion, and the external light emission efficiency was deteriorated. The present invention takes these points into consideration and aims to provide a semiconductor element with high external light emission efficiency. [Structure of the invention]

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明は注入されたキャリアの再結合により光を発
する発光領域と、前記発光領域に前記光が取り出される
前記発光領域表面に直接若しくは低比抵抗層を介して形
成され、前記発光領域に第1のキャリアを注入する第1
の電極と、前記発光領域に直接若しくは他の低比抵抗層
を介して形成され、前記発光領域に第2のキャリアを注
入する第2の電極と、前記第1の電極と前記発光領域の
間の一部に形成され、前記第1のキャリアの前記発光領
域への注入の障壁となる障壁部とを備えたことを特徴と
する半導体発光素子を提供するものである。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a light-emitting region that emits light by recombination of injected carriers, and a light-emitting region that emits light directly to the surface of the light-emitting region from which the light is extracted. Alternatively, a first layer is formed through a low resistivity layer and injects first carriers into the light emitting region.
a second electrode formed directly in the light emitting region or via another low resistivity layer and injecting second carriers into the light emitting region; and between the first electrode and the light emitting region. The present invention provides a semiconductor light emitting device characterized in that it is provided with a barrier portion formed in a part of the semiconductor light emitting device and serving as a barrier to injection of the first carriers into the light emitting region.

【0008】ここで、発光領域とは正孔及び電子がそれ
ぞれ注入され、再結合する際に光を放出する領域で、正
孔は第1の電極から、電子は第2の電極から若しくは正
孔は第2の電極から電子は第1の電極から注入される。 このとき、第1の電極から注入される正孔または電子を
第1のキャリアとし、第2の電極から注入されるキャリ
アを第2のキャリアとする。
[0008] Here, the light-emitting region is a region where holes and electrons are injected and emit light when recombined. electrons are injected from the first electrode. At this time, holes or electrons injected from the first electrode are used as first carriers, and carriers injected from the second electrode are used as second carriers.

【0009】[0009]

【作用】本発明によれば、第1の電極と発光領域の間に
障壁部を形成することにより、この部分には電流が流れ
なくなり、第1の電極下での発光がなくなる。そのため
、従来そこに流れていた電流を他の領域に振り分けるこ
とができ外部発光効率が向上する。また、主電極ができ
るだけ発光を阻害することなく発光領域への供電ができ
る。
According to the present invention, by forming a barrier portion between the first electrode and the light emitting region, no current flows through this portion, and no light is emitted under the first electrode. Therefore, the current that conventionally flowed there can be distributed to other areas, improving external light emission efficiency. Further, the main electrode can supply power to the light emitting region without inhibiting light emission as much as possible.

【0010】0010

【実施例】以下、本発明の詳細を図示の実施例によって
説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to illustrated embodiments.

【0011】図1に本発明の第1の実施例に係わる半導
体発光素子製造工程を示す斜視図を示す。液相エピタキ
シャル成長によりn型のSiC結晶基板11上に発光領
域としてAlとNをドープしたn型SiC発光層12を
約40μm成長し、続いて低比抵抗相としてAlをドー
プしたp型コンタクト層13を約6μm成長する(図1
(a))。
FIG. 1 is a perspective view showing the manufacturing process of a semiconductor light emitting device according to a first embodiment of the present invention. An n-type SiC light-emitting layer 12 doped with Al and N as a light-emitting region is grown to a thickness of approximately 40 μm on an n-type SiC crystal substrate 11 by liquid phase epitaxial growth, followed by a p-type contact layer 13 doped with Al as a low resistivity phase. is grown to approximately 6 μm (Fig. 1
(a)).

【0012】次いで斯る成長基板を塩酸,硝酸、弗酸及
びこれらの混合物で表面処理した後、p型SiCコンタ
クト層13上にSiNを蒸着しホトレジスト工程を用い
て80μmΦのパターンを250μmピッチで形成する
。ここではこのSiN17を障壁層として用いた(図1
(b))。さらに、これにホトレジスト工程を用いて8
0μmΦのSiN層の中心から放射状に幅3μmのP側
Al主電極14を形成する(図1(c))。
Next, after surface-treating the growth substrate with hydrochloric acid, nitric acid, hydrofluoric acid, or a mixture thereof, SiN is deposited on the p-type SiC contact layer 13, and a pattern of 80 μmΦ is formed at a pitch of 250 μm using a photoresist process. do. Here, this SiN17 was used as a barrier layer (Fig. 1
(b)). Furthermore, using a photoresist process, 8
A P-side Al main electrode 14 having a width of 3 μm is formed radially from the center of the SiN layer having a diameter of 0 μm (FIG. 1(c)).

【0013】次いでn型SiC結晶基板11側にn側N
i電極15を全面に形成し1000℃の高温で熱処理す
る。これを形成パターンに従い250μm角の素子に分
離し、導電性接着剤を用いて他の低比抵抗層としてn型
SiC結晶基板11側をステムにマウントした後、80
μmΦのパターンに形成されたSiN絶縁部17上のA
l電極に25μmΦのAuボンディングワイア16でワ
イアボンディングを行う。そのときAu線の先端は約7
5μmΦとなる(図1(d))。こうして得られた半導
体発光素子の外部発光効率は約1%となった。
Next, on the n-type SiC crystal substrate 11 side, an n-side N
An i-electrode 15 is formed on the entire surface and heat-treated at a high temperature of 1000°C. This was separated into 250 μm square elements according to the formation pattern, and the n-type SiC crystal substrate 11 side was mounted on the stem as another low resistivity layer using a conductive adhesive.
A on the SiN insulating part 17 formed in a pattern of μmΦ
Wire bonding is performed to the l electrode using an Au bonding wire 16 with a diameter of 25 μm. At that time, the tip of the Au wire is approximately 7
It becomes 5 μmΦ (Fig. 1(d)). The external light emitting efficiency of the semiconductor light emitting device thus obtained was approximately 1%.

【0014】本実施例において、放射状に形成した主電
極の幅を3μmとしたが、外部発光効率はコンタクト層
厚に対する主電極幅(主電極幅比)に依存する。図2(
a)に本実施例における特性図を示す。電極部を除く光
取出し面の面積に対する主電極の占める面積比(主電極
面積比)は1/2となっている。主電極幅比は1/2を
越えると外部発光効率は低下しており、1/6〜1/2
程度で良好な値が得られる。一方、主電極面積比にも外
部発光効率は依存しており、主電極幅比を1/2とした
ときの特性を図2(b)に示す。図に示したように、主
電極面積比が1/20〜1/2で良好な外部発光効率が
得られる。
In this embodiment, the width of the main electrode formed radially is 3 μm, but the external light emission efficiency depends on the main electrode width (main electrode width ratio) to the contact layer thickness. Figure 2 (
A) shows a characteristic diagram in this example. The area ratio (main electrode area ratio) occupied by the main electrode to the area of the light extraction surface excluding the electrode portion is 1/2. When the main electrode width ratio exceeds 1/2, the external luminous efficiency decreases, and it ranges from 1/6 to 1/2.
A good value can be obtained at a certain level. On the other hand, the external luminous efficiency also depends on the main electrode area ratio, and the characteristics when the main electrode width ratio is set to 1/2 are shown in FIG. 2(b). As shown in the figure, good external light emission efficiency can be obtained when the main electrode area ratio is 1/20 to 1/2.

【0015】また障壁部は、大きさが電極のワイアボン
ディング部と同程度以上であることが望ましいが、その
外周よりコンタクト層厚の1/2までは小さくても良好
な外部発光効率が得られる。さらに小さくても効果はあ
るが、電極のワイアボンディング部の面積の2/3以上
であるのが望ましい。さらにまた、障壁層の真上だけで
なく、一部を覆う様に障壁層の中心からずれた位置に第
1の電極を形成しても良い。また材料は、SiO2 ,
Al2 O3,ZrO2 といった他の絶縁材料も用い
ることができる。
[0015]Although it is desirable that the size of the barrier part is at least the same size as the wire bonding part of the electrode, good external luminous efficiency can be obtained even if the barrier part is smaller than the outer periphery by up to 1/2 of the contact layer thickness. . Although it is effective even if it is even smaller, it is desirable that the area is 2/3 or more of the area of the wire bonding part of the electrode. Furthermore, the first electrode may be formed not only directly above the barrier layer but also at a position shifted from the center of the barrier layer so as to cover a part of the barrier layer. The materials are SiO2,
Other insulating materials such as Al2O3, ZrO2 can also be used.

【0016】ここで発光領域は、キャリアの再結合によ
り光を発することが可能な構造で、PN接合構造の他、
半導体と金属のショットキー接合構造や、半導体,絶縁
体金属の接合のMiS構造によっても形成できる。また
、低比抵抗層とは、導電型を程する半導体や、金属等と
いった非絶縁物から成る層である。
[0016] Here, the light emitting region has a structure capable of emitting light by recombination of carriers, and includes a PN junction structure,
It can also be formed by a Schottky junction structure of a semiconductor and a metal, or a MiS structure of a junction of a semiconductor and an insulating metal. Furthermore, the low resistivity layer is a layer made of a non-insulating material such as a semiconductor or metal having different conductivity types.

【0017】図3に本発明の第2実施例に係わる半導体
発光素子の斜視図を示す。本実施例も第1の実施例と同
様に作成されているが、障壁部18に非オーミック金属
であるNiを用いる。本実施例においても、第1実施例
と同様な効果が得られた。さらに、非オーミック性金属
上に、Al電極を形成するため半導体絶縁体上に形成す
るときと異なり、Alがボールアップをおこさないとい
った効果も得られた。障壁部の材料は、P−SiCに対
して非オーミックであるAu、W、Mo、Ptといった
他の非オーミック金属も用いることができる。
FIG. 3 shows a perspective view of a semiconductor light emitting device according to a second embodiment of the present invention. This embodiment is also manufactured in the same manner as the first embodiment, but the barrier portion 18 is made of Ni, which is a non-ohmic metal. In this example as well, the same effects as in the first example were obtained. Furthermore, unlike when forming an Al electrode on a semiconductor insulator to form an Al electrode on a non-ohmic metal, the effect that Al does not cause ball-up was also obtained. As the material of the barrier part, other non-ohmic metals such as Au, W, Mo, and Pt, which are non-ohmic to P-SiC, can also be used.

【0018】図4に本発明の第3実施例に係わる半導体
発光素子の斜視図を示す。本実施例も第1及び第2実施
例と同様に作成されているが、障壁部にはSiN17上
にNi18が形成され、障壁部は2層で構成されている
。本実施例においても第2の実施例と同様な効果が得ら
れた。
FIG. 4 shows a perspective view of a semiconductor light emitting device according to a third embodiment of the present invention. This example is also produced in the same manner as the first and second examples, but the barrier part is formed of Ni 18 on SiN 17, and the barrier part is composed of two layers. In this example as well, the same effects as in the second example were obtained.

【0019】障壁部は、他にもSiO2 ,Al2 O
3,ZrO2 ,といった他の絶縁材料のうち少なくと
もいずれかと、Au、W、Mo、Ptといった他の非オ
ーミック電極のうち少なくともいずれかとの組合せを用
いることができる。このとき積層膜でもそうでなくても
よい。
[0019] The barrier part is also made of SiO2, Al2O
Combinations of at least one of other insulating materials, such as No. 3, ZrO2, and other non-ohmic electrodes, such as Au, W, Mo, and Pt, can be used. At this time, it may be a laminated film or not.

【0020】図5に、本発明の第4実施例に係わる半導
体発光素子の斜視図を示す。本実施例も第1及至第3実
施例と同様に作成されているが主電極の形状が異ってい
る。すなわち本実施例において主電極は格子状に形成さ
れている。ここで、第1及至第3実施例と同様に主電極
幅比、主電極面積比が設定されているので、第1及至第
3実施例と同様の効果が得られた。主電極の形状は、本
実施例の以外にも主電極幅比、主電極面積比が第1実施
例中に記した範囲内であればよい。
FIG. 5 shows a perspective view of a semiconductor light emitting device according to a fourth embodiment of the present invention. This example is also manufactured in the same manner as the first to third examples, but the shape of the main electrode is different. That is, in this embodiment, the main electrode is formed in a grid shape. Here, since the main electrode width ratio and main electrode area ratio were set as in the first to third embodiments, the same effects as in the first to third embodiments were obtained. The shape of the main electrode may be other than that of this embodiment as long as the main electrode width ratio and main electrode area ratio are within the ranges described in the first embodiment.

【0021】図6に、本発明の第5実施例に係わる半導
体発光素子の斜視図である。本実施例が第1及至第4実
施例と異る点は発光層にIn0.5 (Ga1 −xA
lx)    (0≦x≦1)を用いている点である。
FIG. 6 is a perspective view of a semiconductor light emitting device according to a fifth embodiment of the present invention. This example differs from the first to fourth examples in that the light-emitting layer has In0.5 (Ga1 -xA
lx) (0≦x≦1).

【0022】n型GaAs基板21に、n型InGaA
lPクラッド層22,InGaAlP活性層23,P型
InGaAlPクラッド層24,P型GaAlAsコン
タクト層25が順次形成されている。これにに第1及至
第4実施例と同様にしてAu−Ge障壁部19及び電極
を形成した素子において、1.5%という高い発光効率
が得られた。
[0022] On the n-type GaAs substrate 21, an n-type InGaA
An IP cladding layer 22, an InGaAlP active layer 23, a P-type InGaAlP cladding layer 24, and a P-type GaAlAs contact layer 25 are formed in this order. In the device in which the Au-Ge barrier portion 19 and electrodes were formed in the same manner as in the first to fourth examples, a high luminous efficiency of 1.5% was obtained.

【0023】尚、本実施例において、In0.5 (G
a1 −xAlx)0.5 P(0≦x≦1)を用いた
が、Ga1 −xAlxAs(0≦x≦1)GaPとい
った他の半導体発光材料を用いたときにも有効である。 さらに、n型基板を用いたがP型基板でもよく、このと
きは障壁部となる非オーミック金属はAu−ZnやCr
−Au等とすればよい。また、障壁部はコンタクト層と
異る導電性,若しくは高抵抗,例えばアンドープ或いは
I型の半導体でも可能である。また、障壁部コンタクト
層とショットキー接合する材料でも良い。その他、本発
明の要旨を逸脱しない範囲で種々変更して実施すること
ができる。
[0023] In this example, In0.5 (G
Although a1-xAlx)0.5P (0≦x≦1) was used, it is also effective to use other semiconductor light-emitting materials such as Ga1-xAlxAs (0≦x≦1)GaP. Furthermore, although an n-type substrate is used, a p-type substrate may also be used.
-Au etc. may be used. Further, the barrier portion may be made of a semiconductor having a conductivity different from that of the contact layer or having a high resistance, for example, an undoped or I-type semiconductor. Alternatively, a material that forms a Schottky junction with the barrier contact layer may be used. In addition, various modifications can be made without departing from the gist of the present invention.

【0024】[0024]

【発明の効果】以上詳述したように、半導体発光素子の
外部に取り出される発光に、寄与しない電流を少なくす
ることにより、外部発光効率が向上する。
As described in detail above, by reducing the amount of current that does not contribute to the light emitted externally from the semiconductor light emitting device, the external light emitting efficiency is improved.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】  本発明の第1実施例に係わる半導体発光素
子の製造工程を示す斜視図。
FIG. 1 is a perspective view showing the manufacturing process of a semiconductor light emitting device according to a first embodiment of the present invention.

【図2】  本発明の第1実施例を説明するための特性
図。
FIG. 2 is a characteristic diagram for explaining the first embodiment of the present invention.

【図3】  本発明の第2実施例に係わる半導体発光素
子を示す斜視図。
FIG. 3 is a perspective view showing a semiconductor light emitting device according to a second embodiment of the present invention.

【図4】  本発明の第3実施例に係わる半導体発光素
子を示す斜視図。
FIG. 4 is a perspective view showing a semiconductor light emitting device according to a third embodiment of the present invention.

【図5】  本発明の第4実施例に係わる半導体発光素
子を示す斜視図。
FIG. 5 is a perspective view showing a semiconductor light emitting device according to a fourth embodiment of the present invention.

【図6】  本発明の第5実施例に係わる半導体発光素
子を示す斜視図。
FIG. 6 is a perspective view showing a semiconductor light emitting device according to a fifth embodiment of the present invention.

【図7】  従来の発光素子を示す斜視図。FIG. 7 is a perspective view showing a conventional light emitting element.

【符号の説明】[Explanation of symbols]

11,71…n型SiC結晶基板 12,72…n型SiC発光層 13,73…P型SiCコンタクト層 14,74…P側Al主電極 15…n側Ni電極 16…ボンディングワイア 17…SiN障壁部 18…Ni障壁部 19…Au−Ge障壁部 20,75…n側電極 21…n型GaAs基板 22…n型InGaAlPクラッド層 23…InGaAlP活性層 24…P型InGoAlPクラット層 25…P型GaAlAsコンタクト層 76…P側電極 11, 71...n-type SiC crystal substrate 12,72...n-type SiC light emitting layer 13,73...P-type SiC contact layer 14, 74...P side Al main electrode 15...n-side Ni electrode 16...Bonding wire 17...SiN barrier part 18...Ni barrier part 19...Au-Ge barrier part 20, 75...n side electrode 21...n-type GaAs substrate 22...n-type InGaAlP cladding layer 23...InGaAlP active layer 24...P-type InGoAlP crat layer 25...P-type GaAlAs contact layer 76...P side electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】注入されたキャリアの再結合により光を発
する発光領域と、前記光が取り出される前記発光領域表
面に直接若しくは低比抵抗層を介して形成され、前記発
光領域に第1のキャリアを注入する第1の電極と、前記
発光領域に直接若しくは他の低比抵抗層を介して形成さ
れ、前記発光領域に第2のキャリアを注入する第2の電
極と、前記第1の電極と前記発光領域の間の一部に形成
され、前記第1のキャリアの前記発光領域への注入の障
壁となる障壁部とを備えたことを特徴とする半導体発光
素子。
1. A light emitting region that emits light by recombination of injected carriers; and a first carrier formed on the surface of the light emitting region from which the light is extracted either directly or through a low resistivity layer; a first electrode for injecting second carriers into the light emitting region; a second electrode formed directly in the light emitting region or via another low resistivity layer and injecting second carriers into the light emitting region; A semiconductor light emitting device comprising: a barrier portion formed between the light emitting regions and serving as a barrier to injection of the first carriers into the light emitting regions.
【請求項2】前記低比抵抗層は少なくとも前記第1の電
極と接触する近傍が不純物濃度5×10−18 cm−
3以下で厚さ6μm以下のコンタクト層であることを特
徴とする請求項1記載の半導体発光素子。
2. The low resistivity layer has an impurity concentration of 5×10 −18 cm − at least in the vicinity of contact with the first electrode.
2. The semiconductor light emitting device according to claim 1, wherein the contact layer has a thickness of 3 μm or less and a thickness of 6 μm or less.
【請求項3】前記第1の電極は、前記発光領域表面に直
接若しくは前記低比抵抗層を介して接触する面積が、光
の取り出しが可能な領域の面積の1/2以下で、幅が、
前記コンタクト層の厚さの1/2以下であることを特徴
とする請求項2記載の半導体発光素子。
3. The first electrode has a width such that an area in contact with the surface of the light emitting region directly or through the low resistivity layer is 1/2 or less of an area of a region from which light can be extracted. ,
3. The semiconductor light emitting device according to claim 2, wherein the thickness is 1/2 or less of the thickness of the contact layer.
JP3070727A 1991-04-03 1991-04-03 Semiconductor light emitting element Pending JPH04306885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3070727A JPH04306885A (en) 1991-04-03 1991-04-03 Semiconductor light emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3070727A JPH04306885A (en) 1991-04-03 1991-04-03 Semiconductor light emitting element

Publications (1)

Publication Number Publication Date
JPH04306885A true JPH04306885A (en) 1992-10-29

Family

ID=13439864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3070727A Pending JPH04306885A (en) 1991-04-03 1991-04-03 Semiconductor light emitting element

Country Status (1)

Country Link
JP (1) JPH04306885A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8921887B2 (en) 2011-03-03 2014-12-30 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8921887B2 (en) 2011-03-03 2014-12-30 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing the same
US9331248B2 (en) 2011-03-03 2016-05-03 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing the same

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