JPH04305925A - Polishing method of semiconductor wafer - Google Patents
Polishing method of semiconductor waferInfo
- Publication number
- JPH04305925A JPH04305925A JP3096404A JP9640491A JPH04305925A JP H04305925 A JPH04305925 A JP H04305925A JP 3096404 A JP3096404 A JP 3096404A JP 9640491 A JP9640491 A JP 9640491A JP H04305925 A JPH04305925 A JP H04305925A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- polishing
- epitaxial growth
- wax
- growth surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000005498 polishing Methods 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000007517 polishing process Methods 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 57
- 238000010438 heat treatment Methods 0.000 description 8
- 239000003082 abrasive agent Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 150000004996 alkyl benzenes Chemical class 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Landscapes
- Grinding Of Cylindrical And Plane Surfaces (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、受発光素子等に用いる
半導体ウエハの研磨方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing semiconductor wafers used for light emitting and receiving elements, etc.
【0002】0002
【従来技術】通信用の発光ダイオード(LED)素子、
あるいは半導体レーザ(LD)素子等は、光ファイバ、
あるいは光学素子等と光学的な精度をもって直接接続さ
れる。このため、このような素子を構成する半導体ウエ
ハは研磨加工され、その厚さは光学的精度にまで調整さ
れる。この研磨加工は、エピタキシャル成長法で半導体
層が形成されている面(以下、エピタキシャル成長面と
いう)の反対側の面(以下、非エピタキシャル成長面と
いう)に対してなされる。[Prior art] Light emitting diode (LED) element for communication,
Alternatively, a semiconductor laser (LD) element etc. can be an optical fiber,
Alternatively, it is directly connected to an optical element or the like with optical precision. For this reason, the semiconductor wafer constituting such an element is polished and its thickness is adjusted to optical precision. This polishing process is performed on the surface (hereinafter referred to as the non-epitaxial growth surface) opposite to the surface on which the semiconductor layer is formed by epitaxial growth (hereinafter referred to as the epitaxial growth surface).
【0003】図5に従来から提案されている半導体ウエ
ハの研磨装置15を示す。FIG. 5 shows a semiconductor wafer polishing apparatus 15 that has been conventionally proposed.
【0004】研磨装置15は半導体ウエハ17を押さえ
つけるためのガイド16、半導体ウエハ17に掛ける荷
重18、半導体ウエハ17を研磨するための研磨定板1
9で構成されている。The polishing device 15 includes a guide 16 for pressing down the semiconductor wafer 17, a load 18 to be applied to the semiconductor wafer 17, and a polishing plate 1 for polishing the semiconductor wafer 17.
It consists of 9.
【0005】この研磨装置15による研磨方法は、半導
体ウエハ17を研磨定板19に載置し、半導体ウエハ1
7のエピタキシャル成長面20に荷重18を載せたガイ
ド16を配置し、ガイド16で半導体ウエハ17に押圧
力をかけると共に、研磨材22でその表面が満たされた
研磨定板19を回転させて半導体ウエハ17の非エピタ
キシャル成長面21を研磨する。In the polishing method using this polishing device 15, a semiconductor wafer 17 is placed on a polishing plate 19, and the semiconductor wafer 17 is placed on a polishing plate 19.
A guide 16 carrying a load 18 is placed on the epitaxial growth surface 20 of No. 7, and the guide 16 applies a pressing force to the semiconductor wafer 17, and the polishing plate 19 whose surface is filled with an abrasive material 22 is rotated to remove the semiconductor wafer. 17 non-epitaxial growth surfaces 21 are polished.
【0006】[0006]
【発明が解決しようとする課題】しかしながら前述した
研磨装置15による半導体ウエハ17の研磨方法におい
ては以下に示すような問題点があった。However, the method of polishing the semiconductor wafer 17 using the polishing apparatus 15 described above has the following problems.
【0007】即ち、液相エピタキシャル成長法等で半導
体層を形成すると、半導体ウエハ17のエピタキシャル
成長面20に、半導体結晶の成長斑ができることがある
。図6(イ) はこの成長斑がエピタキシャル成長面2
0の中央にできた例で、このようにエピタキシャル成長
面20の中央に突起23が生じていると、エピタキシャ
ル成長面20をガイド16で押さえつけた時に、荷重1
8の力が半導体ウエハ17全体に平均にかからず、突起
23を生じている箇所のみに力が集中してしまい、研磨
加工中に半導体ウエハ17が突起23の箇所を中心とし
て割れてしまうという問題が生じていた。That is, when a semiconductor layer is formed by a liquid phase epitaxial growth method or the like, growth spots of semiconductor crystals may be formed on the epitaxial growth surface 20 of the semiconductor wafer 17. Figure 6 (a) shows that this growth spot is the epitaxial growth surface 2.
In this example, when the protrusion 23 is formed at the center of the epitaxial growth surface 20, when the epitaxial growth surface 20 is pressed down by the guide 16, the load 1
The force of 8 is not applied evenly to the entire semiconductor wafer 17, but is concentrated only at the location where the protrusion 23 is formed, and the semiconductor wafer 17 is broken centering on the location of the protrusion 23 during the polishing process. A problem had arisen.
【0008】また、図6(ロ) に示すように、半導体
ウエハ17のエピタキシャル成長面20の端部に突起2
4が生じていると、ガイド16が半導体ウエハ17上に
平行に配置されず、このまま研磨を行うと非エピタキシ
ャル成長面21が研磨定板19に対して平行に研磨され
ず、結果として半導体ウエハ17の厚さを精度良く調整
することができなかった。また、これに伴って形成され
る素子自体の特性も劣化していた。Further, as shown in FIG. 6(b), a protrusion 2 is formed at the end of the epitaxial growth surface 20 of the semiconductor wafer 17.
4, the guide 16 will not be placed parallel to the semiconductor wafer 17, and if polishing continues as is, the non-epitaxial growth surface 21 will not be polished parallel to the polishing plate 19, and as a result, the semiconductor wafer 17 will be It was not possible to precisely adjust the thickness. Further, the characteristics of the formed element itself were also deteriorated accordingly.
【0009】また、上記2つの問題点を解決するために
半導体ウエハ17とガイド16との間にスペーサを介在
させて研磨する方法も提案されているが、この場合、介
在させるスペーサの厚さを精度良く調整しなければなら
なくなる一方、均一な厚さを有するスペーサを形成する
こと自体が非常に困難であり、またこれに伴って研磨工
程を煩雑にしてしまっていた。[0009] Furthermore, in order to solve the above two problems, a polishing method has been proposed in which a spacer is interposed between the semiconductor wafer 17 and the guide 16, but in this case, the thickness of the intervening spacer is While accurate adjustment is required, it is extremely difficult to form spacers having a uniform thickness, and this also complicates the polishing process.
【0010】0010
【発明の目的】本発明は前記問題点に鑑みなされたもの
でその目的とするところは、半導体ウエハの一部分に局
部的な力が掛かることによる半導体ウエハの割れが生じ
なく、さらに半導体ウエハの厚さを精度良く調整するこ
とのできる半導体ウエハの研磨方法を提供することにあ
る。OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and its objects are to prevent cracking of the semiconductor wafer from occurring due to local force being applied to a portion of the semiconductor wafer, and to reduce the thickness of the semiconductor wafer. An object of the present invention is to provide a method for polishing a semiconductor wafer, which allows the polishing of semiconductor wafers to be adjusted with high precision.
【0011】[0011]
【課題を解決するための手段】前記目的を達成するため
の本発明の構成は、研磨定板と半導体ウエハとを相対的
に移動させて前記半導体ウエハの一面を研磨する半導体
ウエハの研磨方法において、前記半導体ウエハの非研磨
面にワックスを配置し、該ワックスを介して前記半導体
ウエハに荷重を掛けることを特徴とする。Means for Solving the Problems The present invention provides a method for polishing a semiconductor wafer, in which one side of the semiconductor wafer is polished by relatively moving a polishing plate and a semiconductor wafer. , a wax is disposed on the non-polished surface of the semiconductor wafer, and a load is applied to the semiconductor wafer through the wax.
【0012】0012
【実施例】本発明の一実施例を図を参照して詳細に説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.
【0013】図1は本発明に用いる研磨装置1の正面図
で、この研磨装置1は研磨治具5と研磨定板6とで構成
されている。FIG. 1 is a front view of a polishing apparatus 1 used in the present invention, and this polishing apparatus 1 is composed of a polishing jig 5 and a polishing plate 6. As shown in FIG.
【0014】即ち、研磨治具5は半導体ウエハを研磨定
板6に平行に押さえ付けるためのガイド2、ガイド2を
研磨定板6に平行に配置するためのウエハ平行だし装置
3、半導体ウエハに掛ける荷重4で構成されている。
尚、研磨定板6は研磨治具5に対して相対的に移動しう
るように、例えば回転自在に取り付けられ、且つ研磨治
具5から自由に取り外しができるようにも構成されてい
る。That is, the polishing jig 5 includes a guide 2 for pressing the semiconductor wafer parallel to the polishing plate 6, a wafer paralleling device 3 for arranging the guide 2 parallel to the polishing plate 6, and a semiconductor wafer. It consists of 4 loads. The polishing plate 6 is attached rotatably, for example, so as to be movable relative to the polishing jig 5, and is also configured to be freely detachable from the polishing jig 5.
【0015】以下、図2〜図4を用いてこの研磨装置1
を用いた半導体ウエハの研磨方法を説明する。Hereinafter, this polishing apparatus 1 will be explained using FIGS. 2 to 4.
A method of polishing a semiconductor wafer using the polishing method will be explained.
【0016】先ず、図2、図3は半導体ウエハにワック
スを配置する工程を示し、GaAs、InP等から成る
半導体ウエハ7をアルミナ製の加熱定板8の上に置き、
半導体ウエハ7のエピタキシャル成長面9上にワックス
10を突起12(尚、本実施例のエピタキシャル成長面
9には意図的に突起12を設けている。)が覆いかぶさ
るように配置し、加熱定板8を介してワックス10をホ
ットプレート11の熱で軟化する。First, FIGS. 2 and 3 show the process of placing wax on a semiconductor wafer. A semiconductor wafer 7 made of GaAs, InP, etc. is placed on a heating plate 8 made of alumina.
The wax 10 is placed on the epitaxial growth surface 9 of the semiconductor wafer 7 so that the projections 12 (in this example, the epitaxial growth surface 9 is intentionally provided with the projections 12) are covered with the wax 10, and the heating plate 8 is placed on the surface of the semiconductor wafer 7. The wax 10 is softened by the heat of the hot plate 11.
【0017】具体的には、水平に配置した加熱定板8上
に半導体ウエハ7を載置し、例えば、軟化点が約76℃
、接着力が約27Kg/cm2 、および針入度が25
℃,100g,5sec=1、25℃,200g,5s
ec=10であるエレクトロワックス(一般名)を半導
体ウエハ7のエピタキシャル成長面9上に均一に塗布し
、しかる後、このワックス10を温度約110 ℃に設
定したホットプレート11で約30分間加熱し、軟化さ
せる。Specifically, the semiconductor wafer 7 is placed on a horizontally arranged heating plate 8, and the semiconductor wafer 7 is placed on a heating plate 8 having a softening point of about 76° C., for example.
, adhesive strength is about 27Kg/cm2, and penetration is 25
°C, 100g, 5sec = 1, 25 °C, 200g, 5s
Electrowax (common name) with ec = 10 is uniformly applied on the epitaxial growth surface 9 of the semiconductor wafer 7, and then this wax 10 is heated for about 30 minutes on a hot plate 11 set at a temperature of about 110°C. Soften.
【0018】次に、図3に示すように研磨治具5を加熱
定板8上に配置した後(この前にホットプレート11は
取り除いておくか、あるいはホットプレート11の加熱
電源をOFFにしておく。)、ガイド2をワックス10
を介してエピタキシャル成長面9上に載せ、所定の荷重
4を掛けながらワックス10を室温で約30〜60分間
冷却固化し、半導体ウエハ7をワックス10の接着力で
ガイド2に平行に固定する。尚、この時のガイド2はウ
エハ平行だし装置3によりエピタキシャル成長面9に対
して精度良く平行に配置され、また、荷重4の大きさは
エピタキシャル成長面9に対して0.25〜0.5g/
cm2 になるように設定しておく。Next, as shown in FIG. 3, after placing the polishing jig 5 on the heating plate 8 (before this, remove the hot plate 11 or turn off the heating power of the hot plate 11). ), guide 2 with wax 10
The semiconductor wafer 7 is placed on the epitaxial growth surface 9 via the wafer 1, and the wax 10 is cooled and solidified at room temperature for about 30 to 60 minutes while applying a predetermined load 4, and the semiconductor wafer 7 is fixed parallel to the guide 2 by the adhesive force of the wax 10. At this time, the guide 2 is placed parallel to the epitaxial growth surface 9 with high precision by the wafer parallelization device 3, and the magnitude of the load 4 is 0.25 to 0.5 g// to the epitaxial growth surface 9.
Set it so that it is cm2.
【0019】続いて、半導体ウエハ7をガイド2に固定
させた研磨治具5を、図4に示すように研磨材13でそ
の表面を満たした研磨定板6上に平行に配置し、エピタ
キシャル成長面9に対して大きさ0.5 〜10g /
cm2 の荷重4を掛けながら研磨定板6を回転させ半
導体ウエハ7の非エピタキシャル成長面14を研磨する
。Next, the polishing jig 5 with the semiconductor wafer 7 fixed to the guide 2 is placed parallel to the polishing plate 6 whose surface is filled with the abrasive material 13 as shown in FIG. Size 0.5 to 10g/9
The polishing plate 6 is rotated while applying a load 4 of cm2 to polish the non-epitaxial growth surface 14 of the semiconductor wafer 7.
【0020】非エピタキシャル成長面14の研磨が終了
した後、研磨治具5を加熱定板8に再度配置し、ホット
プレート11の熱でワックス10を溶解除去する。最後
に、エピタキシャル成長面9は、トリクレン、あるいは
アルキルベンゼン系の有機溶剤を用いて有機洗浄する。After polishing the non-epitaxial growth surface 14, the polishing jig 5 is placed again on the heating plate 8, and the wax 10 is melted and removed by the heat of the hot plate 11. Finally, the epitaxial growth surface 9 is organically cleaned using trichlene or an alkylbenzene-based organic solvent.
【0021】本実施例の研磨方法によれば、エピタキシ
ャル成長面9にエピタキシャル成長法等による半導体結
晶の成長斑が生じていても、その成長斑をワックス10
によって覆ってしまっているので、ガイド2を半導体ウ
エハ7上に常に平行に配置でき、これに伴って研磨時の
荷重をエピタキシャル成長面9全体に均等に掛けること
ができる。従って、半導体ウエハ7の一部分に局部的な
力が掛かることによる半導体ウエハ7の割れを生じなく
なり、非エピタキシャル成長面14を精度良く研磨する
ことができる。According to the polishing method of this embodiment, even if growth spots of semiconductor crystals are formed on the epitaxial growth surface 9 due to the epitaxial growth method, the growth spots can be removed by wax 10.
Since the guide 2 is covered by the semiconductor wafer 7, the guide 2 can always be placed parallel to the semiconductor wafer 7, and accordingly, the load during polishing can be evenly applied to the entire epitaxial growth surface 9. Therefore, cracking of the semiconductor wafer 7 due to local force applied to a portion of the semiconductor wafer 7 does not occur, and the non-epitaxial growth surface 14 can be polished with high precision.
【0022】[0022]
【発明の効果】本発明の研磨方法によれば、半導体ウエ
ハの荷重を掛ける面上にワックスを配置し、このワック
スを介して半導体ウエハに荷重を掛けているので、半導
体ウエハの一部分に局部的な力が掛かることによる半導
体ウエハの割れが生じなくなり、しかも半導体ウエハの
厚さを精度良く調整することができるようになる。[Effects of the Invention] According to the polishing method of the present invention, wax is placed on the surface of the semiconductor wafer on which the load is applied, and the load is applied to the semiconductor wafer through this wax, so that the polishing method is applied locally to a portion of the semiconductor wafer. This prevents the semiconductor wafer from cracking due to excessive force, and allows the thickness of the semiconductor wafer to be adjusted with high precision.
【図1】本発明の研磨装置の正面図。FIG. 1 is a front view of a polishing apparatus of the present invention.
【図2】本発明の研磨方法の一工程を説明する工程説明
図。FIG. 2 is a process explanatory diagram illustrating one step of the polishing method of the present invention.
【図3】本発明の研磨方法の一工程を説明する工程説明
図。FIG. 3 is a process explanatory diagram illustrating one step of the polishing method of the present invention.
【図4】本発明の研磨方法の一工程を説明する工程説明
図。FIG. 4 is a process explanatory diagram illustrating one step of the polishing method of the present invention.
【図5】従来の研磨装置の正面図。FIG. 5 is a front view of a conventional polishing device.
【図6】(イ),(ロ) は共に一般的な半導体ウエハ
のエピタキシャル成長面を示す正面図。FIGS. 6A and 6B are front views showing the epitaxial growth surface of a typical semiconductor wafer.
1 研磨装置 2 ガイド 3 ウエハ平行だし装置 4 荷重 5 研磨治具 6 研磨定板 7 半導体ウエハ 8 加熱定板 9 エピタキシャル成長面 10 ワックス 11 ホットプレート 12 突起 13 研磨材 14 非エピタキシャル成長面 1. Polishing equipment 2 Guide 3 Wafer parallelization device 4 Load 5 Polishing jig 6 Polishing plate 7 Semiconductor wafer 8 Heating plate 9 Epitaxial growth surface 10 Wax 11 Hot plate 12 Protrusion 13 Abrasive material 14 Non-epitaxial growth surface
Claims (2)
移動させて前記半導体ウエハの一面を研磨する半導体ウ
エハの研磨方法において、前記半導体ウエハの非研磨面
にワックスを配置し、該ワックスを介して前記半導体ウ
エハに荷重を掛けることを特徴とする半導体ウエハの研
磨方法。1. A method for polishing a semiconductor wafer in which one surface of the semiconductor wafer is polished by relatively moving a polishing plate and the semiconductor wafer, wherein wax is placed on the non-polished surface of the semiconductor wafer, and the wax is removed from the surface of the semiconductor wafer. A method for polishing a semiconductor wafer, the method comprising: applying a load to the semiconductor wafer through the semiconductor wafer.
いる突起が覆い被さるように配置したことを特徴とする
請求項1記載の半導体ウエハの研磨方法。2. The method of polishing a semiconductor wafer according to claim 1, wherein the wax is placed so as to cover projections formed on the non-polishing surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3096404A JPH04305925A (en) | 1991-04-02 | 1991-04-02 | Polishing method of semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3096404A JPH04305925A (en) | 1991-04-02 | 1991-04-02 | Polishing method of semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04305925A true JPH04305925A (en) | 1992-10-28 |
Family
ID=14164029
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3096404A Pending JPH04305925A (en) | 1991-04-02 | 1991-04-02 | Polishing method of semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04305925A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7459397B2 (en) | 2004-05-06 | 2008-12-02 | Opnext Japan, Inc. | Polishing method for semiconductor substrate, and polishing jig used therein |
-
1991
- 1991-04-02 JP JP3096404A patent/JPH04305925A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7459397B2 (en) | 2004-05-06 | 2008-12-02 | Opnext Japan, Inc. | Polishing method for semiconductor substrate, and polishing jig used therein |
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