JPH04304655A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a narrower groove type element isolating region than a minimum resolution size of a photoresist film and a method for manufacturing the same. CONSTITUTION:A groove 104a of a width (W+2alpha) is formed on a p-type silicon substrate 101, and a silicon epitaxial layer 105 having a thickness alpha is formed on the surface of the groove 104a thereby to obtain a groove 104b of a width W. Here, the (W+2alpha) is a value of a minimum resolution size or more of a photoresist film, and the W is a value smaller than the minimum resolution size of the film.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a trench-type fine isolation region in a semiconductor device and a method of manufacturing the same.

0002

2. Description of the Related Art The structure and manufacturing method of a conventional trench-type element isolation region will be described with reference to FIG. First, as shown in FIG. 4(a), for example, a p-type silicon substrate 40
A groove 404 having a width W' is formed on the surface of the substrate 1 by reactive ion etching using the photoresist film 403 as a mask. Next, as shown in FIG. 4(b), an insulating film 4 is formed on the entire surface.
06a is deposited, and the trench 404 is filled with this. The thickness of the insulating film 406a is W'/2 or more. Subsequently, as shown in FIG. 4(c), etching back is performed to form the groove 40.
An insulating film 406b with a flattened surface is left only inside the 4th layer. As a result, a groove-shaped element isolation region is formed.

0003

[Problem to be solved by the invention] The method described above is
This method cannot be used to form grooves narrower than the minimum resolution dimension of the photoresist film. At present, the minimum resolution dimension of a photoresist film in light exposure is about 0.5 μm. Therefore,
W' cannot be made narrower than 0.5 μm.

Furthermore, when a channel stopper is required, such as in a MOS type semiconductor device, it is difficult to form a uniform diffusion layer on the semiconductor surface of a trench with a width of about submicrons.

[0005]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
In a groove-shaped element isolation region of a predetermined width provided on the semiconductor surface, there is a gap between the insulating film filling the groove and the semiconductor substrate.
A semiconductor epitaxial layer having a predetermined thickness is interposed. Furthermore, in a semiconductor device that requires a channel stopper, the semiconductor epitaxial layer has the required conductivity type and serves as the channel stopper.

In the method for manufacturing a semiconductor device of the present invention, when forming a trench-type element isolation region with a width W on the surface of a semiconductor substrate, first a trench with a width W+2α is formed, and then a film thickness is formed on the surface of the trench with a width W+2α. Grow a semiconductor epitaxial layer of α. Furthermore, in a semiconductor device that requires a channel stopper, a semiconductor epitaxial layer is grown by doping with impurities of the required conductivity type.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a cross-sectional view of the process order for explaining this embodiment along the manufacturing method according to the first embodiment of the present invention.

First, as shown in FIG. 1A, an insulating film 102 is formed on a p-type silicon substrate 101, and the insulating film 102 and the p-type silicon substrate 101 are sequentially etched using a photoresist film 103 as a mask. , groove 10 with width W+2α
Form 4a. Here, W is the final groove width,
The width is narrower than the minimum resolution dimension of the photoresist film, that is, 0 μm<W≦0.5 μm. However, W+2α≧0
．． It is 5 μm.

Next, as shown in FIG. 1(b), after removing the photoresist film 103, epitaxial growth of silicon is performed. At this time, silicon epitaxial layer 105 grows only on the surface of groove 104a. By setting the film thickness of the silicon epitaxial layer 105 to α,
A groove 104b having a width W is formed. For example, the width W+2α of the groove 104a is set to 0, which is the minimum resolution dimension of the photoresist film.
．． 5 μm, and if the film thickness α of the silicon epitaxial layer 105 is 100 nm, the groove 104 with a width of 0.3 μm
b is formed. Subsequently, a BPSG film, for example, is deposited so as to completely fill the trench 104b, and if necessary, heat treatment is applied to form an insulating film 106a. The thickness of the insulating film 106a is W/2 or more.

Next, as shown in FIG. 1(c), the insulating film 1 is
06b and 102 are etched back by reactive ion etching, leaving the insulating film 106b with a flattened surface only inside the groove 104b, completing the formation of the element isolation region according to this embodiment. Note that the insulating film 102 may be removed before depositing the insulating film 106a.

Although the channel stopper is not mentioned in this embodiment, a p-type impurity may be added when growing the silicon epitaxial layer 105 if necessary.

FIG. 2 is a cross-sectional view of the process order for explaining this embodiment along the manufacturing method according to the second embodiment of the present invention. The width of the grooves 204a and 204b in this embodiment,
The film thicknesses of the silicon epitaxial layers 205a and 205b are the same as the widths of the grooves 104a and 104b and the film thickness of the silicon epitaxial layer 105 in the first embodiment.First, as shown in FIG. A photoresist film 203 is formed on the surface of the silicon substrate 201, a groove 204a is formed by etching using the photoresist film 203 as a mask, and p-type diffusion is performed on the bottom surface of the groove 204a by ion implantation using the photoresist film 203 as a mask. Form layer 207.

Next, as shown in FIG. 2B, after removing the photoresist film 203, a p-type silicon epitaxial layer 205a is formed on the entire surface. At this time, at the same time,
A groove 204b is formed. Subsequently, as shown in FIG. 2C, by etching back the silicon epitaxial layer 205a, a p-type silicon epitaxial layer 205b is formed remaining only on the side walls of the groove 204b. At this stage, the formation of the channel stopper is complete.

Next, as shown in FIG. 2(d), an insulating film 206a is deposited on the entire surface, and the trench 204b is filled with it. Subsequently, as shown in FIG. 2E, the insulating film 206b is left only inside the trench 204b by etching back, completing the formation of the element isolation region according to this embodiment.

FIG. 3 is a cross-sectional view of the process order for explaining this embodiment along the manufacturing method according to the third embodiment of the present invention. This embodiment relates to an element isolation region when an n-well 308 with a depth d is formed on the surface of a p-type silicon substrate 301. In this embodiment, reference will be made to the depth direction of the groove.

First, as shown in FIG. 3A, an n-well 308 with a depth d is formed on the surface of a p-type silicon substrate 301, and an insulating film 302 is formed on the n-well 308. After that, a photoresist film 303 is formed on the insulating film 302,
By etching using this as a mask, the depth d+β and the width W+
A groove 304a of 2α is formed. However, α<β.

Next, as shown in FIG. 3(b), after removing the photoresist film 303, p-type silicon is epitaxially grown. At this time, silicon epitaxial layer 305 grows only on the surface of groove 304a. By setting the thickness of the silicon epitaxial layer 305 to α, a groove 104b having a width W and a depth d−α+β is formed. By forming the groove 304a with a depth of d+β,
The p-type silicon epitaxial layer 305 is the n-well 3
08, which will function as a channel stopper. Subsequently, a BPSG film, for example, is deposited so as to completely fill the trench 304b, and if necessary, heat treatment is applied to form an insulating film 306a.

Next, as shown in FIG. 3(c), the insulating film 3
06b and 302 are etched back by reactive ion etching, leaving the insulating film 306b only inside the groove 304b, completing the formation of the element isolation region according to this embodiment.

[0019]

[Effects of the Invention] As explained above, in the present invention, a groove wider than a groove narrower than the minimum resolution dimension of a photoresist film is formed, and a semiconductor epitaxial layer is formed on the surface of this groove. As a result, a groove-shaped element isolation region having a width narrower than the minimum resolution dimension of the photoresist film can be obtained. Furthermore, if a channel stopper is required, a homogeneous channel stopper can be easily obtained by doping the semiconductor epitaxial layer with necessary impurities during growth.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view for explaining a third embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a trench-type element isolation region in a conventional semiconductor device and a method for manufacturing the same.

[Explanation of symbols]

101, 201, 301, 401 p-type silicon substrate 102, 106, 206, 302, 306, 406
Insulating film 103, 203, 303, 403 Photoresist film 104, 204, 304, 404 Groove 105
,205,305 Silicon epitaxial layer 2
07 p-type diffusion layer 308 n-well

Claims (16)

[Claims] 1. A semiconductor device comprising: a groove provided on the surface of a semiconductor of one conductivity type; a semiconductor epitaxial layer provided on the surface of the groove; and an insulating film buried inside the groove via the semiconductor epitaxial layer. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the semiconductor epitaxial layer is provided only on the side surface of the trench, and has a diffusion layer of one conductivity type on the semiconductor surface at the bottom of the trench. 3. The semiconductor device according to claim 1, wherein the semiconductor epitaxial layer is of one conductivity type. 4. The semiconductor device according to claim 2, wherein the semiconductor epitaxial layer is of one conductivity type. 5. A semiconductor device comprising: a semiconductor layer of an opposite conductivity type provided on the semiconductor surface; and the insulating film provided penetrating the semiconductor layer via the semiconductor epitaxial layer. The semiconductor device according to item 1. 6. The semiconductor device according to claim 5, wherein the semiconductor epitaxial layer is provided only on the side surfaces of the trench, and has a diffusion layer of one conductivity type on the semiconductor surface at the bottom of the trench. 7. The semiconductor device according to claim 5, wherein the semiconductor epitaxial layer is of one conductivity type. 8. The semiconductor device according to claim 6, wherein the semiconductor epitaxial layer is of one conductivity type. 9. A semiconductor substrate having a width W on the surface of a semiconductor substrate of one conductivity type.
A step of forming a groove of +2α, a step of forming a semiconductor epitaxial layer having a thickness of α on the surface of the groove, and a step of embedding an insulating film inside the groove via the semiconductor epitaxial layer. A method for manufacturing a featured semiconductor device. 10. A step of forming a groove having a width of W+2α on the surface of a semiconductor substrate of one conductivity type, forming a diffusion layer of one conductivity type on the semiconductor surface at the bottom of the groove, and forming a diffusion layer of one conductivity type on the surface of the groove. 10. The method of manufacturing a semiconductor device according to claim 9, further comprising the steps of: forming a semiconductor epitaxial layer with α, and removing the semiconductor epitaxial layer at the bottom of the groove by etchback using anisotropic etching. 11. On the surface of a semiconductor layer of an opposite conductivity type with a film thickness d provided on the surface of a semiconductor substrate of one conductivity type, a layer with a depth of d +
10. The method of manufacturing a semiconductor device according to claim 9, further comprising the step of providing a groove deeper than α. 12. A layer having a depth of d+ on the surface of a semiconductor layer of an opposite conductivity type with a film thickness d provided on the surface of a semiconductor substrate of one conductivity type.
11. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of providing a groove deeper than α. 13. The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor epitaxial layer is of one conductivity type. 14. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor epitaxial layer is of one conductivity type. 15. The method of manufacturing a semiconductor device according to claim 11, wherein the semiconductor epitaxial layer is of one conductivity type. 16. The method of manufacturing a semiconductor device according to claim 12, wherein the semiconductor epitaxial layer is of one conductivity type.