CN115148582A - Self-aligned mask forming method - Google Patents

Self-aligned mask forming method Download PDF

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Publication number
CN115148582A
CN115148582A CN202110349814.6A CN202110349814A CN115148582A CN 115148582 A CN115148582 A CN 115148582A CN 202110349814 A CN202110349814 A CN 202110349814A CN 115148582 A CN115148582 A CN 115148582A
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silicon substrate
ion implantation
dielectric layer
mask
doping type
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杨瑞坤
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Galaxycore Shanghai Ltd Corp
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Galaxycore Shanghai Ltd Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention provides a self-aligned mask forming method, which is characterized in that a mask of processes such as ion implantation or epitaxial growth and the like is formed by etching a monocrystalline silicon substrate, so that the side wall of the mask can be straight, the process difficulty is reduced, and the process precision is ensured; masks for ion implantation or epitaxial growth of different doping types can be formed only by one-time photoetching, so that the self-alignment effect is achieved, and the error of nested alignment is avoided; by pre-burying the dielectric layer in the monocrystalline silicon substrate and stopping the step of removing the first mask to form the second mask in the pre-buried dielectric layer, the difference of etching uniformity caused by the difference of the key sizes of different parts of the first mask is avoided.

Description

Self-aligned mask forming method
Technical Field
The invention relates to a self-aligned mask forming method.
Background
In the conventional semiconductor process, multiple steps of ion implantation or epitaxial growth are usually required, and a thick photoresist or a dielectric layer of silicon oxide, silicon nitride or the like is generally used as a mask for the ion implantation or the epitaxial growth.
With the increasing demand for miniaturization and high integration of portable electronic devices, the Critical Dimension (Critical Dimension) of semiconductor devices is rapidly reduced, for example, in the field of CMOS image sensors, with the increasing demand for high pixel and small volume, the ion implantation depth of the photosensitive region and the isolation region is deeper and deeper, the width is smaller and smaller, the depth of the epitaxially grown trench is also deeper and smaller, and the aspect ratio of the required mask reaches, for example, 10:1 or more.
In order to form a mask with a required high aspect ratio, the process difficulty is increased, and the side wall of the mask is difficult to be straight, so that the appearance and the precision of an ion implantation area or an epitaxial layer are influenced; when it is necessary to form ion implantation regions or epitaxial layers of different doping types, masks for ion implantation or epitaxial growth of different doping types need to be formed by two times of photolithography, respectively, thereby increasing an error of nested alignment.
Disclosure of Invention
The invention aims to provide a self-aligned mask forming method, which reduces the process difficulty, ensures the process precision of ion implantation or epitaxial growth and the like by using a mask, has a self-aligned effect and avoids the error of nested alignment.
In view of the above, the present invention provides a self-aligned mask forming method, comprising: providing a monocrystalline silicon substrate with a pre-buried dielectric layer; etching the monocrystalline silicon substrate to form first grooves, and taking the parts between the first grooves as a first mask; and forming a dielectric layer to fill the first grooves, removing the first mask and stopping on the pre-buried dielectric layer to form second grooves, and taking the parts between the second grooves as second masks.
Preferably, the pre-buried dielectric layer completely covers or partially covers the monocrystalline silicon substrate.
Preferably, the step of providing the monocrystalline silicon substrate with the pre-buried dielectric layer includes: providing a first monocrystalline silicon substrate, forming a fully covered embedded dielectric layer inside the first monocrystalline silicon substrate, and epitaxially forming a second monocrystalline silicon substrate on the surface of the first monocrystalline silicon substrate; and the step of etching the monocrystalline silicon substrate to form the first groove is stopped at the pre-buried dielectric layer.
Preferably, the step of providing the monocrystalline silicon substrate with the pre-buried dielectric layer includes: and providing a third monocrystalline silicon substrate, forming a partially covered pre-buried dielectric layer on the surface of the third monocrystalline silicon substrate, and epitaxially forming a fourth monocrystalline silicon substrate on the surface of the third monocrystalline silicon substrate.
Preferably, the first mask and the second mask are used for carrying out ion implantation or epitaxial growth of different doping types on the monocrystalline silicon substrate.
Preferably, after the first mask is formed, the monocrystalline silicon substrate is subjected to ion implantation of a first doping type to form an ion implantation region of the first doping type; and after forming a second mask, carrying out ion implantation of a second doping type on the monocrystalline silicon substrate to form an ion implantation area of the second doping type.
Preferably, before or among the ion implantation of the first doping type, a dielectric layer is formed to cover the bottom and the side wall of the first trench, and the depth of the ion implantation area of the first doping type is adjusted by controlling the thickness of the dielectric layer at the bottom of the first trench; and adjusting the width of the ion implantation area of the first doping type by controlling the thickness of the dielectric layer on the side wall of the first groove.
Preferably, before the ion implantation of the second doping type or between the ion implantation of multiple times, a dielectric layer is formed to cover the bottom and the side wall of the second trench, and the depth of the ion implantation area of the second doping type is adjusted by controlling the thickness of the dielectric layer at the bottom of the second trench; and adjusting the width of the ion implantation area of the second doping type by controlling the thickness of the dielectric layer on the side wall of the second groove.
Preferably, the step of forming the first mask includes: and forming a patterned third mask on the monocrystalline silicon substrate by photoetching, etching the monocrystalline silicon substrate to form first grooves, wherein the monocrystalline silicon substrate between the first grooves, the embedded dielectric layer and the third mask above the embedded dielectric layer are jointly used as the first mask.
Preferably, a dielectric layer covering the bottom and the side walls of the first trench and the second trench is formed by thermal oxidation or deposition.
Preferably, the single crystal silicon substrate between the first doping type ion implantation region and the second doping type ion implantation region serves as a buffer layer, and the width of the buffer layer is adjusted by controlling the width of the first doping type ion implantation region and the width of the second doping type ion implantation region.
Preferably, the buffer layer is a low doped or undoped region.
Preferably, the first doping type ion implantation region and the second doping type ion implantation region serve as a photosensitive region and an isolation region of the image sensor, respectively.
According to the self-aligned mask forming method, the mask of the processes such as ion implantation or epitaxial growth is formed by etching the monocrystalline silicon substrate, so that the side wall of the mask can be straight, the process difficulty is reduced, and the process precision is ensured; the mask for ion implantation or epitaxial growth of different doping types can be formed only by once photoetching, so that the self-alignment effect is realized, and the error of nested alignment is avoided; by pre-burying the dielectric layer in the monocrystalline silicon substrate, the step of removing the first mask to form the second mask can be stopped at the pre-buried dielectric layer, so that the difference of etching uniformity caused by the difference of the key sizes of different parts of the first mask is avoided.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.
FIG. 1 is a flow chart of a method of forming a self-aligned mask of the present invention;
FIGS. 2-18 are process diagrams of a method for forming a self-aligned mask according to a first embodiment of the present invention;
fig. 19-35 are process diagrams illustrating a self-aligned mask forming method according to a second embodiment of the invention.
In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.
Detailed Description
In order to solve the problems in the prior art, the invention provides a self-aligned mask forming method, which is characterized in that a mask of processes such as ion implantation or epitaxial growth and the like is formed by etching a monocrystalline silicon substrate, so that the side wall of the mask can be straight, the process difficulty is reduced, and the process precision is ensured; the mask for ion implantation or epitaxial growth of different doping types can be formed only by once photoetching, so that the self-alignment effect is realized, and the error of nested alignment is avoided; by pre-burying the dielectric layer in the monocrystalline silicon substrate, the step of removing the first mask to form the second mask can be stopped at the pre-buried dielectric layer, so that the difference of etching uniformity caused by the difference of the key sizes of different parts of the first mask is avoided.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
FIG. 1 illustrates a self-aligned mask formation method of the present invention, comprising: providing a monocrystalline silicon substrate with a pre-buried dielectric layer; etching the monocrystalline silicon substrate to form first grooves, and taking the parts between the first grooves as a first mask; and forming a dielectric layer to fill the first grooves, removing the first mask and stopping on the pre-buried dielectric layer to form second grooves, and taking the parts between the second grooves as second masks. Preferably, the first mask and the second mask are used for carrying out ion implantation or epitaxial growth of different doping types on the monocrystalline silicon substrate.
Because the mask is formed by etching the monocrystalline silicon substrate, the side wall of the mask can be made straight, the process difficulty is reduced, and the process precision is ensured; masks for ion implantation or epitaxial growth of different doping types can be formed only by one-time photoetching, so that the self-alignment effect is achieved, and the error of nested alignment is avoided; by pre-burying the dielectric layer in the monocrystalline silicon substrate, the step of removing the first mask to form the second mask can be stopped at the pre-buried dielectric layer, so that the difference of etching uniformity caused by the difference of the key sizes of different parts of the first mask is avoided.
The present invention will be described in detail with reference to specific examples.
Example one
Fig. 2-18 illustrate a preferred embodiment of the self-aligned mask forming method of the present invention. In this embodiment, the first mask and the second mask are formed and used for ion implantation processes of different doping types, and those skilled in the art can understand that the formation process of the masks used for other processes such as epitaxial growth is similar to that of this embodiment.
Referring to fig. 2-3, a first monocrystalline silicon substrate 131 is provided, a pre-buried dielectric layer 133 is formed inside the first monocrystalline silicon substrate 131, the pre-buried dielectric layer 133 completely covers the first monocrystalline silicon substrate 131, and a second monocrystalline silicon substrate 132 is epitaxially formed on the surface of the first monocrystalline silicon substrate 131, so that the monocrystalline silicon substrate 100 (including the first monocrystalline silicon substrate 131 and the second monocrystalline silicon substrate 132) with the pre-buried dielectric layer 133 is formed.
The pre-buried dielectric layer 133 may be, for example, a silicon oxide layer, and a specific implementation manner may be to form a buried oxide layer (with a bulk concentration of about 2E 18) inside the first monocrystalline silicon substrate 131, because the quality requirement of the buried oxide layer is generally low, the conventional ion implantation process may meet the requirement, or multiple times of ion implantation may be used to increase the thickness of the buried oxide layer, and then, the buried oxide layer is activated to form the silicon oxide layer 133. Of course, other forming methods or pre-buried dielectric layers 133 made of other materials may be used.
Referring to fig. 4-6, a silicon oxide layer 101 and a silicon nitride layer 102 are sequentially formed on the single crystal silicon substrate 100 having the pre-buried dielectric layer 133, the patterned silicon oxide layer 101 and the patterned silicon nitride layer 102 are formed on the single crystal silicon substrate 100 by photolithography and etching, the single crystal silicon substrate 100 is etched by using the silicon oxide layer 101 and the patterned silicon nitride layer 102 as a third mask 110, and the first trench 103 is formed by stopping on the pre-buried dielectric layer 133. The pre-buried dielectric layer 133 serves as a stop layer for etching the monocrystalline silicon substrate 100, and can well control the morphology and the precision of the first trench 103.
In other preferred embodiments not shown, a single common dielectric such as a silicon oxide layer, a silicon oxynitride layer, or a combination thereof may be used as the third mask for etching the single crystal silicon substrate.
Referring to fig. 7 to 11, the single crystal silicon substrate 100 (i.e., the first single crystal silicon substrate 131 portion) under the first trench 103 is ion-implanted with the first doping type using the portion between the first trenches 103 as a first mask to form first doping type ion-implanted regions 105a, 105b.
In the present embodiment, the single crystal silicon substrate 100 (including the first single crystal silicon substrate 131 and the second single crystal silicon substrate 132) between the first trenches 103, the pre-buried dielectric layer 133 and the third mask 110 above the pre-buried dielectric layer are used together as a first mask for the ion implantation of the first doping type, so as to prevent the tunnel Effect (Channel Effect) in the ion implantation process from affecting the ion implantation concentration. In other preferred embodiments not shown, the third mask 110 may also be removed, and only the monocrystalline silicon substrate 100 and the pre-buried dielectric layer 133 between the first trenches 103 are used as the first mask for the ion implantation of the first doping type. Because the first mask is formed by etching the monocrystalline silicon substrate, the side wall of the first mask can be made straight, the process difficulty is reduced, and the appearance and the precision of an ion implantation area are ensured.
Specifically, first, a dielectric layer 104 (taking silicon oxide as an example herein) is formed by thermal oxidation or deposition to cover the bottom and the sidewall of the first trench 103 (see fig. 7), then, as required, the dielectric layer 104 and the pre-buried dielectric layer 133 at the bottom of the first trench 103 are completely removed (see fig. 8) or the dielectric layer 104 and the pre-buried dielectric layer 133 at the bottom of the first trench 103 are partially removed to adjust the thicknesses of the dielectric layer 104 and the pre-buried dielectric layer 133 to a preset range, then, with the portion between the first trenches 103 as a first mask, ion implantation of a first doping type is performed on the monocrystalline silicon substrate 100 below the first trench 103 to form a deep ion implantation region 105a (see fig. 9), and then, a dielectric layer 104 is formed by thermal oxidation or deposition to cover the bottom and the sidewall of the first trench 103 (see fig. 10) to adjust the thickness of the dielectric layer 104 as required, and ion implantation of the first doping type is performed on the monocrystalline silicon substrate 100 below the first trench 103 again to form a shallow ion implantation region 105b (see fig. 11).
That is, before the first doping type ion implantation or among multiple ion implantations, the depth of the first doping type ion implantation regions 105a and 105b can be adjusted by forming the dielectric layer 104 to cover the bottom and the side wall of the first trench 103 and by controlling the thickness of the dielectric layer 104 and the pre-buried dielectric layer 133 at the bottom of the first trench 103, so as to realize the effects of wide depth distribution of high-energy deep ion implantation (for example, corresponding to the ion implantation region 105 a) and small depth distribution of low-energy shallow ion implantation (for example, corresponding to the ion implantation region 105 b); and the width of the first doping type ion implantation regions 105a and 105b is adjusted by controlling the thickness of the dielectric layer 104 on the side wall of the first trench 103.
Referring to fig. 12-15, after the first doping type ion implantation regions 105a and 105b are formed, the first trench 103 is preferably filled by low temperature annealing or a non-annealing High Aspect Ratio (HARP) deposition dielectric layer 104, the top dielectric layer 104 is removed by chemical mechanical polishing to stop at the surface of the silicon nitride layer 102 (or at the surface of the single crystal silicon substrate if a single silicon oxide layer is used as a third mask), and then the silicon nitride layer 102, the silicon oxide layer 101, and the single crystal silicon substrate 100 between the dielectric layers 104 are sequentially removed (i.e., the first mask is removed) to stop at the pre-buried dielectric layer 133, thereby forming the second trench 107.
Due to the fact that the pre-buried dielectric layer 133 is arranged in the monocrystalline silicon substrate 100 in advance, the step of removing the first mask can be stopped at the pre-buried dielectric layer 133, and the phenomenon that the appearance and the precision of a second groove and a second mask formed subsequently are affected due to the fact that the etching uniformity difference is caused by the difference of the key sizes of different parts of the first mask (the first mask is in a criss-cross structure, and the key size near an intersection point is larger than the key sizes of other parts of the first mask) is avoided.
Referring to fig. 16-17, the portion between the second trenches 107 (i.e., the dielectric layer 104) is used as a second mask to perform a second doping type ion implantation on the monocrystalline silicon substrate 100 under the second trenches 107, so as to form second doping type ion implantation regions 106a, 106b. The self-alignment mask can be used for forming ion implantation masks with different doping types only by once photoetching, so that the self-alignment effect is achieved, and the error of nested alignment is avoided.
Similarly, before the second doping type ion implantation or among multiple ion implantations, a dielectric layer 104 may be formed to cover the bottom and the sidewall of the second trench 107 in a thermal oxidation or deposition manner (since the sidewall of the second trench 107 is the dielectric layer 104, this step is equivalent to increasing the thickness of the dielectric layer 104 on the basis of the original dielectric layer 104), and by controlling the thicknesses of the dielectric layer 104 and the pre-buried dielectric layer 133 at the bottom of the second trench 107, the depths of the ion implantation regions 106a and 106b of the second doping type are adjusted, so as to achieve the effects of wide depth distribution of high-energy deep ion implantation (e.g., corresponding to the ion implantation region 106 a) and small depth distribution of low-energy shallow ion implantation (e.g., corresponding to the ion implantation region 106 b); and the width of the ion implantation regions 106a and 106b of the second doping type is adjusted by controlling the thickness of the dielectric layer 104 on the side wall of the second trench 107.
As shown in fig. 17, the single crystal silicon substrate 100 between the first doping type ion implantation regions 105a and 105b and the second doping type ion implantation regions 106a and 106b is generally a low doped or undoped region, and can be used as a buffer layer between the ion implantation regions of different doping types, and the purpose of adjusting the width of the buffer layer can be achieved by controlling the width of the first doping type ion implantation regions 105a and 105b and the width of the second doping type ion implantation regions 106a and 106b.
Finally, referring to fig. 18, the second mask and the pre-buried dielectric layer 133 are removed, and the single crystal silicon substrate is planarized for subsequent processes.
The self-aligned mask forming method of the embodiment is particularly suitable for the field of CMOS image sensors, and preferably, the first mask and the second mask have a width smaller than 0.5 micrometer and a depth larger than 2 micrometers, and ion implantation is performed through the self-aligned mask with a high aspect ratio to form a first doping type ion implantation region and a second doping type ion implantation region which are respectively used as a photosensitive region and an isolation region of the image sensor, so as to meet the product requirements of high pixels and small volume.
Example two
Fig. 19-35 illustrate another preferred embodiment of the self-aligned mask forming method of the present invention. In this embodiment, the first mask and the second mask are formed and used for ion implantation processes of different doping types, and those skilled in the art can understand that the formation process of the masks used for other processes such as epitaxial growth is similar to that of this embodiment.
Referring to fig. 19-21, a third monocrystalline silicon substrate 231 is provided, a pre-buried dielectric layer 233 with a thickness of 0.2 to 0.3 microns, such as a silicon oxide layer, is completely covered on the surface of the third monocrystalline silicon substrate 231 by a thermal oxidation or deposition method, then the pre-buried dielectric layer 233 is formed by etching the pre-buried dielectric layer 233, the pre-buried dielectric layer 233 is partially covered on the third monocrystalline silicon substrate 231, and then a fourth monocrystalline silicon substrate 232 is epitaxially formed on the surface of the third monocrystalline silicon substrate 231, so that the monocrystalline silicon substrate 200 (including the third monocrystalline silicon substrate 231 and the fourth monocrystalline silicon substrate 232) with the pre-buried dielectric layer 233 is formed.
Referring to fig. 22 to 24, a silicon oxide layer 201 and a silicon nitride layer 202 are sequentially formed on a single-crystal silicon substrate 200 having an embedded dielectric layer 233, a patterned silicon oxide layer 201 and a patterned silicon nitride layer 202 are formed on the single-crystal silicon substrate 200 by photolithography and etching, the single-crystal silicon substrate 200 is etched by using the silicon oxide layer 201 and the silicon nitride layer 202 as a third mask 210, and preferably, a third single-crystal silicon substrate 231 (the surface of the third single-crystal silicon substrate 233 is slightly damaged) which stops near the embedded dielectric layer 233, thereby forming a first trench 203.
In other preferred embodiments not shown, a single common dielectric such as a silicon oxide layer, a silicon oxynitride layer, or a combination thereof may be used as the third mask for etching the single crystal silicon substrate.
Referring to fig. 25 to 28, the single-crystal silicon substrate 200 (i.e., the third single-crystal silicon substrate 231 portion) under the first trench 203 is ion-implanted with the first doping type using the portion between the first trenches 203 as a first mask to form the ion-implanted regions 205a, 205b with the first doping type.
In the present embodiment, the single crystal silicon substrate 200 (including the third single crystal silicon substrate 231 and the fourth single crystal silicon substrate 232) between the first trenches 203, the pre-buried dielectric layer 233 and the third mask 210 above the pre-buried dielectric layer 233 are used together as a first mask for the ion implantation of the first doping type, so as to prevent the tunnel Effect (tunnel Effect) in the ion implantation process from affecting the ion implantation concentration. In other preferred embodiments not shown, the third mask 210 may also be removed, and only the monocrystalline silicon substrate 200 and the pre-buried dielectric layer 233 between the first trenches 203 are used as the first mask for the ion implantation of the first doping type. Because the first mask is formed by etching the monocrystalline silicon substrate, the side wall of the first mask can be made straight, the process difficulty is reduced, and the appearance and the precision of an ion implantation area are ensured.
Specifically, first, a dielectric layer 204 (here, silicon oxide is taken as an example) is formed by thermal oxidation or deposition to cover the bottom and the side walls of the first trench 203 (see fig. 25), then, as required, the dielectric layer 204 at the bottom of the first trench 203 is completely removed (see fig. 26) or the dielectric layer 204 at the bottom of the first trench 203 is partially removed to adjust the thickness of the dielectric layer 204 to a preset range, next, ion implantation of the first doping type is performed on the monocrystalline silicon substrate 200 below the first trench 203 by using the portion between the first trenches 203 as a first mask to form a deep ion implantation region 205a (see fig. 27), and then, the dielectric layer 204 is formed by thermal oxidation or deposition to cover the bottom and the side walls of the first trench 203 (not shown) to adjust the thickness of the dielectric layer 204 as required, and ion implantation of the first doping type is performed on the monocrystalline silicon substrate 200 below the first trench 203 again to form a shallow ion implantation region 205b (see fig. 28).
That is to say, before the first doping type ion implantation or between multiple times of ion implantation, the depth of the first doping type ion implantation regions 205a and 205b can be adjusted by forming the dielectric layer 204 to cover the bottom and the sidewall of the first trench 203 and by controlling the thickness of the dielectric layer 204 at the bottom of the first trench 203, so as to achieve the effects of wide depth distribution of high-energy deep ion implantation (for example, corresponding to the ion implantation region 205 a) and small depth distribution of low-energy shallow ion implantation (for example, corresponding to the ion implantation region 205 b); and the width of the ion implantation regions 205a, 205b of the first doping type is adjusted by controlling the thickness of the dielectric layer 204 on the sidewall of the first trench 203.
Referring to fig. 29-32, after the first doping type ion implantation regions 205a and 205b are formed, the first trench 203 is preferably filled by depositing a dielectric layer 204 through a low temperature annealing or a non-annealing High Aspect Ratio (HARP) Process, removing the top dielectric layer 204 by chemical mechanical polishing to stop at the surface of the silicon nitride layer 202 (or at the surface of the single crystal silicon substrate if a single silicon oxide layer is used as a third mask), and then sequentially removing the silicon nitride layer 202, the silicon oxide layer 201, and the single crystal silicon substrate 200 (i.e., removing the first mask) between the dielectric layers 204 to stop at the pre-buried dielectric layer 233, thereby forming the second trench 207.
Because the pre-buried dielectric layer 233 is arranged in the monocrystalline silicon substrate 200 in advance, the step of removing the first mask can be stopped at the pre-buried dielectric layer 233, so that the etching uniformity difference caused by the difference of the key sizes of different parts of the first mask (the first mask is in a criss-cross structure, and the key size near the intersection point is larger than the key sizes of other parts) is avoided, and the appearance and the precision of a subsequently formed second groove and a second mask are influenced.
Referring to fig. 33, the portions between the second trenches 207 (i.e., the dielectric layer 204) are used as a second mask to perform a second doping type ion implantation on the monocrystalline silicon substrate 200 under the second trenches 207, so as to form second doping type ion implantation regions 206a and 206b. The self-alignment mask can be used for forming ion implantation masks with different doping types only by once photoetching, so that the self-alignment effect is achieved, and the error of nested alignment is avoided.
Similarly, before the second doping type ion implantation or among multiple ion implantations, a dielectric layer 204 may be formed to cover the bottom and the sidewall of the second trench 207 by thermal oxidation or deposition (since the sidewall of the second trench 207 is the dielectric layer 204, this step is equivalent to increasing the thickness of the dielectric layer 204 on the basis of the original dielectric layer 204), and the depth of the ion implantation regions 206a and 206b of the second doping type is adjusted by controlling the thickness of the dielectric layer 204 and the pre-buried dielectric layer 233 at the bottom of the second trench 207, so as to achieve the effects of wide depth distribution of high-energy deep ion implantation (e.g., corresponding to the ion implantation region 206 a) and small depth distribution of low-energy shallow ion implantation (e.g., corresponding to the ion implantation region 206 b); and the width of the ion implantation regions 206a, 206b of the second doping type is adjusted by controlling the thickness of the dielectric layer 204 on the sidewalls of the second trench 207.
As shown in fig. 33, the single crystal silicon substrate 200 between the first doping type ion implantation regions 205a and 205b and the second doping type ion implantation regions 206a and 206b is generally a low doped or undoped region, and can be used as a buffer layer between the ion implantation regions of different doping types, and the purpose of adjusting the width of the buffer layer can be achieved by controlling the width of the first doping type ion implantation regions 205a and 205b and the width of the second doping type ion implantation regions 206a and 206b.
Finally, referring to fig. 24-35, the second mask and the pre-buried dielectric layer 233 are removed, and the single-crystal silicon substrate is planarized for subsequent processes.
The self-aligned mask forming method of the embodiment is particularly suitable for the field of CMOS image sensors, and preferably, the first mask and the second mask have a width smaller than 0.5 micrometer and a depth larger than 2 micrometers, and ion implantation is performed through the self-aligned mask with a high aspect ratio to form a first doping type ion implantation region and a second doping type ion implantation region which are respectively used as a photosensitive region and an isolation region of the image sensor, so as to meet the product requirements of high pixels and small volume.
In summary, the self-aligned mask forming method of the present invention forms a mask for ion implantation or epitaxial growth by etching the monocrystalline silicon substrate, so that the sidewall of the mask can be made straight, the process difficulty is reduced, and the process precision is ensured; masks for ion implantation or epitaxial growth of different doping types can be formed only by one-time photoetching, so that the self-alignment effect is achieved, and the error of nested alignment is avoided; by pre-burying the dielectric layer in the monocrystalline silicon substrate, the step of removing the first mask to form the second mask can be stopped at the pre-buried dielectric layer, so that the difference of etching uniformity caused by the difference of key sizes of different parts of the first mask is avoided.
In addition, the width of the ion implantation area is adjusted by controlling the thickness of the dielectric layer on the side wall of the groove, so that the width of the buffer layer between the ion implantation areas with different doping types is adjusted; the depth of the ion implantation area is adjusted by controlling the thickness of the medium layer at the bottom of the groove, so that the effects of wide distribution of high-energy deep layer ion implantation depth and small distribution of low-energy shallow layer ion implantation depth are realized.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. It will furthermore be evident that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims (13)

1. A method of forming a self-aligned mask, comprising:
providing a monocrystalline silicon substrate with a pre-buried dielectric layer;
etching the monocrystalline silicon substrate to form first grooves, and using the parts between the first grooves as a first mask; and forming a dielectric layer to fill the first grooves, removing the first mask and stopping on the pre-buried dielectric layer to form second grooves, and taking the parts between the second grooves as second masks.
2. The method of claim 1, wherein the pre-buried dielectric layer completely covers or partially covers the single-crystal silicon substrate.
3. The method of claim 2, wherein the step of providing the single crystal silicon substrate with the buried dielectric layer comprises: providing a first monocrystalline silicon substrate, forming a fully covered embedded dielectric layer inside the first monocrystalline silicon substrate, and epitaxially forming a second monocrystalline silicon substrate on the surface of the first monocrystalline silicon substrate; and the step of etching the monocrystalline silicon substrate to form the first groove is stopped at the pre-buried dielectric layer.
4. The method of claim 2, wherein the step of providing the single crystal silicon substrate with the buried dielectric layer comprises: and providing a third monocrystalline silicon substrate, forming a partially covered pre-buried dielectric layer on the surface of the third monocrystalline silicon substrate, and epitaxially forming a fourth monocrystalline silicon substrate on the surface of the third monocrystalline silicon substrate.
5. The self-aligned mask forming method according to claim 1, wherein the first mask and the second mask are used for ion implantation or epitaxial growth of different doping types for the single crystal silicon substrate.
6. The self-aligned mask forming method according to claim 5, wherein after the first mask is formed, ion implantation of a first doping type is performed on the single-crystal silicon substrate to form an ion implanted region of the first doping type; and after forming a second mask, carrying out ion implantation of a second doping type on the monocrystalline silicon substrate to form an ion implantation area of the second doping type.
7. The self-aligned mask forming method of claim 6, wherein a dielectric layer is formed to cover the bottom and sidewalls of the first trench before the ion implantation of the first doping type or between the ion implantation of the first doping type, and the depth of the ion implantation region of the first doping type is adjusted by controlling the thickness of the dielectric layer at the bottom of the first trench; and adjusting the width of the ion implantation area of the first doping type by controlling the thickness of the dielectric layer on the side wall of the first groove.
8. The method of claim 7, wherein a dielectric layer is formed to cover the bottom and sidewalls of the second trench before the second doping type ion implantation or between the multiple ion implantations, and the depth of the second doping type ion implantation region is adjusted by controlling the thickness of the dielectric layer at the bottom of the second trench; and adjusting the width of the ion implantation area of the second doping type by controlling the thickness of the dielectric layer on the side wall of the second groove.
9. The self-aligned mask forming method of claim 1, wherein the step of forming the first mask comprises: and forming a patterned third mask on the monocrystalline silicon substrate by photoetching, etching the monocrystalline silicon substrate to form first grooves, wherein the monocrystalline silicon substrate between the first grooves, the embedded dielectric layer and the third mask above the embedded dielectric layer are jointly used as the first mask.
10. The method of claim 8, wherein a dielectric layer covering the bottom and sidewalls of the first trench and the second trench is formed by thermal oxidation or deposition.
11. The self-aligned mask forming method according to claim 8, wherein the single crystal silicon substrate between the ion implantation region of the first doping type and the ion implantation region of the second doping type serves as a buffer layer, and the width of the buffer layer is adjusted by controlling the width of the ion implantation region of the first doping type and the width of the ion implantation region of the second doping type.
12. The method of claim 11, wherein the buffer layer is a low doped or undoped region.
13. The self-aligned mask forming method according to claim 6, wherein the first doping type ion implantation region and the second doping type ion implantation region are used as a photosensitive region and an isolation region of the image sensor, respectively.
CN202110349814.6A 2021-03-31 2021-03-31 Self-aligned mask forming method Pending CN115148582A (en)

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