JPH04304428A - Manufacture of active matrix liquid crystal display - Google Patents
Manufacture of active matrix liquid crystal displayInfo
- Publication number
- JPH04304428A JPH04304428A JP3068668A JP6866891A JPH04304428A JP H04304428 A JPH04304428 A JP H04304428A JP 3068668 A JP3068668 A JP 3068668A JP 6866891 A JP6866891 A JP 6866891A JP H04304428 A JPH04304428 A JP H04304428A
- Authority
- JP
- Japan
- Prior art keywords
- film
- liquid crystal
- crystal display
- active matrix
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 33
- 239000011159 matrix material Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims abstract description 116
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 18
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 230000001681 protective effect Effects 0.000 description 19
- 229910004205 SiNX Inorganic materials 0.000 description 9
- 239000007789 gas Substances 0.000 description 9
- 239000011651 chromium Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 238000007740 vapor deposition Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、薄膜トランジスタを用
いたアクティブマトリックス液晶ディスプレイの製造方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix liquid crystal display using thin film transistors.
【0002】0002
【従来の技術】従来、このような分野の技術としては、
例えば、特開昭63−284522号に記載されるもの
があった。薄膜トランジスタTFT(Thin Fi
lm Transistor)液晶ディスプレイは軽
い、低消費電力、高精細、大容量などの特徴があるので
、最近、大きな市場を形成するようになってきている。
特に、液晶パネルは、面積が大きくなることにつれて、
面内特性の均一性が大きな問題になる。[Prior Art] Conventionally, technologies in this field include:
For example, there was one described in JP-A-63-284522. Thin film transistor TFT
(lm Transistor) Since liquid crystal displays have characteristics such as light weight, low power consumption, high definition, and large capacity, they have recently started to form a large market. In particular, as the area of liquid crystal panels increases,
Uniformity of in-plane properties becomes a major problem.
【0003】図3は従来のアクティブマトリックス液晶
ディスプレイ(AMLCD)の構造を示す要部断面図で
ある。この図に示すように、まずAMLCDの下基板と
なるα−SiTFT基板は、第1透明絶縁基板1の上に
、クロム(Cr)、タンタル(Ta)、モリブデン(M
o)、アルミニウム(Al)よりなる金属層を、スパッ
タ、または蒸着により0.1〜0.3μm程度成膜し、
その後ホトリソエッチングより、所定の形状に加工する
ことでゲート電極2を形成する。FIG. 3 is a sectional view of a main part showing the structure of a conventional active matrix liquid crystal display (AMLCD). As shown in this figure, an α-SiTFT substrate, which will become the lower substrate of the AMLCD, is placed on a first transparent insulating substrate 1 containing chromium (Cr), tantalum (Ta), and molybdenum (M).
o) A metal layer made of aluminum (Al) is formed to a thickness of about 0.1 to 0.3 μm by sputtering or vapor deposition,
Thereafter, the gate electrode 2 is formed by processing into a predetermined shape by photolithography etching.
【0004】次いで、陽極酸化法で第1ゲート絶縁膜と
なるゲート金属酸化膜3を0.1〜0.5μm形成する
。次に、NH3 ,SiH4 ガスを主成分とするプラ
ズマCVD(PCVD)法により、第2ゲート絶縁膜と
するシリコン窒化膜(SiNx )4を、膜厚0.1〜
0.4μm、SiH4 ガスを主成分とするPCVD法
により、アモルファスシリコン膜(n− −α−Si)
を膜厚0.05μm〜0.2μm、SiH4 ガスとP
H3 ガスを主成分とするPCVD法により、n+ −
α−Si層を0.01〜0.1μmそれぞれ基板全面に
堆積させる。[0004] Next, a gate metal oxide film 3, which will become a first gate insulating film, is formed to a thickness of 0.1 to 0.5 μm by an anodic oxidation method. Next, a silicon nitride film (SiNx) 4, which will serve as a second gate insulating film, is deposited to a thickness of 0.1 to
0.4μm, amorphous silicon film (n- -α-Si) was formed by PCVD method using SiH4 gas as the main component.
The film thickness is 0.05 μm to 0.2 μm, SiH4 gas and P
By the PCVD method using H3 gas as the main component, n+ −
An α-Si layer of 0.01 to 0.1 μm is deposited on the entire surface of the substrate.
【0005】次いで、アルミニウム(Al)、クロム(
Cr)、ニクロム(NiCr)などよりなる金属層を、
スパッタ、または蒸着により0.3〜1.0μm程度成
膜し、それを所定の形状に加工することにより、ソース
電極7及びドレイン電極8を形成する。そして、ホトリ
ソと反応性イオンエッチングにより、α−Si半導体層
5,6を所定の島形状に形成する。その後、半導体層5
上のチャンネン部分の不要オーミック層6をCF4 と
O2 を主成分とするRIEによるドライエッチングに
より除去する。Next, aluminum (Al), chromium (
Cr), nichrome (NiCr), etc.
The source electrode 7 and the drain electrode 8 are formed by forming a film with a thickness of about 0.3 to 1.0 μm by sputtering or vapor deposition and processing it into a predetermined shape. Then, the α-Si semiconductor layers 5 and 6 are formed into a predetermined island shape by photolithography and reactive ion etching. After that, the semiconductor layer 5
The unnecessary ohmic layer 6 in the upper channel portion is removed by dry etching using RIE mainly containing CF4 and O2.
【0006】次に、PCVD法により、シリコン窒化膜
(SiNx )などからなる中間絶縁膜9を形成する。
その後、ソースと次に形成する透明電極ITO膜との導
通のためのコンタクトホール10を中間絶縁膜の所定部
分に形成する。そして、ITO膜(In2 O3 +S
nO2 )を、スパッタ、または蒸着により0.1μm
程度成膜し、それを所定の形状に加工することで表示用
電極となる透明電極11を形成する。Next, an intermediate insulating film 9 made of a silicon nitride film (SiNx) or the like is formed by the PCVD method. Thereafter, a contact hole 10 for electrical connection between the source and a transparent electrode ITO film to be formed next is formed in a predetermined portion of the intermediate insulating film. Then, ITO film (In2 O3 +S
nO2) to 0.1 μm by sputtering or vapor deposition.
By forming a film to a certain extent and processing it into a predetermined shape, a transparent electrode 11 that becomes a display electrode is formed.
【0007】最後に、PCVD法によりシリコン窒化膜
(SiNx )などからなる絶縁膜を成膜し、そして加
工により所定の形状にすることで下基板の表面保護膜1
2を形成する。以上の透明電極付α−SiTFTを、2
次元的に配置することで、α−SiTFTアレイ基板が
完成する。このTFTアレイ基板上に膜厚0.1μmの
ポリイミドよりなる有機膜を形成し、ラビング処理する
ことで配向処理膜13を形成する。その後、セル間隔を
均一に形成、保持するために、直径3〜10μmのスペ
ーサ14を配向処理膜13上に散布することで下基板が
完成する。Finally, an insulating film made of silicon nitride (SiNx) or the like is formed by the PCVD method and processed into a predetermined shape to form the surface protective film 1 of the lower substrate.
form 2. The above α-Si TFT with transparent electrode is
By dimensionally arranging them, an α-SiTFT array substrate is completed. An organic film made of polyimide having a thickness of 0.1 μm is formed on this TFT array substrate, and an alignment treatment film 13 is formed by rubbing the organic film. Thereafter, in order to form and maintain uniform cell spacing, spacers 14 having a diameter of 3 to 10 μm are sprinkled on the alignment film 13 to complete the lower substrate.
【0008】一方、上基板(対向電極側)は、以下に示
す如く形成される。即ち、透明絶縁基板15上に膜厚0
.1μm程度のITO膜よりなる対向透明電極16を、
スパッタ、または蒸着と加工により所定の形状に形成す
る。次いで、光の漏れを防止し、コントラストを向上さ
せるためのブラックマトリックス層17を形成する。こ
の対向電極上に膜厚0.1μm程度のポリイミドよりな
る有機膜を形成し、ラビング処理することで配向処理膜
18を形成する。On the other hand, the upper substrate (counter electrode side) is formed as shown below. That is, the film thickness is 0 on the transparent insulating substrate 15.
.. A counter transparent electrode 16 made of an ITO film of about 1 μm,
It is formed into a predetermined shape by sputtering or vapor deposition and processing. Next, a black matrix layer 17 is formed to prevent light leakage and improve contrast. An organic film made of polyimide having a thickness of about 0.1 μm is formed on this counter electrode, and a rubbing process is performed to form an alignment film 18.
【0009】更に、高分子絶縁材料(エポキシ系などの
材料)にスペーサを混入させた材料を用いた厚膜のスク
リーン印刷法により、膜厚5〜20μmのシール層19
を所定のパターンで形成することにより、上基板が完成
する。上基板と下基板が完成したら、シール層を挟んで
、該シール層により上下基板を位置合わせし、貼り合わ
せ後、加圧固定し、シール層を加熱硬化させる。更に、
シール層の内側を真空脱気した後、所定の注入口より液
晶20を注入する。Furthermore, a sealing layer 19 with a thickness of 5 to 20 μm is formed by a thick film screen printing method using a material in which a spacer is mixed into a polymeric insulating material (such as an epoxy material).
By forming a predetermined pattern, the upper substrate is completed. When the upper and lower substrates are completed, the upper and lower substrates are aligned with a sealing layer in between, and after bonding, they are fixed under pressure and the sealing layer is heated and cured. Furthermore,
After the inside of the seal layer is vacuum degassed, liquid crystal 20 is injected through a predetermined injection port.
【0010】最後に、注入口を封止し、偏光膜21を所
定の位置に貼り付けることにより、α−SiTFTを用
いた液晶ディスプレイが完成する。Finally, by sealing the injection port and pasting the polarizing film 21 in a predetermined position, a liquid crystal display using α-SiTFT is completed.
【0011】[0011]
【発明が解決しようとする課題】TFTはアドレス線、
データ線を介してマトリックス状に多数接続されており
、薄膜トランジスタマトリックスを駆動することにより
、透明画素電極11と対向透明電極16間に電圧が印加
され、液晶20が駆動される。液晶20の厚みdは、使
用する液晶材料などによって最適値が異なるが、液晶デ
ィスプレイの画面内における厚みdのバラツキは、なる
べく小さい値にすることが望ましい。厚みdのバラツキ
が大きい場合、色ムラ、応答速度のバラツキが発生して
表示品質を劣化させる原因となる。[Problem to be solved by the invention] The TFT has an address line,
A large number of transistors are connected in a matrix through data lines, and by driving the thin film transistor matrix, a voltage is applied between the transparent pixel electrode 11 and the opposing transparent electrode 16, and the liquid crystal 20 is driven. Although the optimal value for the thickness d of the liquid crystal 20 varies depending on the liquid crystal material used, it is desirable that the variation in the thickness d within the screen of the liquid crystal display be as small as possible. If the variation in the thickness d is large, color unevenness and variation in response speed occur, causing deterioration of display quality.
【0012】そして、TFTがある下基板の製造では、
第1透明絶縁基板の上に数回にわたって成膜をする。こ
れらの膜に内部応力が存在するため、該下基板が変形し
てしまう。例えば、図4(a)に示すように、基板上に
シリコン酸化膜(SiOx )のパッシベーション膜を
所定の条件で形成すると、上に凸の形状に基板が変形し
てしまう。また、基板上にシリコン窒化膜(SiNx)
のパッシベーション膜を形成すると、上に凹の形状に基
板が変形してしまう。[0012] In manufacturing the lower substrate on which the TFT is located,
A film is formed several times on the first transparent insulating substrate. The presence of internal stress in these films causes the lower substrate to deform. For example, as shown in FIG. 4A, when a passivation film of silicon oxide (SiOx) is formed on a substrate under predetermined conditions, the substrate is deformed into an upwardly convex shape. In addition, a silicon nitride film (SiNx) is formed on the substrate.
When a passivation film is formed, the substrate is deformed into an upwardly concave shape.
【0013】この問題を解決するため、特開昭63−2
84522号では、下基板の表面保護膜をシリコン酸化
膜(SiOx )とシリコン窒化膜(SiNx )から
なる二層構造で、保護膜全体の反りを無くすように、二
種の膜厚を調節する。しかし、保護膜を二層構造にする
には、成膜プロセスが面倒になる。また、保護膜を形成
するまで下基板の上に成膜を数回行ったことによって、
下基板はもう既に変形している可能性があるので、保護
膜の反りを無くしたとしても、下基板全体の反りが残さ
れている。このため液晶層の厚みを画面全体にわたって
均一にすることが困難であるという問題があった。[0013] In order to solve this problem, Japanese Patent Laid-Open No. 63-2
In No. 84522, the surface protective film of the lower substrate has a two-layer structure consisting of a silicon oxide film (SiOx) and a silicon nitride film (SiNx), and the thicknesses of the two types of films are adjusted so as to eliminate warpage of the entire protective film. However, forming the protective film into a two-layer structure requires a complicated film formation process. In addition, by forming the film on the lower substrate several times until the protective film was formed,
Since the lower substrate may have already been deformed, even if the warpage of the protective film is eliminated, the entire lower substrate remains warped. Therefore, there was a problem in that it was difficult to make the thickness of the liquid crystal layer uniform over the entire screen.
【0014】本発明は、上に述べたアクティブマトリッ
クス液晶ディスプレイの下基板が変形するという問題点
を除去し、色ムラや応答速度のバラツキが少ない表示品
質の優れた薄膜トランジスタを用いたアクティブマトリ
ックス液晶ディスプレイの製造方法を提供することを目
的とする。The present invention eliminates the problem of the deformation of the lower substrate of the active matrix liquid crystal display mentioned above, and provides an active matrix liquid crystal display using thin film transistors that has excellent display quality with less color unevenness and variation in response speed. The purpose is to provide a manufacturing method for.
【0015】[0015]
【課題を解決するための手段】本発明は、上記目的を達
成するために、マトリックス状に接続された複数の薄膜
トランジスタが形成され、その上に表面保護膜となるシ
リコン窒化膜が形成された下基板と、透明電極が形成さ
れた上基板と、これらの間に挟まれた液晶層とを有する
アクティブマトリックス液晶ディスプレイの製造方法に
おいて、前記下基板の反りが最小になるように、成膜条
件を調節し、前記表面保護膜となるシリコン窒化膜を形
成するようにしたものである。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a substrate in which a plurality of thin film transistors connected in a matrix are formed, and a silicon nitride film serving as a surface protection film is formed thereon. In a method for manufacturing an active matrix liquid crystal display having a substrate, an upper substrate on which a transparent electrode is formed, and a liquid crystal layer sandwiched between these, film forming conditions are set so that warpage of the lower substrate is minimized. The silicon nitride film serving as the surface protection film is formed by adjusting the temperature.
【0016】[0016]
【作用】本発明は、上記したように、アクティブマトリ
ックス液晶ディスプレイの下基板の製造方法において、
表面保護膜であるシリコン窒化膜を形成するとき、成膜
条件を調節し、保護膜の内部応力の方向及び大きさを制
御し、保護膜の応力と保護膜が形成されるまで下基板の
応力とが打ち消し合うようにして成膜する。[Operation] As described above, the present invention provides a method for manufacturing a lower substrate of an active matrix liquid crystal display.
When forming a silicon nitride film, which is a surface protective film, the film forming conditions are adjusted to control the direction and magnitude of the internal stress of the protective film, and the stress of the protective film and the stress of the lower substrate are adjusted until the protective film is formed. The film is formed so that the two cancel each other out.
【0017】[0017]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例を示すア
クティブマトリックス液晶ディスプレイの下基板の製造
工程断面図である。まず、その下基板のゲート電極形成
から透明電極形成までは従来と同様の技術を用いる。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a manufacturing process of a lower substrate of an active matrix liquid crystal display according to an embodiment of the present invention. First, the same techniques as in the prior art are used from the formation of the gate electrode to the formation of the transparent electrode on the lower substrate.
【0018】即ち、図1(a)に示すように、まずAM
LCDの下基板となるα−SiTFT基板は、第1透明
絶縁基板31の上に、クロム(Cr)、タンタル(Ta
)、モリブデン(Mo)、アルミニウム(Al)よりな
る金属層を、スパッタ、または蒸着により0.1〜0.
3μm程度成膜し、その後ホトリソエッチングにより所
定の形状に加工することでゲート電極32を形成する。
そして、陽極酸化法で第1ゲート絶縁膜となるゲート金
属の酸化膜33を0.1〜0.5μm形成する。その後
、NH3 ,SiH4 ガスを主成分とするプラズマC
VD(PCVD)法により、第2ゲート絶縁膜となるシ
リコン窒化膜(SiNx )34を膜厚0.1〜0.4
μm、SiH4 ガスを主成分とするPCVD法により
、アモルファスシリコン(n− −α−Si)膜を膜厚
0.05μm〜0.2μm、SiH4 ガスとPH3
ガスを主成分とするPCVD法により、n+ −α−S
i層を0.01〜0.1μmそれぞれ基板全面に堆積さ
せる。次に、アルミニウム(Al),クロム(Cr),
ニクロム(NiCr)などよりなる金属層を、スパッタ
、または蒸着により0.3〜1.0μm程度成膜し、そ
れを所定の形状に加工することにより、ソース電極37
及びドレイン電極38を形成する。そして、ホトリソと
反応性イオンエッチングにより、α−Si半導体層35
,36を所定の島形状に形成する。その後、半導体層3
5上のチャンネル部分の不要オーミック層36をCF4
とO2 を主成分とするドライエッチングにより除去
する。その後、PCVD法により、シリコン窒化膜(S
iNx )などからなる中間絶縁膜39を形成する。そ
の後、ソースと次に形成する透明電極ITO膜との導通
のためのコンタクトホール40を中間絶縁膜の所定部分
に形成し、ITO(In2 O3 +SnO2 )膜を
、スパッタ、または蒸着により0.1μm程度成膜し、
それを所定の形状に加工することで表示用電極となる透
明電極41を形成する。That is, as shown in FIG. 1(a), first, the AM
The α-SiTFT substrate, which becomes the lower substrate of the LCD, is made of chromium (Cr), tantalum (Ta) on the first transparent insulating substrate 31.
), molybdenum (Mo), and aluminum (Al) by sputtering or vapor deposition.
The gate electrode 32 is formed by forming a film with a thickness of about 3 μm and then processing it into a predetermined shape by photolithography etching. Then, a gate metal oxide film 33, which will become a first gate insulating film, is formed to a thickness of 0.1 to 0.5 μm by an anodic oxidation method. After that, plasma C containing NH3 and SiH4 gas as main components
A silicon nitride film (SiNx) 34, which will become the second gate insulating film, is formed to a thickness of 0.1 to 0.4 by VD (PCVD) method.
An amorphous silicon (n--α-Si) film is formed with a thickness of 0.05 μm to 0.2 μm by PCVD method using SiH4 gas as the main component, and SiH4 gas and PH3
By PCVD method using gas as the main component, n+ -α-S
The i-layer is deposited to a thickness of 0.01 to 0.1 μm over the entire surface of the substrate. Next, aluminum (Al), chromium (Cr),
The source electrode 37 is formed by forming a metal layer made of nichrome (NiCr) or the like to a thickness of about 0.3 to 1.0 μm by sputtering or vapor deposition, and processing it into a predetermined shape.
and a drain electrode 38 is formed. Then, by photolithography and reactive ion etching, the α-Si semiconductor layer 35 is
, 36 are formed into a predetermined island shape. After that, the semiconductor layer 3
Unnecessary ohmic layer 36 in the channel part on 5 is replaced with CF4
and O2 as the main components. After that, a silicon nitride film (S
An intermediate insulating film 39 made of, for example, iNx is formed. After that, a contact hole 40 for electrical connection between the source and the transparent electrode ITO film to be formed next is formed in a predetermined part of the intermediate insulating film, and an ITO (In2O3 +SnO2) film is deposited to a thickness of about 0.1 μm by sputtering or vapor deposition. Form a film,
By processing it into a predetermined shape, a transparent electrode 41 that becomes a display electrode is formed.
【0019】次に、下基板の反りを検査し、それぞれ基
板の反りを把握する。表面保護膜を形成するとき、成膜
条件を調節することによって、保護膜の内部応力の方向
及び大きさを制御して保護膜の応力と保護膜を形成する
までの下基板の応力とが打ち消し合うようにする。即ち
、下基板が凸(凹)になる場合、図1(b)に示すよう
に、保護膜の内部応力を引張(圧縮)応力になるように
表面保護膜としてのシリコン窒化膜42を形成する。Next, the lower substrate is inspected for warpage, and the warpage of each board is determined. When forming a surface protective film, by adjusting the film forming conditions, the direction and magnitude of the internal stress of the protective film can be controlled to cancel out the stress of the protective film and the stress of the lower substrate until the protective film is formed. make it fit. That is, when the lower substrate is convex (concave), the silicon nitride film 42 as a surface protective film is formed so that the internal stress of the protective film becomes tensile (compressive) stress, as shown in FIG. 1(b). .
【0020】ここで、成膜法については、原料ガスとし
てSiH4 、NH3 、N2 、H2 の4種類の混
合ガスを用いた13.56MHzの平行平板型高周波プ
ラズマCVD法で行う。具体的な成膜条件として、Si
H4 、NH3 、N2 、H2 の流量はそれぞれ1
0〜100sccm、30〜500sccm、0〜60
0sccm、0〜600sccmに、高周波パワーは1
00〜600Wに、成膜圧力は0.1〜2torrに、
電極間距離は30〜200mmに、基板温度は200〜
600℃になるように調節すれば、SiNx は略スト
イキオメトリックな組成(N/Si〜1.3、密度〜2
.8g/cm3 )で、内部応力が引張から圧縮まで、
膜組成や光学バンドギャップの変化と独立させて自由に
制御することができる。また、膜の内部応力の大きさが
、成膜時間を調節することによっても変えられる。[0020] Here, the film formation method is performed by a 13.56 MHz parallel plate type high frequency plasma CVD method using a mixed gas of four types of SiH4, NH3, N2, and H2 as raw material gases. As specific film forming conditions, Si
The flow rates of H4, NH3, N2, and H2 are each 1
0~100sccm, 30~500sccm, 0~60
0sccm, 0 to 600sccm, high frequency power is 1
00 to 600 W, film forming pressure to 0.1 to 2 torr,
The distance between the electrodes is 30-200mm, and the substrate temperature is 200-200mm.
If the temperature is adjusted to 600°C, SiNx has a nearly stoichiometric composition (N/Si ~1.3, density ~2
.. 8g/cm3), the internal stress ranges from tension to compression,
It can be freely controlled independently of changes in film composition and optical bandgap. Furthermore, the magnitude of the internal stress of the film can also be changed by adjusting the film formation time.
【0021】成膜条件と保護膜の内部応力の相関関係の
例として、図2に、高周波パワーと膜の内部応力との相
関関係を示している。高周波パワーを100Wから50
0Wまで変化させた場合、膜の内部応力は引張応力(+
4dynes/cm2 )から圧縮応力(−4dyne
s/cm2 )まで連続的に変化している。この時、高
周波パワー以外の成膜条件として、SiH4 、NH3
、N2 、H2 の流量はそれぞれ20sccm、8
0sccm、100sccm、100sccm、成膜圧
力は1.0torr、電極間距離は100mm、基板温
度は300℃である。As an example of the correlation between the film forming conditions and the internal stress of the protective film, FIG. 2 shows the correlation between the high frequency power and the internal stress of the film. High frequency power from 100W to 50
When the internal stress of the film is changed to 0W, the tensile stress (+
4dynes/cm2) to compressive stress (-4dynes/cm2)
s/cm2). At this time, as the film forming conditions other than high frequency power, SiH4, NH3
, N2, and H2 flow rates were 20 sccm and 8 sccm, respectively.
0 sccm, 100 sccm, 100 sccm, the film forming pressure was 1.0 torr, the distance between the electrodes was 100 mm, and the substrate temperature was 300°C.
【0022】次に、このTFTアレイ基板上に、図1(
c)に示すように、膜厚0.1μmのポリイミドよりな
る有機膜を形成し、ラビング処理することで、配向処理
膜43を形成する。なお、上記したTFTはアモルファ
スシリコンTFT、多結晶シリコンTFT、CdSeT
FT等の薄膜トランジスタならば材料を問わないもので
ある。Next, on this TFT array substrate, a pattern shown in FIG.
As shown in c), an organic film made of polyimide having a thickness of 0.1 μm is formed and rubbed, thereby forming an alignment film 43. Note that the above-mentioned TFTs include amorphous silicon TFTs, polycrystalline silicon TFTs, and CdSeT.
Any material can be used for thin film transistors such as FT.
【0023】また、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。Furthermore, the present invention is not limited to the above embodiments, but various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【0024】[0024]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、薄膜トランジスタを用いたアクティブマトリッ
クス液晶ディスプレイの保護膜としてのシリコン窒化膜
の成膜条件を適切に調節することによって、下基板の反
りが最小となるようにすることができる。As described above in detail, according to the present invention, by appropriately adjusting the film forming conditions of a silicon nitride film as a protective film of an active matrix liquid crystal display using thin film transistors, The warpage can be minimized.
【0025】従って、大面積の画面を有するアクティブ
マトリックス液晶ディスプレイであっても画面内の液晶
層の厚さの均一化が容易である。よって、色ムラがなく
応答速度のバラツキがない優れた表示品質を得ることが
できる。Therefore, even in an active matrix liquid crystal display having a large screen area, it is easy to make the thickness of the liquid crystal layer within the screen uniform. Therefore, it is possible to obtain excellent display quality with no color unevenness and no variation in response speed.
【図1】本発明の実施例を示すアクティブマトリックス
液晶ディスプレイの下基板の要部製造工程断面図である
。FIG. 1 is a cross-sectional view showing a manufacturing process of a main part of a lower substrate of an active matrix liquid crystal display according to an embodiment of the present invention.
【図2】本発明の実施例を示すアクティブマトリックス
液晶ディスプレイの表面保護膜の形成時の高周波パワー
と膜の内部応力との相関関係を示図である。FIG. 2 is a diagram showing the correlation between high frequency power and internal stress of the film during formation of a surface protective film of an active matrix liquid crystal display according to an embodiment of the present invention.
【図3】従来のアクティブマトリックス液晶ディスプレ
イ(AMLCD)の構造を示す断面図である。FIG. 3 is a cross-sectional view showing the structure of a conventional active matrix liquid crystal display (AMLCD).
【図4】SiOx 膜、SiNx 膜のひずみによる基
板のたわみを示す図である。FIG. 4 is a diagram showing the deflection of the substrate due to the strain of the SiOx film and the SiNx film.
31 第1透明絶縁基板
32 ゲート電極
33 ゲート金属の酸化膜
34 シリコン窒化膜(SiNx )35,36
α−Si半導体層
37 ソース電極
38 ドレイン電極
39 中間絶縁膜
40 コンタクトホール
41 透明電極
42 表面保護膜(シリコン窒化膜)43
配向処理膜31 First transparent insulating substrate 32 Gate electrode 33 Gate metal oxide film 34 Silicon nitride film (SiNx) 35, 36
α-Si semiconductor layer 37 Source electrode 38 Drain electrode 39 Intermediate insulating film 40 Contact hole 41 Transparent electrode 42 Surface protection film (silicon nitride film) 43
Orientation treatment film
Claims (3)
膜トランジスタが形成され、その上に表面保護膜となる
シリコン窒化膜が形成された下基板と、透明電極が形成
された上基板と、これらの間に挟まれた液晶層とを有す
るアクティブマトリックス液晶ディスプレイの製造方法
において、前記下基板の反りが最小になるように、成膜
条件を調節し、前記表面保護膜となるシリコン窒化膜を
形成することを特徴とするアクティブマトリックス液晶
ディスプレイの製造方法。1. A lower substrate on which a plurality of thin film transistors connected in a matrix are formed, a silicon nitride film serving as a surface protection film is formed thereon, an upper substrate on which a transparent electrode is formed, and a space between these. In the method of manufacturing an active matrix liquid crystal display having a liquid crystal layer sandwiched between the silicon nitride film and the silicon nitride film, the silicon nitride film serving as the surface protection film is formed by adjusting the film forming conditions so that the warpage of the lower substrate is minimized. A method for manufacturing an active matrix liquid crystal display characterized by:
法で成膜されたものであることを特徴とする請求項1記
載のアクティブマトリックス液晶ディスプレイの製造方
法。2. The silicon nitride film is formed by plasma CVD.
2. The method of manufacturing an active matrix liquid crystal display according to claim 1, wherein the active matrix liquid crystal display is formed by a method.
法で成膜され、成膜条件として、SiH4 、NH3
、N2 、H2 の流量はそれぞれ10〜100scc
m、30〜500sccm、0〜600sccm、0〜
600sccmに、基板温度は200〜600℃に、高
周波パワーは100〜600Wに、成膜圧力は0.1〜
2torrに、電極間距離は30〜200mmになるよ
うに調節したことを特徴とする請求項1記載のアクティ
ブマトリックス液晶ディスプレイの製造方法。3. The silicon nitride film is formed by plasma CVD.
The film was formed using SiH4, NH3 as the film forming conditions.
, N2, and H2 flow rates are each 10 to 100 scc.
m, 30-500sccm, 0-600sccm, 0-
600sccm, substrate temperature 200~600℃, high frequency power 100~600W, and film forming pressure 0.1~600°C.
2. The method of manufacturing an active matrix liquid crystal display according to claim 1, wherein the distance between the electrodes is adjusted to 2 torr and the distance between the electrodes to be 30 to 200 mm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3068668A JPH04304428A (en) | 1991-04-02 | 1991-04-02 | Manufacture of active matrix liquid crystal display |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3068668A JPH04304428A (en) | 1991-04-02 | 1991-04-02 | Manufacture of active matrix liquid crystal display |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04304428A true JPH04304428A (en) | 1992-10-27 |
Family
ID=13380324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3068668A Withdrawn JPH04304428A (en) | 1991-04-02 | 1991-04-02 | Manufacture of active matrix liquid crystal display |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04304428A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004133109A (en) * | 2002-10-09 | 2004-04-30 | Seiko Epson Corp | Method for manufacturing substrate having thin film formed thereon, method for manufacturing electrooptical device, electrooptical device, and electronic appliance |
JP2007511786A (en) * | 2003-10-27 | 2007-05-10 | イー インク コーポレイション | Electro-optic display |
CN100433115C (en) * | 2002-02-07 | 2008-11-12 | Nec液晶技术株式会社 | Liquid crystal display equipment capable of effectively preventing irregularity of color |
US8969886B2 (en) | 2002-04-24 | 2015-03-03 | E Ink Corporation | Electro-optic displays having backplanes comprising ring diodes |
-
1991
- 1991-04-02 JP JP3068668A patent/JPH04304428A/en not_active Withdrawn
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100433115C (en) * | 2002-02-07 | 2008-11-12 | Nec液晶技术株式会社 | Liquid crystal display equipment capable of effectively preventing irregularity of color |
US8969886B2 (en) | 2002-04-24 | 2015-03-03 | E Ink Corporation | Electro-optic displays having backplanes comprising ring diodes |
US9419024B2 (en) | 2002-04-24 | 2016-08-16 | E Ink Corporation | Methods for forming patterned semiconductors |
US9632389B2 (en) | 2002-04-24 | 2017-04-25 | E Ink Corporation | Backplane for electro-optic display |
JP2004133109A (en) * | 2002-10-09 | 2004-04-30 | Seiko Epson Corp | Method for manufacturing substrate having thin film formed thereon, method for manufacturing electrooptical device, electrooptical device, and electronic appliance |
JP2007511786A (en) * | 2003-10-27 | 2007-05-10 | イー インク コーポレイション | Electro-optic display |
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