JPH04303923A - Method of forming selectively grown, buried semiconductor - Google Patents

Method of forming selectively grown, buried semiconductor

Info

Publication number
JPH04303923A
JPH04303923A JP9334991A JP9334991A JPH04303923A JP H04303923 A JPH04303923 A JP H04303923A JP 9334991 A JP9334991 A JP 9334991A JP 9334991 A JP9334991 A JP 9334991A JP H04303923 A JPH04303923 A JP H04303923A
Authority
JP
Japan
Prior art keywords
silicon oxide
oxide film
sio2
sinx
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9334991A
Other languages
Japanese (ja)
Inventor
Nobukazu Takado
高堂 宣和
Yuichi Ide
雄一 井手
Naotaka Kuroda
黒田 尚考
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9334991A priority Critical patent/JPH04303923A/en
Publication of JPH04303923A publication Critical patent/JPH04303923A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide a title method whose fineness degree is sufficient for manifesting a quantum effect and which does not cause damage in a processing operation. CONSTITUTION:A silicon oxide film 14 haivng a thickness of 300Angstrom is formed, by an electron beam vapor deposition method, on the surface of a GaAs substrate 11 on which an AlGaAs layer 12 having a thcikness of 2mum and a GaAs cap layer 13 having a thickness of 300Angstrom have been laminated. Then, while xenon fluoride gas 17 is being supplied, the silicon oxide film 14 is irradiated with a focused ion beam 16. Thereby, an opening part 18 can be formed. Then, when a showerlike electron beam 19 is irradiated through the opening part in the atmosphere of chlorine, the surface of the GaAs substrate directly under the opening part 18 is etched efficiently. GaAs 22 can be buried and selectively grown in an etched part 21 formed in this manner by using a metal organic vapor growth apparatus and, in addition, by making use of the silicon oxide film (SiO2) 14 as a mask in a selective growth operation.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体基板への選択埋
め込み結晶成長法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for selectively implanting crystal growth in a semiconductor substrate.

【0002】0002

【従来の技術】半導体基板での選択埋め込み結晶成長、
例えばGaAs基板でのAlGaAsの選択埋め込み結
晶成長等は光・電子素子の集積化技術として期待されて
いる。この選択埋め込み成長の従来技術としては、減圧
有機金属気相成長法(MOVPE)を用いてGaAs基
板にAlGaAsの選択埋め込み成長を行う方法が応用
物理学会結晶工学分科会第2回結晶工学シンポジウム、
1985年7月予稿集に掲載の香門浩一らによる文献「
減圧OMVPEによるGaAs,AlGaAsの選択成
長」に述べられている。
[Prior Art] Selective buried crystal growth on a semiconductor substrate;
For example, selective buried crystal growth of AlGaAs on a GaAs substrate is expected to be a technology for integrating opto-electronic devices. As a conventional technique for this selective implantation growth, there is a method of selectively implanting AlGaAs onto a GaAs substrate using low pressure metal organic vapor phase epitaxy (MOVPE).
A document by Koichi Komon et al. published in the July 1985 Proceedings “
"Selective growth of GaAs and AlGaAs by low pressure OMVPE".

【0003】この文献によれば、選択マスクとしてSi
Nx膜をプラズマCVDによりGaAs基板上に約10
00Å堆積させて用いる。次にフォトリソグラフィによ
り5〜10μm幅のストライプ状のパターンをSiNx
膜に形成し、さらに4H2 SO4 :H2 O2 :
H2 O溶液中でエッチングし深さ5μmの溝を形成す
る。成長装置は、抵抗加熱方式の縦型反応炉であり、原
料にはトリメチルアルミニウム(TMA)、トリメチル
ガリウム(TMG)、AsH3 を使用する。成長は、
圧力0.1〜10Torr、基板温度650〜770℃
、全流量300〜500sccmの範囲で行っている。
According to this document, Si is used as a selection mask.
A Nx film is deposited on a GaAs substrate by plasma CVD for approximately 10
It is used by depositing 00 Å. Next, a striped pattern with a width of 5 to 10 μm was formed on the SiNx by photolithography.
Formed into a film and further 4H2 SO4 :H2 O2 :
A groove with a depth of 5 μm is formed by etching in H2O solution. The growth apparatus is a resistance heating type vertical reactor, and trimethylaluminum (TMA), trimethylgallium (TMG), and AsH3 are used as raw materials. The growth is
Pressure 0.1-10 Torr, substrate temperature 650-770°C
, at a total flow rate of 300 to 500 sccm.

【0004】0004

【発明が解決しようとする課題】近年加工の微細化が進
み1000Å以下の加工寸法が実現されてきているが、
この加工寸法は量子効果が期待される領域である。した
がって1000Å以下のパターンで埋め込み選択成長を
行えば量子細線や量子箱が実現できる。しかし上記の埋
め込み選択成長で半導体基板をウェットエッチングして
いるため微細化が困難である。またSiNx膜と半導体
基板のエッチングをドライエッチングに変更した場合で
も、SiNx膜上のレジスト層を電子ビームリソグラフ
ィ等によりパターニングし、これをマスクとしてSiN
x膜をドライエッチングして微細パターンを転写し、さ
らにSiNx膜をマスクとしてGaAs基板をドライエ
ッチングして微細パターンを転写する必要がある。しか
しこのような方法では1000Å以下の微細パターンを
2回も精度よく転写することが実際上困難である。
[Problem to be solved by the invention] In recent years, processing has become finer and processing dimensions of 1000 Å or less have been realized.
This processing dimension is an area in which quantum effects are expected. Therefore, quantum wires and quantum boxes can be realized by performing embedded selective growth with a pattern of 1000 Å or less. However, since the semiconductor substrate is wet-etched in the buried selective growth described above, miniaturization is difficult. Furthermore, even if the etching of the SiNx film and semiconductor substrate is changed to dry etching, the resist layer on the SiNx film is patterned by electron beam lithography, etc., and this is used as a mask to
It is necessary to dry-etch the x film to transfer the fine pattern, and then dry-etch the GaAs substrate using the SiNx film as a mask to transfer the fine pattern. However, with this method, it is actually difficult to accurately transfer a fine pattern of 1000 Å or less twice.

【0005】本発明の目的は、量子効果を顕在化させる
に十分な微細度を有し、かつ加工ダメージがない埋め込
み選択成長方法を提供することにある。
[0005] An object of the present invention is to provide a buried selective growth method that has sufficient fineness to make quantum effects apparent and is free from processing damage.

【0006】[0006]

【課題を解決するための手段】本発明による半導体の埋
め込み選択成長法は、III−V族化合物半導体基板上
への半導体の埋め込み選択成長法において、III−V
族化合物半導体基板表面上にシリコン酸化膜(SiO2
 )またはシリコン窒化膜(SiNx)を形成する工程
と、このシリコン酸化膜(SiO2 )またはシリコン
窒化膜(SiNx)にフッ素原子を含む反応性ガス又は
ラジカル雰囲気中でマスクレスエッチングを施す工程と
、前記シリコン酸化膜(SiO2 )またはシリコン窒
化膜(SiNx)をマスクにしてハロゲン原子を含む反
応性ガス又はラジカル雰囲気中で前記化合物半導体基板
を選択的にドライエッチングする工程と、前記シリコン
酸化膜(SiO2 )またはシリコン窒化膜(SiNx
)をマスクとして前記化合物半導体基板をエッチングし
た部分に半導体の埋め込み選択成長法を行う工程とを含
むことを特徴とする。
[Means for Solving the Problems] The buried selective growth method of a semiconductor according to the present invention is a method of buried selective growth of a semiconductor on a III-V group compound semiconductor substrate.
A silicon oxide film (SiO2
) or a silicon nitride film (SiNx); a step of performing maskless etching on the silicon oxide film (SiO2) or silicon nitride film (SiNx) in a reactive gas or radical atmosphere containing fluorine atoms; selectively dry etching the compound semiconductor substrate in a reactive gas or radical atmosphere containing halogen atoms using a silicon oxide film (SiO2) or silicon nitride film (SiNx) as a mask; or silicon nitride film (SiNx
) is used as a mask to perform a buried selective growth method of a semiconductor on the etched portion of the compound semiconductor substrate.

【0007】[0007]

【作用】本発明では、III−V族化合物半導体基板表
面上のシリコン酸化膜(SiO2 )またはシリコン窒
化膜(SiNx)をフッ素原子を含む反応性ガス又はラ
ジカル雰囲気中でマスクレスエッチングして微細パター
ンを形成し、さらにパターン化されたこのシリコン酸化
膜(SiO2 )またはシリコン窒化膜(SiNx)を
化合物半導体のドライエッチングと埋め込み選択成長の
両方のマスクとして用いることにより簡単な工程で微細
領域の埋め込み選択成長を実現することができる。
[Operation] In the present invention, a silicon oxide film (SiO2) or a silicon nitride film (SiNx) on the surface of a III-V compound semiconductor substrate is etched into a fine pattern by maskless etching in a reactive gas or radical atmosphere containing fluorine atoms. By using this patterned silicon oxide film (SiO2) or silicon nitride film (SiNx) as a mask for both dry etching and selective buried growth of compound semiconductors, it is possible to selectively fill fine areas in a simple process. Growth can be achieved.

【0008】[0008]

【実施例】以下、本発明の実施例を工程ごとの断面図に
より図1に示す。図1(a)に示すようにGaAs基板
上の2μm厚のAlGaAs層12さらに300Å厚の
GaAsキャップ層13を積層したGaAs基板11の
表面に300Å厚のシリコン酸化膜(SiO2 )14
を電子ビーム蒸着法により設ける。次に同図(b)に示
すようにガス圧1mTorrのフッ化ゼノン(XeF2
 )ガス17を供給しながら5KeVの集束電子ビーム
16をシリコン酸化膜(SiO2 )14に照射するこ
とにより、シリコン酸化膜(SiO2 )14はドライ
エッチングされ微細な開口部18を形成できる。次に同
図(c)に示すようにガス圧5X10−4Torrの塩
素雰囲気中で100eVのシャワー状電子ビーム19を
図1(b)で形成したシリコン酸化膜(SiO2 )1
4の開口部18を通してGaAs基板表面に照射するこ
とによりシリコン酸化膜(SiO2 )14の開口部1
8の直下のGaAs基板表面上で塩素ガスとGaAsま
たはAlGaAsとの化学反応が電子ビームにより引き
起され効率的エッチングが行われる。このようにして形
成したエッチング部分21に同図(b),(c)の加工
を行った電子ビームエッチング装置と真空を介して結合
された有機金属気相成長装置を用いさらに同図(b)で
形成した開口部18を有するシリコン酸化膜(SiO2
 )14を選択成長時のマスクとすることにより、同図
(d)に示すような、GaAs22の埋め込み選択成長
が可能となる。この時の有機金属気相成長はトリメチル
ガリウム(TMC),AsH3 を原料とし、圧力0.
01Torr、基板温度650〜770℃、全流量30
sccmで行った。
[Embodiment] An embodiment of the present invention will be shown in FIG. 1 with cross-sectional views showing each step. As shown in FIG. 1(a), a 300 Å thick silicon oxide (SiO2) film 14 is formed on the surface of a GaAs substrate 11 on which a 2 μm thick AlGaAs layer 12 is further laminated with a 300 Å thick GaAs cap layer 13.
is provided by electron beam evaporation. Next, as shown in the same figure (b), xenon fluoride (XeF2
) By irradiating the silicon oxide film (SiO2) 14 with a 5 KeV focused electron beam 16 while supplying a gas 17, the silicon oxide film (SiO2) 14 is dry etched and a fine opening 18 can be formed. Next, as shown in FIG. 1(c), a shower-like electron beam 19 of 100 eV is applied to the silicon oxide film (SiO2) 1 formed in FIG.
By irradiating the GaAs substrate surface through the opening 18 of 4, the opening 1 of the silicon oxide film (SiO2) 14 is exposed.
A chemical reaction between the chlorine gas and GaAs or AlGaAs is caused by the electron beam on the surface of the GaAs substrate immediately below the surface of the substrate 8, resulting in efficient etching. The etched portion 21 formed in this way was processed using an electron beam etching device as shown in FIGS. 2(b) and 3(c) and an organometallic vapor phase epitaxy device connected via vacuum. A silicon oxide film (SiO2
) 14 as a mask during selective growth, it becomes possible to selectively grow GaAs 22 by embedding it as shown in FIG. 2(d). In this metal organic vapor phase growth, trimethyl gallium (TMC) and AsH3 are used as raw materials, and the pressure is 0.
01Torr, substrate temperature 650-770℃, total flow rate 30
I went with sccm.

【0009】以上に説明した実施例では、シリコン酸化
膜(SiO2)12の加工に集束電子ビームを用いたが
、代わりに集束イオンビームを用いても同様の加工が可
能である。またGaAs基板11の加工には、かならず
しもシャワー状電子ビームを用いる必要はなくパターニ
ングされたシリコン酸化膜(SiO2 )12をマスク
として反応性のシャワーイオンビームまたはラジカルビ
ーム例えば塩素の反応性イオンビームエッチング(RI
BE)によりGaAs基板を加工してもよい。但しGa
As基板の加工にシャワーイオンビームを用いた場合に
は加工表面にダメージ層が残るため、基板温度200℃
以上で塩素ラジカルビームを照射する等してダメージ層
を除去することが必要となる。
In the embodiment described above, a focused electron beam is used to process the silicon oxide film (SiO2) 12, but the same process can be performed by using a focused ion beam instead. Furthermore, in processing the GaAs substrate 11, it is not always necessary to use a shower electron beam; instead, a reactive shower ion beam or a radical beam, such as chlorine reactive ion beam etching ( R.I.
A GaAs substrate may be processed by BE). However, Ga
When a shower ion beam is used to process an As substrate, a damaged layer remains on the processed surface, so the substrate temperature is 200°C.
In the above process, it is necessary to remove the damaged layer by irradiating with a chlorine radical beam or the like.

【0010】また本実施例ではGaAsの結晶成長を示
したが、本発明は他の半導体、例えばGaP、InPな
どに適用可能であり、結晶成長法としては有機金属気相
成長法の例を示したが、その他の選択成長可能な結晶成
長法、例えばクロライド気相成長法、原子層エピタキシ
ャル成長などでも適用できる。シリコン酸化膜(SiO
2 )の代わりにシリコン窒化膜(SiNx)でも、本
発明の効果が得られる。
[0010]Although this example shows the crystal growth of GaAs, the present invention can be applied to other semiconductors, such as GaP and InP. However, other crystal growth methods that allow selective growth, such as chloride vapor phase epitaxy and atomic layer epitaxial growth, can also be applied. Silicon oxide film (SiO
The effects of the present invention can also be obtained by using a silicon nitride film (SiNx) instead of 2).

【0011】[0011]

【発明の効果】本発明によれば、シリコン酸化膜(Si
O2 )またはシリコン窒化膜(SiNx)を用いるこ
とによりフッ素原子を含む反応性ガス又はラジカル雰囲
気中でマスクレスエッチングすることができ、またこの
シリコン酸化膜(SiO2 )またはシリコン窒化膜(
SiNx)はハロゲン原子を含む反応性ガス又はラジカ
ル雰囲気中での化合物半導体のドライエッチングのマス
クともなる。従ってパターン化されたこのシリコン酸化
膜(SiO2 )またはシリコン窒化膜(SiNx)を
化合物半導体のドライエッチングと埋め込み選択成長の
両方のマスクとして用いることかがきるため構成が簡単
で精度のよい加工・埋め込み選択成長が可能となる。
According to the present invention, silicon oxide film (Si
Maskless etching can be performed in a reactive gas or radical atmosphere containing fluorine atoms by using a silicon oxide film (SiO2) or a silicon nitride film (SiNx).
SiNx) also serves as a mask for dry etching of compound semiconductors in a reactive gas or radical atmosphere containing halogen atoms. Therefore, it is possible to use this patterned silicon oxide film (SiO2) or silicon nitride film (SiNx) as a mask for both dry etching and selective implantation growth of compound semiconductors, resulting in a simple structure and accurate processing and implantation. Selective growth becomes possible.

【0012】また本発明は、レジストマスクのフォトリ
ソグラフィに伴う現像液によるウェット処理を必要とし
ないのでマスクレスエッチングから埋め込み選択成長ま
で真空一貫プロセスで行うことができ、特に化合物半導
体には表面の大気からの汚染を回避でき有効である。
Furthermore, since the present invention does not require wet processing using a developer accompanying photolithography of a resist mask, it can be performed in a vacuum integrated process from maskless etching to buried selective growth. It is effective in avoiding contamination from

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の第一の実施例の工程を説明する断面図
である。
FIG. 1 is a sectional view illustrating the steps of a first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11    GaAs基板 12    AlGaAs層 13    GaAsキャップ層 14    シリコン酸化膜(SiO2 )15   
 フィラメント 16    集束電子ビーム 17    フッ化ゼノン(XeF2 )ガス18  
  開口部 19    シャワー状電子ビーム 20    塩素(Cl2 )ガス 21    エッチング部分 22    GaAs領域
11 GaAs substrate 12 AlGaAs layer 13 GaAs cap layer 14 Silicon oxide film (SiO2) 15
Filament 16 Focused electron beam 17 Zenon fluoride (XeF2) gas 18
Opening 19 Shower electron beam 20 Chlorine (Cl2) gas 21 Etched portion 22 GaAs region

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  III−V族化合物半導体基板上への
半導体の埋め込み選択成長法において、III−V族化
合物半導体基板表面上にシリコン酸化膜(SiO2 )
またはシリコン窒化膜(SiNx)を形成する工程と、
このシリコン酸化膜(SiO2 )またはシリコン窒化
膜(SiNx)にフッ素原子を含む反応性ガス又はラジ
カル雰囲気中でマスクレスエッチングを施す工程と、前
記シリコン酸化膜(SiO2 )またはシリコン窒化膜
(SiNx)をマスクにしてハロゲン原子を含む反応性
ガス又はラジカル雰囲気中で前記化合物半導体基板を選
択的にドライエッチングする工程と、前記シリコン酸化
膜(SiO2 )またはシリコン窒化膜(SiNx)を
マスクとして前記化合物半導体基板をエッチングした部
分に半導体の埋め込み選択成長を行う工程とを含むこと
を特徴とする半導体の埋め込み選択成長法。
[Claim 1] In a method for selectively growing a semiconductor on a III-V compound semiconductor substrate, a silicon oxide film (SiO2) is deposited on the surface of the III-V compound semiconductor substrate.
Or a step of forming a silicon nitride film (SiNx);
A step of performing maskless etching on this silicon oxide film (SiO2) or silicon nitride film (SiNx) in a reactive gas or radical atmosphere containing fluorine atoms; selectively dry etching the compound semiconductor substrate in a reactive gas or radical atmosphere containing halogen atoms using the silicon oxide film (SiO2) or silicon nitride film (SiNx) as a mask; 1. A method for selectively growing a semiconductor by selectively growing a semiconductor in an etched portion.
【請求項2】  マスクレスエッチングは、フッ素原子
を含む反応性ガス又はラジカル雰囲気中で集束電子ビー
ム又は集束イオンビームなどの集束エネルギービームを
シリコン酸化膜(SiO2 )またはシリコン窒化膜(
SiNx)表面に照射して行う請求項1に記載の半導体
の埋め込み選択成長法。
2. Maskless etching is a method of etching a silicon oxide (SiO2) or silicon nitride (SiO2) film using a focused energy beam such as a focused electron beam or a focused ion beam in a reactive gas or radical atmosphere containing fluorine atoms.
2. The buried selective growth method of a semiconductor according to claim 1, wherein the method is performed by irradiating the SiNx surface.
【請求項3】  ドライエッチングは、ハロゲン原子を
含む反応性ガス又はラジカル雰囲気中で電子ビーム又は
イオンビームなどのエネルギービームをIII−V族化
合物半導体基板表面に照射して行う請求項1に記載の半
導体の埋め込み選択成長法。
3. The dry etching according to claim 1, wherein the dry etching is performed by irradiating the surface of the III-V compound semiconductor substrate with an energy beam such as an electron beam or an ion beam in a reactive gas or radical atmosphere containing halogen atoms. Embedded selective growth method for semiconductors.
JP9334991A 1991-03-29 1991-03-29 Method of forming selectively grown, buried semiconductor Withdrawn JPH04303923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9334991A JPH04303923A (en) 1991-03-29 1991-03-29 Method of forming selectively grown, buried semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9334991A JPH04303923A (en) 1991-03-29 1991-03-29 Method of forming selectively grown, buried semiconductor

Publications (1)

Publication Number Publication Date
JPH04303923A true JPH04303923A (en) 1992-10-27

Family

ID=14079799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9334991A Withdrawn JPH04303923A (en) 1991-03-29 1991-03-29 Method of forming selectively grown, buried semiconductor

Country Status (1)

Country Link
JP (1) JPH04303923A (en)

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* Cited by examiner, † Cited by third party
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KR20040040902A (en) * 2002-11-08 2004-05-13 엘지전자 주식회사 Method for selectively removing GaN substrate using laser
JP2013527596A (en) * 2010-03-24 2013-06-27 ボード オブ トラスティーズ オブ ザ レランド スタンフォード ジュニア ユニバーシティ Irradiation-induced nucleation of quantum confinement structures by atomic layer deposition

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040040902A (en) * 2002-11-08 2004-05-13 엘지전자 주식회사 Method for selectively removing GaN substrate using laser
JP2013527596A (en) * 2010-03-24 2013-06-27 ボード オブ トラスティーズ オブ ザ レランド スタンフォード ジュニア ユニバーシティ Irradiation-induced nucleation of quantum confinement structures by atomic layer deposition

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