JPH04294621A - Limiter circuit - Google Patents

Abstract

PURPOSE:To suppress the dispersion in a limiting characteristic even when dispersion takes place in the matching state of transistor(TR) element input output by setting a bias point of the TR element in the vicinity of pinch-off. CONSTITUTION:When a microwave signal is fed to an input signal input terminal 12, a bias point moves on an AC load line periodically. As an input signal level increases, a drain current of a field effect TR (FET) 19 flows through a filter circuit 20 as a short-circuit current of a harmonic wave component of the input signal frequency. Thus, the matching state of the FET 11, for example, differs from each lot of a microwave monolithic circuit MMIC, since the DC component of the drain is large, the dispersion in the input signal level subject to limiting is suppressed, then the yield in the MMIC manufacture is improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a limiter circuit for limiting the amplitude of a transistor output.

0002

[Prior Art] Conventionally, microwave limiter circuits composed of active elements such as field effect transistors (hereinafter referred to as FETs), capacitors, inductors, etc. have been used to maintain an output signal at a constant level in response to fluctuations in the input signal level. It has a suppressing function and is an important component in radar communication systems.

FIG. 4 shows the configuration of a FET limiter circuit used in conventional microwave communication.

In FIG. 4, 11 is an F whose source is grounded.
ET, 12 is a microwave signal input terminal, 13 is a signal output terminal, 14 is an input matching circuit, and 15 is an output matching circuit. The drain voltage of the FET 11 is supplied from a bias supply terminal 16 via a drain resistor 17. A gate bias voltage is supplied from a bias supply terminal 18 via a gate resistor 19.

As shown in the FET static characteristic diagram of FIG. 5, the bias point P of the FET 11 is set so that it is near pinch-off and the drain-source voltage VDS is near the knee voltage. Here, when a microwave signal is applied to the signal input terminal 12, the bias point P moves periodically on the AC load line A, and as the input signal level increases, the drain current changes as shown in FIG. As shown, it changes in a form close to a square half-wave rectified wave.

Therefore, the DC component ID of the drain current
Assuming that the change in drain current is a square half-wave rectified wave, C2 is IDC2=I0/4

...(1). I0 is the maximum value of the current amplitude shown in FIG. At this time, since the bias point P of FET11 is near the pinch-off, IDC2>IDC0

...(2). IDC0 is a bias current when there is no signal.

On the other hand, since the drain bias voltage of the FET 11 is supplied through the drain resistor 17, the drain-source voltage VDS decreases by the increase in the DC component of the drain current. Therefore, the saturated output signal level of the FET 11 is suppressed, and the input signal level is limited. In other words, the limiting characteristics of the FET limiter circuit depend on the amount of increase in the DC component of the drain current.

However, in the conventional FET limiter circuit with the above configuration, a microwave monolithic circuit (MMI
In the case of configuration C), the bias point P of the FET is pinched.
Since it is set close to off, the element sensitivity to the FET parameters of the circuit is high, and the matching state of the FET 11 is M
It varies from lot to lot of MIC. This variation causes variation in the increase in the DC component of the drain current, and also causes variation in the input signal level to which the limiting is applied, as shown in Lots 1, 2, and 3, for example, as shown in FIG. Therefore, it is necessary to inspect whether the variations are within an allowable range, and this has been a cause of a decrease in yield in MMIC manufacturing.

[0009] Furthermore, in a FET limiter circuit constructed using a hybrid IC (HIC), differences in FET lots and assembly variations cause variations in the matching state of the FETs, so it is necessary to adjust the limiting characteristics. This has been a cause of a decrease in yield in HIC production.

Note that the above applies not only to FETs but also when ordinary transistors are used.

[0011]

[Problems to be Solved by the Invention] As described above, in conventional limiter circuits, the bias point of the transistor element is set near pinch-off, so the element sensitivity to circuit parameters is high, and in MMIC, it is To,
Furthermore, in HIC, the matching state of input and output of transistor elements differs due to the influence of assembly variations, etc., and this causes variations in limiting characteristics.

The present invention was made to solve the above problem, and the bias point of the transistor element is set near the pinch-off, so that even if there are variations in the matching state of the input and output of the transistor element, the limit can be maintained. An object of the present invention is to provide a limiter circuit that can suppress variations in timing characteristics.

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention connects the first controlled electrode of the transistor to ground, applies a bias voltage to the second controlled electrode via a resistor, and controls the transistor. A limiter circuit that limits the output amplitude of a second controlled electrode by limiting a bias current as an input signal supplied to the electrode increases, the limiter circuit being connected to the second controlled electrode and controlling the electrode. It is configured to include a filter circuit that creates a short-circuit state at a frequency that is an integer multiple of the electrode input frequency excluding the fundamental frequency.

[0014]

[Operation] In the limiter circuit having the above configuration, the second controlled electrode is short-circuited at a frequency that is an integral multiple of the control electrode input frequency excluding the fundamental frequency, and the amount of increase in the DC component of the second controlled electrode is reduced. By increasing the bias point of the transistor element near the pinch-off, even if variations occur in the matching state of the input and output of the transistor element,
Suppress variations in limiting characteristics.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. However, in FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals, and the different parts will be mainly explained here.

FIG. 1 shows its configuration, which is composed of MMIC. A filter circuit 18 is connected between the drain electrode of the FET 11 and the signal output terminal 13. This filter circuit 20 has a function of short-circuiting the drain electrode at a frequency that is an integral multiple of the source input signal frequency of the FET 11 excluding the fundamental frequency f. In reality, if a filter is formed taking into account up to the second and third harmonics 2f and 3f, it is sufficient to realize a short-circuit state for the harmonics. 3rd harmonic 2
This is realized by using open end stubs a and b so that the drain electrode is short-circuited to f and 3f. A is a stub for shorting the second harmonic, and b is a stub for shorting the third harmonic.

Note that FIG. 1 shows a case in which the input matching circuit 14 and the output matching circuit 15 are constructed using stubs c, d, e, and f, respectively.

The operation of the above configuration will be explained below with reference to FIGS. 2 and 3.

Now, when a microwave signal is supplied to the input signal input terminal 12, the bias point P shown in FIG. 5 moves periodically on the AC load line A. As the input signal level increases, the drain current of the FET 11 changes in a form close to a rectangular wave as shown in FIG. 2 because a short circuit current of a harmonic component of the input signal frequency f flows through the filter circuit 20.

Therefore, assuming that the drain current changes in a rectangular waveform, the DC component IDC1 of the drain current is IDC1=I0/π

...(3), IDC1>IDC2

...The relationship (4) is obtained.

Therefore, even if the matching state of the FET 11 differs from lot to lot of MMIC, the FET limiter circuit having the above configuration has a large direct current component of the drain current, so that, as shown in FIG. It is possible to suppress variations in the input signal level caused by limiting in units of 1, 2, and 3. As a result, the yield in MMIC manufacturing can be improved by about 10% or more.

[0022] In the above embodiment, the explanation has been made on the assumption that the change in the drain current is a rectangular wave, but this is only an odd-order harmonic component, and in reality, the DC component is an even-order harmonic component. As a result, the DC component of the drain current increases significantly. This makes it possible to further suppress variations in the limiting characteristics.

Further, although the above description has been made regarding the case where FETs are used, the present invention can also be applied to cases where ordinary transistors are used, and similar results can be obtained. Needless to say, the present invention is also applicable to a case configured with HIC.

[0024]

As described above, according to the present invention, even if the bias point of the transistor element is set near the pinch-off, and the matching state of the input and output of the transistor element varies, variations in the limiting characteristics can be prevented. It is possible to provide a limiter circuit that can suppress

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a limiter circuit using FETs as an embodiment of the limiter circuit according to the present invention.

FIG. 2 is a waveform diagram showing the drain current waveform of the same example.

FIG. 3 is a characteristic diagram showing the limiting characteristics for each lot when the FET limiter circuit of the same embodiment is configured with MMIC.

FIG. 4 is a circuit diagram showing the configuration of a conventional FET limiter circuit.

FIG. 5 is a characteristic diagram showing static characteristics of an FET.

FIG. 6 is a waveform diagram showing the drain current waveform of FIG. 4;

FIG. 7 is a characteristic diagram showing the limiting characteristics for each lot when the FET limiter circuit in FIG. 4 is configured with an MMIC.

[Explanation of symbols]

11...FET, 12...Microwave signal input terminal, 13...
Signal output terminal, 14...Input matching circuit, 15...Output matching circuit, 16...Drain bias supply terminal, 17...Drain resistance, 18...Gate bias supply terminal, 19...Gate resistance, 20...Filter circuit, a, b...Open end stub.

Claims (5)

[Claims] 1. A first controlled electrode of a transistor is grounded, a bias voltage is applied to a second controlled electrode via a resistor, and a bias current is increased as an input signal supplied to the control electrode increases. In a limiter circuit that limits the output amplitude of a second controlled electrode, the limiter circuit is connected to the second controlled electrode and controls the electrode at a frequency that is an integral multiple of the control electrode input frequency excluding the fundamental frequency. A limiter circuit that includes a filter circuit that creates a short-circuit condition. 2. The limiter circuit according to claim 1, wherein the limiter circuit is a microwave monolithic circuit. 3. The limiter circuit according to claim 2, wherein the filter circuit is formed of an open-ended stub. 4. The limiter circuit according to claim 1, which is a microwave hybrid circuit. 5. The limiter circuit according to claim 4, wherein the filter circuit is formed of an open-ended stub.