JPH04293126A - Repeat circuit of data processor - Google Patents

Abstract

PURPOSE:To enable the repeat operation of a desired number of times by a correct number of times even if an interruption processing enters in the course of repeat operation by constituting the circuit so that a value of a repeat counter is not varied at the time of interrupting operation. CONSTITUTION:In the repeat circuit which is contained in a data processor reading out and executing successively an instruction group stored in a memory and executes the control so that the same instruction is executed plural times, this circuit is provided with a counter control circuit 60 for executing the control so that a value of a repeat counter 51 for counting the number of times of a repeat is not varied, when an interrupting operation is inserted in the course of executing a repeat operation. That is, in the repeat circuit, when an interruption request INTR enters, an REPA signal is negated by setting an RSF/F 56, so that a decrement operation of the repeat counter register 51 is not executed and the repeat operation becomes a temporarily stopped state. Accordingly, at the time of returning from the interruption, the repeat processing can be finished by a correct number of times.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a repeat circuit that is included in an instruction control circuit of a data processing device such as a microprocessor and repeatedly executes the same instruction, and particularly relates to an improved circuit configuration thereof. .

0002

2. Description of the Related Art FIG. 4 is a diagram showing a conventional repeat circuit. In the figure, 51 is a repeat counter register;
2 is a decrementer, 53 is a φ (zero) detection circuit, 54 is an AND circuit, and 55 is an RS flip-flop.

Next, the operation will be explained. First, the repeat operation of the repeat circuit shown in FIG. 4 will be briefly explained using FIG. 3, which shows an example of a program control circuit including this repeat circuit, and FIG. 5, which shows its operation timing. In FIG. 3, 1 is a program counter (hereinafter abbreviated as PC), 2 is a PC value as an address input,
an instruction memory that outputs an instruction corresponding to that address; 3;
numeral 4 is an instruction register (hereinafter abbreviated as IR) for fetching the instruction outputted from the instruction memory 2; numeral 4 is a decoder for interpreting the contents of the instruction stored in the IR; numeral 5 is a repeat circuit. Further, 6 is an inverter, 7 is an AND circuit, and 8 is a stack register. Here, it is assumed that the PC1, IR3, and the repeat counter in the repeat circuit 5 operate in synchronization with a clock (hereinafter abbreviated as CLK). Also,
The outputs of the decoder 4 are representatively shown as RTI and REPR.

Normally, the PC 1 repeats an increment operation in synchronization with CLK, and the programs in the instruction memory 2 are sequentially read out to the IR 3 and decoded by the decoder 4.
A control signal is sent to the instruction execution unit, and the program read from the instruction memory 2 is executed. At this time, Figure 5
As shown in FIG. 3, if a repeat command REP exists in the program, the decoder 4 decodes this repeat command and outputs a repeat request signal REPR to the repeat circuit 5. This REPR activates the repeat circuit 5, and the repeat circuit 5 receives a signal R indicating that it is in the repeat operation.
Output EPA. REPA signal is connected to inverter 6 and A
The ND circuit 7 disables the CLK signal to be input to the PC1, thereby stopping the increment operation of the PC1. Therefore, during the period when the repeat circuit 5 is outputting the REPA signal, the output of the PC 1 will be the same value, and the same instruction M(n+1) on the program will be repeated.

An example of a conventional repeat circuit necessary for the above-mentioned repeat operation will be explained below. First, a value indicating the number of repeats is initially set in the repeat counter register 51 (hereinafter abbreviated as RC) by some means (for example, data transfer using a bus). Then, when the REPR signal is input as the activation signal of the repeat circuit, the RSF/F
55 is set, and a signal REPA indicating that repeating is in progress is outputted from its Q output. At the same time, the AND circuit 54 is enabled, the clock CLK is given to the RC 51, and the value obtained by subtracting 1 from the decrementer 52 is C
It is taken into RC51 in synchronization with LK, and RC51 performs a decrement operation. At this time, the φ detection circuit 53 constantly checks the value of RC, and the value obtained by subtracting 1 from RC is φ(
=0), a repeat end signal REPφ is output and the RSF/F 55 is reset. This allows REP
A is negated and the operation of the repeat circuit ends.

By the way, in the system shown in FIG. 3, it is necessary to interrupt from the outside and insert a special processing program in the middle of the operation according to the program sequence in the instruction memory. is often the case. For this purpose, a stack register 8 of PC1 is provided, and when an interrupt occurs, the value of PC1 is saved in the stack register 8, and the start address of the interrupt processing program is stored in PC1. After that, the PC is incremented, the interrupt processing program is executed sequentially, and the return instruction R is executed.
TI (Return from Interrupt)
The interrupt processing program returns to the main program. When returning, the value of the stack register is stored in the PC, and the PC is then incremented to resume execution of the main program.

However, in this conventional circuit, if an interrupt occurs during a repeat operation, the signal REPA indicating that the repeat is in progress is asserted, so the PC
The interrupt processing program does not operate normally because the clock CLK to is disabled. Furthermore, since REPA is asserted, RC is decremented, and the repeat count value immediately before the interrupt is generated is destroyed. For this reason, conventionally, a circuit provided separately within the program control circuit has been used to prevent interrupts from being accepted during the repeat operation, thereby avoiding the above-mentioned problems.

[0008]

[Problem to be Solved by the Invention] Since the conventional repeat circuit is configured as described above, if an interrupt occurs during repeat operation, the problem is that normal repeat operation becomes impossible after returning from the interrupt. There was a point.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a repeat circuit for a data processing device that can obtain a normal repeat count even when an interrupt occurs.

0010

SUMMARY OF THE INVENTION A repeat circuit for a data processing device according to the present invention is provided with a counter control circuit that controls the value of a repeat counter so that it does not change when an interrupt is activated.

[0011]

[Operation] In the present invention, with the above-described configuration, the value of the repeat counter does not change even when an interrupt occurs, so that the repeat processing can be completed with the correct number of times when returning from the interrupt.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a repeat circuit of a data processing device according to an embodiment of the present invention. In the figure, 51 is a repeat counter register, 52 is a decrementer, 53 is a φ detection circuit, 54 is an AND circuit, 55 is RSF/F, and 56 is RS
F/F, 57 is an inverter, 58 is an AND circuit, and 59 is a latch. A counter control circuit 60 controls the repeat counter value so as not to change when an interrupt is activated, and is comprised of the RSF/F 56, latch 59, inverter 57, and AND circuit 58.

The operation of the circuit shown in FIG. 1 will be explained below using the timing chart shown in FIG. 2 and the circuit diagram of the program control circuit shown in FIG. 4. In the initial state, the value of PC is n
, RC has a value of 4, and RSF/Fs 55 and 56 are both in the reset state. PC value is n+1 in synchronization with CLK
At the same time, the instruction at address n is taken into the IR. If the instruction at address n is a repeat instruction, the decoder 4 outputs a REPR signal. In response to this, RSF/F55 in FIG. 1 is set and the REPA signal is asserted, thereby disabling the CLK signal to the PC, stopping the increment operation of the PC, and entering the repeat state. Then, as in the conventional case, the RC decrement operation is performed in synchronization with CLK.

In this state, the interrupt request signal INT
Assume that R is input. When an interrupt occurs, the PC value in that cycle is saved to the stack register, and when an interrupt occurs in the PC in the next cycle, the start address i of the processing program is stored, and the IR is saved according to the PC address of the previous cycle. To cancel the instruction, use the no-operation instruction (
(hereinafter abbreviated as nop), and from now on, the PC is i, i+1
By incrementing ,...,i+m,
Execute the interrupt handling program. At this time, when the repeat circuit receives an interrupt request INTR, the RSF/F56
By setting , the REPA signal is negated and the repeat counter register 51 is not decremented, that is, the repeat operation is temporarily stopped.

Return from the interrupt processing program is as follows. First, assume that address i+m is a return instruction RTI. When the RTI instruction is decoded, the value saved in the stack register is stored in the PC in the next cycle, and the main program is then restarted. At this time, when the repeat circuit receives the return control signal RTI, the RSF
/F56 is reset, AND circuit 58
is enabled, the REPA signal is asserted, the decrementing operation of the repeat counter is restarted, and the operation of the repeat circuit is restarted. In other words, the repeat operation of the main program is resumed.

After that, when the value of RC becomes 1, the φ detection circuit detects this, RSF/F55 is reset, and R
The repeat operation ends when the EPA signal is negated.

As described above, according to this embodiment, when an interrupt occurs during execution of a repeat operation, the REPA signal is negated and the repeat counter is prevented from being decremented, so that when returning from the interrupt, the remaining number of repeats is calculated. Can be executed correctly.

In the above embodiment, as a method of detecting the end of the repeat operation, the value of RC is decremented by 1 and detected by the φ detection circuit, but as shown in FIG. 6, the value of the repeat counter 51 is 1 detection circuit 61 may be used for detection.

Further, in the above embodiment, the repeat count value is set in the repeat counter by an instruction other than the repeat instruction, but an operand for specifying the repeat count is provided in the repeat instruction, and this is decoded. It may be set in a repeat counter, and the same effect as in the above embodiment can be obtained.

Further, the repeat circuit may have any structure as long as it can store the value of the repeat counter at the time of an interrupt, and the same effect as in the above embodiment can be achieved.

[0021]Although the above embodiment describes the case where it is applied to a microprocessor, it is also applicable to a DSP (Digital Processor).
The present invention can be applied to any system that operates under program control, such as a tal signal processor) or a board computer, and provides the same effects as the above embodiments.

Furthermore, although the above embodiment has been described as being realized by wired logic, it may also be realized by a microprogram, and the same effects as in the above embodiment can be obtained.

[0023]

As described above, according to the present invention, the repeat circuit of the data processing device is configured so that the value of the repeat counter does not change during interrupt operation. This has the effect of making it possible to perform the repeat operation the correct number of times.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a repeat circuit of a data processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart for explaining one embodiment of the present invention.

FIG. 3 is a diagram showing a program control circuit including a repeat circuit.

FIG. 4 is a diagram showing a conventional repeat circuit.

FIG. 5 is a diagram showing a timing chart for explaining the operation of a conventional repeat circuit.

FIG. 6 is a circuit diagram of a repeat circuit of a data processing device according to another embodiment of the present invention.

[Explanation of symbols]

51 Repeat counter 52 Decrementer 53 φ detection circuit 54, 58 AND circuit 55, 56 RSF/F circuit 57 Inverter 59 latch 60 Counter control circuit 61 1 detection circuit

Claims (1)

[Claims] 1. In a repeat circuit that is built into a data processing device that sequentially reads and executes a group of instructions stored in a memory and controls the execution of the same instruction multiple times, an interrupt operation is inserted during execution of the repeat operation. 1. A repeat circuit for a data processing device, comprising a counter control circuit that controls the value of a repeat counter that counts the number of repeats so that it does not change when the repeat count is repeated.