JPH0429259B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog voltage output device, and more particularly to an analog voltage output device that converts a plurality of digital signals into a plurality of corresponding analog voltages and outputs the converted signals.

Conventionally, when outputting a digitally processed signal externally as an analog voltage value, a digital-to-analog converter is used to convert the digital signal to an analog voltage, and a voltage follower circuit or impedance converter is used to output the external signal as an analog voltage value. A device that outputs images was used.

An example of such a conventional analog voltage output device is shown in FIG. In the figure, 1 is a digital-to-analog converter (hereinafter abbreviated as a DA converter), and 2 is an operational amplifier as a current-to-voltage converter that receives the analog output current of the DA converter 1 and converts it into a voltage. , 3 is an operational amplifier serving as a voltage follower circuit or an impedance converter.

As is clear from the figure, D-A converter 1
The digital signal input to is converted into an analog current there, and further converted into an analog voltage in the current/voltage converter 2.

Impedance converter 3 outputs an output voltage equal to the input voltage. In this case, since the output impedance of the impedance converter 3 is sufficiently low, by selecting the value of its input resistance R sufficiently large, the output voltage can be kept constant regardless of the magnitude of its output current (i.e., its input voltage) can be maintained.

When an analog voltage output device using such a conventional DA converter is used, a relatively stable analog voltage can be obtained as an output. However, since this device has a one-to-one correspondence between inputs and outputs, if there are multiple outputs, the same number of sets of D-A converters, current/voltage converters, and impedance converters as the number of outputs are required. shall be.

Therefore, the circuit becomes complicated, which not only increases cost but also reduces reliability.

By the way, in order to solve these drawbacks, 1.
It is conceivable to provide a plurality of voltage hold circuits for one D-A converter, and use a changeover switch (analog switch) to sequentially output the output of the D-A converter to a predetermined voltage hold circuit.

However, when configured in this way, each voltage hold circuit and the output line of the D-A converter may be disconnected, so there is a risk that the voltage held by the voltage hold circuit, that is, the output voltage, may fluctuate (decrease). There is.

A branch technique for solving these drawbacks will be described below. FIG. 2 is a block diagram showing another example of an analog voltage output device. In this figure, the same reference numerals as in FIG. 1 represent the same or equivalent parts.

In the figure, 4 is a microcomputer, 7 is an analog multiplexer including analog switches _SW0 to _SW7 , and 8 to 15 are operational amplifiers as voltage follower circuits or impedance converters. Each voltage follower circuit constitutes a voltage hold circuit together with the respective hold capacitors C ₀ to C ₇ .

The circuit elements experimentally used by the inventor in the circuit configuration of FIG. 2 are as follows.

D-A converter 1...NEC μPD624D Current/voltage converter 2 Voltage follower circuits 8 to 15...TI TL081 Microcomputer 4...NEC μPD1511 Analog multiplexer 7...Toshiba TC4051BP
Next, the operation of the configuration shown in FIG. 22 will be explained with reference to the timing chart of FIG. 3.

The microcomputer outputs signals A, B, and C for designating analog switches, as shown in the timing chart shown in FIG.

Here, the signals A, B, and C can be considered as binary numbers, and when all of the signals A, B, and C are "0", the analog switch SW ₀ in Fig. 2 is designated and closed. , other analog switches SW ₁ to _{SW 7}
is held open. When all signals A, B, and C are “1”, the analog switch in Figure 2
SW ₇ is designated and closed, and the remaining analog switches SW ₀ to SW ₆ are open.

At time _T1 , the microcomputer 4 outputs signals A=0, B=0, and C and supplies them to the analog multiplexer 7. As a result, the analog switch SW ₀ in the analog multiplexer 7 is designated.

At the same time, the microcomputer 4 sends to the DA converter 1 an 8-bit data signal corresponding to the voltage to be output to the output terminal α. D-A
Converter 1 converts this signal into an analog current signal. The analog current signal is converted into an analog voltage signal Va by the amplifier 2 and is supplied to the common connection terminal of the analog multiplexer 7 via the resistor R ₁ .

At time _T2 , the microcomputer 4
Inhibit terminal of analog multiplexer 7
Set INH to L (low) level. Then, the previously specified analog switch SW ₀ in the analog multiplexer 7 is closed, and the analog voltage Va is supplied to the input terminal of the voltage follower circuit 8.

At time T ₃ , analog multiplexer 7
Set the inhibit terminal INH to H level to open the analog switch _SW0 . After that, until _the analog switch SW ₀ is closed again, the analog output voltage is
Hold Va.

At time T ₄ , the microcomputer 4 determines that A=
1, B=0, C=0 and designates the analog switch SW ₁ in the analog multiplexer 7.

At the same time, a digital signal corresponding to the analog voltage Vb to be outputted to the output terminal b is supplied to the DA converter 1. The digital signal is converted into an analog voltage Vb and supplied to the common terminal of the analog multiplexer 7.

At time _T5 , the microcomputer 4
Inhibit terminal of analog multiplexer 7
INH is set to L level, and the analog switch SW ₁ in the analog multiplexer 7 designated at this time is closed. As a result, analog voltage Vb is applied to the input terminal of voltage follower circuit 9.

At time T ₆ , analog multiplexer 7
Set the inhibit terminal INH to H level and open the analog switch _SW1 . Thereafter, the analog output voltage Vb is held by the hold circuit consisting of the capacitor _C1 and the voltage follower circuit 9 until the analog switch _SW1 is closed again.

Similarly, the analog voltages Vc to Vh to be sequentially supplied to the output terminals c to h are output cyclically at a predetermined period. Once the output has been completed, the voltage supply is started again from the output terminal α.

Generally, when using a circuit as shown in FIG. 2, the larger the capacitance of the capacitors C ₀ to _{C 7} used in the hold circuit, the better the voltage holding characteristics will be.

However, on the other hand, if the capacitance of the capacitor is increased, the capacitor is formed by these capacitors C ₀ to C ₇ and a current limiting resistor R ₁ . Since the time constant of the integrating circuit becomes large, the response time becomes long. In other words,
It takes a long time for the terminal voltage of each capacitor C ₀ to _{C 7} to reach a predetermined value and stabilize (hold).

In this way, under conditions where the response time of each hold circuit is long, if the hold voltages of all hold circuits are updated cyclically and periodically as described above, the time interval of voltage updates becomes The problem is that the signal is too long and cannot follow signals with a large rate of change.

As a solution to this problem, only when the digital signal from the microcomputer 4 changes and the output needs to change accordingly, the corresponding one of the analog switches SW ₀ to _{SW 7} is closed, and the above-mentioned It is conceivable to generate an updated analog voltage at the corresponding output terminal as follows.

However, in this method, the update period of the output with a small rate of change becomes long, so the fluctuation in the output voltage becomes large due to the leakage current of the capacitor of the hold circuit. Moreover, the fluctuation range has a drawback that it varies depending on the output terminals a to h.

Furthermore, the fluctuation width of the output voltage not only differs depending on the data update time but also varies from circuit to circuit, so it cannot be calculated accurately and it is not easy to compensate.

Therefore, as in the configuration shown in FIG. 2, analog voltages are cyclically output to the output terminals a to h, regardless of the presence or absence of a change in the output voltage, thereby reducing the fluctuation width of the output voltage. This means that it is desirable.

In addition, when updating the output voltage cyclically in this way, by shortening the time for one switching/scanning cycle, the values of the hold capacitors C ₀ to C ₇ can be reduced, and the output voltage can be changed easily. It also has the advantage of being communicated quickly.

However, the time for one cycle of switching and scanning described above is the conversion time (settling time) of the D-A converter 1, the operational amplifiers 2, 8 to 15 as current/voltage converters and voltage follower circuits, etc.
response time, or analog switch SW ₀
It is clear that it is constrained by the response time of ~ _SW7 .

By the way, in the configuration shown in FIG. 2, the capacitors C0 to C7 forming the voltage hold circuit
, analog multiplexer 7 and operational amplifier 8 ~
Charges flow into or out of these. This phenomenon occurs when each analog switch SW in the analog multiplexer 7
This occurs even when SW 0 to SW7 are in the open state.

Here, when each analog switch SW0 to SW7 is in an open state, the leakage current from the analog multiplexer 7 to each capacitor _C0 to _C7 has the highest contribution rate to fluctuations in the output voltages Va to Vh.
Alternatively, it is known that this is due to leakage current from each capacitor C ₀ to _{C 7} to the analog multiplexer 7 . As described above, in the analog voltage output device as shown in FIG. 2, the variation in the analog output voltage at each of the output terminals a to h is relatively large due to the leakage current.

The present invention has been made in order to solve the above-mentioned drawbacks, and an object of the present invention is to provide an analog voltage output device that uses an analog switch and in which fluctuations in the analog output voltage at each of the output terminals a to h do not become too large. .

The present invention is characterized in that the leakage current is said to be proportional to the square of the potential difference between the voltage at the common input terminal of the analog multiplexer and the voltage at the opposite terminal of each analog switch, that is, the analog output voltage. It was created with a focus on

That is, in the present invention, the voltage hold circuits are connected in two stages. Specifically, the present invention connects a plurality of first analog switches to a D-A converter, and each of the first analog switches is provided with a first voltage hold circuit, a second analog switch, and a second voltage hold circuit. are connected in series so that a series of first and second analog switches between a predetermined second voltage hold circuit and a DA converter are energized almost simultaneously.

Since the holding voltage of the output stage voltage hold circuit (second voltage hold circuit) and the holding voltage of the first stage voltage hold circuit (first voltage hold circuit) are almost equal, the potential difference before and after the second analog switch is extremely small. As a result, the leakage current of the hold capacitor of the final stage voltage hold circuit becomes extremely small.

FIG. 4 is a block diagram of an embodiment of the present invention.
In this figure, the same reference numerals as in FIG. 2 represent the same or equivalent parts.

As is clear from a comparison with Fig. 2, the digital signal from the microcomputer 4 is converted into an analog current by the DA converter 1, which is then passed through the analog switches SW ₀ to _{SW 7} to the corresponding voltage follower circuit. The configuration until it is transmitted to the output side of signals 8 to 15 is exactly the same as that shown in FIG. 2 described above.

In the embodiment shown in FIG. 4, the selection and energization of the analog switches SW ₀ to SW ₇ are shown to be performed by individual control outputs SC ₀ to _{SC 7} from the microcomputer. , it goes without saying that a multiplexer similar to that shown in FIG. 2 may be substituted.

In the figure, 20-27 are second analog switches connected to the outputs of the voltage follower circuits 8-15 via corresponding resistors _R10 - _R17 , respectively. These analog switches 2
0 to 27 are the aforementioned analog switches SW ₀ to _{SW 7}
Similarly, they are selected and energized by control outputs _SC0 to _SC7 from the computer 4.

C ₁₀ to _{C 17} are each of the second analog switches 20
Hold capacitors 30 to 37 are voltage follower circuits connected to the output terminal side of 27, and each pair of the hold capacitor and voltage follower circuit constitutes a second voltage hold circuit.

As described above with reference to FIG. 2, the input ends of the analog switches SW ₀ -SW ₇ are commonly connected, and the analog voltages Va - Vh are periodically and cyclically applied thereto.

Therefore, as is clear, the potential difference between the input side (common connection) terminal and the output side terminal of each analog switch SW ₀ to _{SW 7} is likely to become large. That is, the amount of charge flowing into or flowing out from the capacitors C ₀ to _{C 7} forming the voltage hold circuit increases, and the fluctuations in the hold voltage increase.

On the other hand, in the configuration shown in FIG. 4, when focusing on a specific final output terminal (any one of a to h), there is a Two analog switches arranged in series (analog switches SW0 to SW7 (hereinafter referred to as
(referred to as the first analog switch SW0 to SW7)
and the second analog switch 20~
27) are energized almost simultaneously, the voltage generated on the common input line of the first analog switch at a certain time is applied to the voltage follower circuits 8 to 15 (hereinafter referred to as the first voltage follower circuit). The voltage follower circuits 30 to 37 (hereinafter referred to as second voltage follower circuits 30 to 37) are commonly supplied. As a result, the first voltage follower circuit and the second voltage follower circuit are connected to the capacitors C0 to C7.
Due to the charging action of C10 to C17, approximately the same voltage is maintained.

The fluctuation of the holding voltage of the voltage follower circuit is
It depends on the potential difference before and after the analog switch, and at different times, the first analog switch
When the potential of the common line of SW0 to ST7 is changed by the DA converter 1, the potential of the common line of the first analog switches SW0 to SW7 and the set potential of the first voltage follower circuit are changed. , it is quite conceivable that there is a large difference.

However, since the holding potential of the second voltage follower circuit is almost equal to the holding potential of the first voltage follower circuit, the potential difference before and after the second analog switch is extremely small, and as a result, each hold capacitor C10~ The amount of charge flowing into or flowing out of C17 becomes extremely small.

Therefore, fluctuations in the held potential of the second voltage follower circuit, that is, the terminal voltages at the final output terminals a to h, are extremely small, resulting in good signal hold characteristics.

As is clear from the above description, according to the present invention, even when there are multiple analog output signals, one
It is only necessary to use one D-A converter, which makes it possible to simplify the circuit and reduce costs. Furthermore, since there is no need to take into account variations in the characteristics of the D-A converter, there is an advantage that assembly and adjustment can be simplified. Furthermore, a second voltage hold circuit is further connected to the voltage hold circuit (first voltage hold circuit) connected to the analog switch (first analog switch) via a second analog switch. Therefore, the signal hold characteristics at the signal output end are further improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional analog voltage output device, Fig. 2 is a block diagram showing another example of an analog voltage output device, Fig. 3 is a timing chart for explaining its operation, and Fig. 4 is a diagram of the present invention. FIG. 2 is a block diagram of an embodiment of the invention. 1...D-A converter, 2...Current/voltage converter, 4...Microcomputer, 7...
Analog multiplexer, 8-15, 30-37
...Voltage follower circuit, 20 to 27, SW ₀
~SW ₇ ...Analog switch, a~h...Analog voltage output terminal.

Claims (1)

[Claims] 1: a digital-to-analog converter that receives a digital signal and outputs an analog voltage; a plurality of first analog switches, each of which has one terminal commonly connected to the output of the digital-to-analog converter; a plurality of first voltage hold circuits each having an input terminal connected to the other terminal of each first analog switch; and a plurality of second analog switches each connected to an output terminal of each of the first voltage hold circuits; a plurality of second voltage hold circuits connected to each of the second analog switch terminals on the side opposite to the first voltage hold circuit; and means for energizing the first analog switch and the second analog switch; An analog voltage output device characterized in that the energizing means energizes a first analog switch and a second analog switch, which are respectively connected to an input terminal and an output terminal of one first voltage hold circuit, almost simultaneously.