JPH04291930A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain the title device which has reduced a difference in level and which has-reduced problems at photolithography by forming an insulating layer which is formed on a semiconductor substrate so as to surround a gate electrode, which is provided with an opening on a source/drain region and whose surface is nearly at the same height as that of the gate electrode. CONSTITUTION:The title device is provided with the following: a semiconductor substrate 1 of a first conductivity type; a gate insulating film 2 formed on the semiconductor substrate 1; a gate electrode 3 formed on the gate insulating film 2; and one pair of second-conductivity-type regions 4, 5 which are formed on the surface of the semiconductor substrate 1 on both sides of the gate electrode 3 and which is provided with a second conductivity type opposite to said first conductivity type. In addition, the device is provided with the following: an insulating layer 6 which is formed on the semiconductor substrate 1 so as to surround the gate electrode 3, which is provided with openings 11 on the second-conductivity-type regions 4, 5 and whose surface is nearly at the same height as that of the gate electrode 3; and one pair of current electrodes 7, 8 which are connected to the second-conductivity-type regions 4, 5 via the openings 11 on the second-conductivity-type regions 4, 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device and its manufacturing method suitable for miniaturization.

In semiconductor devices such as memories, there is a strong demand for higher integration and higher speed. In order to meet these demands, miniaturization of each transistor constituting a semiconductor device is desired.

0003

2. Description of the Related Art FIG. 2 schematically shows a method of manufacturing a MOS transistor according to the prior art.

In FIG. 2A, an LDD (structure having a drain region with low impurity concentration) type source/drain region 54 is formed on the surface of a semiconductor substrate 51 made of p-type silicon or the like.
, 55 are formed. These source/drain regions include regions 64, 66 with relatively low impurity concentration and regions 65, 67 with relatively high impurity concentration. Further, a field oxide film 68 is formed on the surface of the semiconductor substrate 51 surrounding the element region.

A gate electrode 53 made of polycrystalline silicon (polysilicon) or the like is formed on a region sandwiched between the source/drain regions 54 and 55 with a gate insulating film 52 made of a silicon oxide film or the like interposed therebetween. An insulating layer 62 made of silicon oxide or the like is formed to cover this gate electrode 53. Insulating layer 6
A photoresist layer 69 is formed over the insulating layer 62 to form an opening through the insulating layer 62 to expose the source/drain regions 54,55.

[0006] Note that there are LDDs on both sides of the gate electrode 53.
A sidewall oxide film 71 for creating the structure is formed. That is, before forming the sidewall oxide film 71, relatively low-dose ion implantation is performed to form regions 64 and 66 with a relatively low impurity concentration, and then the sidewall oxide film 71 is formed, and relatively high-dose ions are implanted. Implantation is performed to form regions 65 and 67 with relatively high impurity concentration to form an LDD structure.

Thereafter, an opening pattern is exposed in the photoresist layer 69 and the insulating layer 62 is selectively etched, thereby forming the source/drain regions 54 and 55 and the gate electrode 5.
Form an opening above 3.

As shown in FIG. 2B, an aluminum (Al) layer is formed on the insulating layer 62 in which the opening 61 is formed, and patterned using photolithography to form a source electrode 57 and a drain electrode. 58. Form a metal gate electrode 59 connected to the polycrystalline gate electrode 53.

Here, the surface of the insulating layer 62 has different heights above the source/drain regions 54 and 55 and above the gate electrode 53.

[0010] As transistors are miniaturized, their dimensions are reduced. For example, the gate length of the gate electrode placed between the source/drain regions is 1 in the case of 1MDRAM.
．． 2μm, 0.8μm for 4MDRAM, 16MDRA
The size is gradually reduced to 0.5 μm for M and 0.3 μm for 64M DRAM. In addition, the gate length is 0.3 μm (0
．． 3μm rule), the thickness of the gate electrode is approximately 200n.
m, the thickness of the interlayer insulating film will be approximately 400 nm. In order to expose such fine patterns,
It becomes necessary to select a large numerical aperture for the optical system used in photolithography. When the numerical aperture is increased, the depth of focus becomes shallower. When the depth of focus of the lens becomes shallow, differences in level during the semiconductor manufacturing process become a problem. For example, in the structure shown in FIGS. 2A and 2B, the surface of the insulating layer 62 has a step equal to the thickness of the gate electrode 53. Then, the lens system is required to have a depth of focus sufficient to overcome this step.

Furthermore, as the gate length becomes smaller, it becomes difficult to provide an opening above the gate electrode 53 and directly form an aluminum electrode as shown in FIG. 2(B). On the other hand, the gate electrode 53 formed of polycrystalline silicon has a thinner thickness, and its lateral resistance cannot be ignored.

FIG. 3 shows a transistor structure according to the prior art in consideration of miniaturization. In FIG. 3A, a polysilicon gate electrode 53 extending vertically at the center defines a source region 54 and a drain region 55 on the left and right sides thereof. The gate electrode 53 has a wider region outside the element. After forming an insulating layer on the surface of the gate electrode 53, an opening 73 is formed in the widened region of the gate electrode as well as the contact opening 61 in the source region 54 and drain region 55. Thereafter, an aluminum layer is formed and patterned to form an aluminum gate electrode 75, which is brought into contact with the underlying polysilicon gate electrode through the opening 73. Note that in the openings 61 of the source region 54 and drain region 55, the source electrode and the drain electrode contact the underlying semiconductor layer through the openings 61.

According to this configuration, since the gate electrode contacts the aluminum gate electrode 75 at both ends thereof, the resistance of the gate electrode only needs to be considered from the position where it contacts the aluminum electrode. In this way, the effective gate resistance can be reduced.

Even with such a configuration, for example, C
In MOS circuits and the like, the resistance of the polysilicon gate electrode beyond the point of contact with the aluminum gate electrode poses a problem.

FIG. 3(B) schematically shows the configuration of a CMOS circuit. In the CMOS structure, a p-channel transistor 77 and an n-channel transistor 78 are formed adjacent to each other. The polysilicon gate electrode 53
The two transistors 77 and 78 are formed in common. For example, the gate width of p-channel transistor 77 is approximately 20 μm, and the gate width of n-channel transistor 78 is approximately 19 μm. The polysilicon gate electrode 53 then extends for a length of at least 30 μm without contacting the aluminum electrode. Therefore, the resistance of the polysilicon gate electrode cannot be ignored.

[0016] Furthermore, peripheral circuit portions of memory circuits and the like have transistors with long gate widths. In such a case, the length of the polysilicon gate electrode becomes long and its resistance cannot be ignored.

Furthermore, even when the polysilicon gate electrode is supplemented by an aluminum electrode, the size of the opening becomes smaller as the transistor becomes finer. When the size of the opening becomes smaller, for example, 1 μm square or less, the contact resistance tends to increase rapidly.

Furthermore, as miniaturization progresses, it becomes necessary to form contact regions for the source and drain regions in portions where the thickness of the insulating layer 62 changes, as shown in FIG. 2(C). It's coming. The insulating layer 62 has a surface that gradually changes from the end of the gate electrode 53 toward the surface of the semiconductor substrate 51, but has a larger thickness near the gate electrode 53 than in other parts. If the opening 61 is formed in a portion where the thickness of the insulating layer 62 changes, the etching depth required to expose the semiconductor surface becomes deep. However, if etching is carried out for a sufficient period of time to remove a thick insulating layer, over-etching will occur in the thin portions of the insulating layer.

[0019]

[Problem to be solved by the invention] As explained above,
When a conventional transistor structure is used and miniaturized, problems such as surface steps and increased resistance of a gate electrode formed of polysilicon or the like arise.

[0020] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which steps are reduced and problems in photolithography are reduced.

Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which the resistance of a gate electrode made of polycrystalline silicon does not cause problems.

[0022]

[Means for Solving the Problems] FIG. 1 shows a diagram illustrating the principle of the present invention.

FIG. 1(A) is a cross-sectional view showing the configuration of the main parts of a semiconductor device. A gate electrode 3 is formed on a first conductivity type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. On the surface of the semiconductor substrate on both sides of this gate electrode 3,
A pair of second conductivity type regions 4 of a second conductivity type opposite to the first conductivity type
, 5 are formed and function as source/drain regions. Further, around the gate electrode 3, an insulating layer 6 is formed on the semiconductor substrate 1 surrounding the gate electrode 3 and having an opening 11 above the second conductivity type regions 4 and 5. This insulating layer 6 has a surface approximately at the same height as the gate electrode 3.

A pair of current electrodes 7 and 8 are formed to be connected to the second conductivity type regions 4 and 5 through openings 11 on the second conductivity type regions 4 and 5.

Note that a low resistance metal electrode, for example 9, is formed on the surface of the gate electrode 3 or on the gate electrode 3, if necessary.

Although the element region is surrounded by the element isolation region 18, it is not essential.

FIG. 1(B) shows a configuration in an intermediate step of creating the configuration of FIG. 1(A). A gate electrode 3 is formed on the surface of the semiconductor substrate 1 with a gate insulating film 2 interposed therebetween, and second conductivity type regions 4 and 5 are formed on the surface of the semiconductor substrate 1 on both sides of the gate electrode 3. An insulating layer 1 that covers the semiconductor substrate 1 and the gate electrode 3 and has a substantially flat surface.
2 is formed. That is, the insulating layer 12 buries the gate electrode 3 to form a substantially flat surface.

Thereafter, the insulating layer 12 is etched from the surface, and when the etching is stopped when the gate electrode 3 is exposed, an insulating layer having a surface substantially the same as the surface of the gate electrode 3 is formed. This state is shown by a broken line in the figure.

[0029]

[Operation] Since the gate electrode 3 and the surrounding insulating layer 6 form almost the same plane, when the photoresist layer is created to form the opening 11, there are almost no steps, so even a shallow depth of focus is fatal. It does not become a hindrance. Therefore, highly accurate photolithography can be performed.

Furthermore, since the gate electrode 3 is exposed on the surface of the insulating layer 6, a low-resistance metal electrode 9 can be easily formed on or on the surface. In this case, since the contact can be formed on a continuous surface, contact resistance is not a problem.

[0031]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 shows the basic configuration. 4(A) is a plan view, and FIG. 4(B) and (C) are 4B-4 in FIG. 4(A).
It is a sectional view along the B line and the 4C-4C line.

In FIG. 4A, a gate electrode 3 made of polysilicon extends vertically in the figure, and an insulating layer 6 made of silicon oxide or the like is formed on the left and right sides of the gate electrode 3 to form substantially the same plane. There is. In the semiconductor substrate under the insulating layer 6, a source region 4 and a drain region 5, which are n-type regions, are formed facing each other with the gate electrode 3 in between. Note that in order to form an opening in a region 11 of the insulating layer 6 indicated by a broken line, the surface is covered with a photoresist layer 19 (not shown).

FIG. 4(B) shows a cross-sectional view along the current direction of FIG. 4(A). On the surface of a semiconductor substrate 1 made of p-type silicon, a source region 4 and a drain region 5 made of an n-type region with a higher impurity concentration are formed. Outside the source region 4 and drain region 5, an element isolation region 18 of silicon oxide is formed by LOCOS. Note that a channel stop region 22 made of a p-type region with a high impurity concentration is formed under the element isolation region 18 to prevent an induced channel. The gate electrode 3 made of polysilicon is doped with phosphorus (P) to provide conductivity. In addition, the gate electrode 3
A gate insulating film 2 made of silicon oxide or the like is formed between the surface of the semiconductor substrate 1 and the semiconductor substrate 1 . On the side of the gate electrode 3,
A sidewall oxide film 21 is formed. This sidewall oxide film 21 is an n-type region 1 with a low impurity concentration.
4 and 16, and n-type regions 15 and 17 with high impurity concentration. An insulating layer 6 made of silicon oxide or the like is formed on the outside of the sidewall oxide film 21 . The surface 3a of the gate electrode 3 and the surface 6a of the insulating layer 6 form substantially the same surface. This is formed almost identically. This almost same plane 3
A photoresist layer 19 is formed on a and 6a.

FIG. 4C shows a cross-sectional view along the direction of the gate electrode. Gate electrode 3 is formed on the surface of semiconductor substrate 1 with gate insulating film 2 interposed therebetween, and extends over element isolation region 18 . Although a configuration is shown in which the surface 3a of the gate electrode 3 is flat also on the element isolation region 18, the gate electrode 3 may have an upwardly raised surface on the element isolation region 18.

From the structure shown in FIG. 4, an opening 11 reaching the source region 4 and drain region 5 is formed, and a source electrode and a drain electrode are formed to create a transistor structure. In the illustrated configuration, since the underlying surface on which the photoresist layer 19 is formed is made substantially flat, depth of focus problems in the photolithography process are reduced. Furthermore, since the surface 3a of the gate electrode 3 is exposed, a good conductor such as a metal layer can be formed on the entire exposed surface. Therefore, the problem of increased resistance even when the thickness of the polysilicon gate electrode 3 is reduced can be easily solved.

Examples of the present invention will be explained in more detail below. FIG. 5 shows a process of creating a flat surface structure on a semiconductor substrate for forming a MOS transistor.

Next, FIG. 5A shows a step of forming element isolation regions and the like on the semiconductor substrate. A thin oxide film and a nitride film are laminated and formed on the surface of a p-type silicon semiconductor substrate 1,
The nitride film is patterned to remain on the element formation region, and the semiconductor substrate 1 is oxidized to form the element isolation region 18. The element isolation region 18 has a thickness of, for example, 400 nm. Furthermore, a gate oxide film 2 having a thickness of about 12 nm, for example, is formed on the surface of the element formation region.

Phosphorus (P) is deposited on the surface of the structure shown in FIG. 5(A).
A polysilicon layer with a thickness of about 200 nm doped with is formed, and subsequently a silicon oxide film with a thickness of about 30 nm is formed by CVD. Thereafter, a photoresist layer is formed on the surface and patterned to form a polysilicon gate electrode 3 as shown in FIG. 5(B). Note that a silicon oxide layer 20 formed by CVD remains on the surface of the polysilicon gate electrode 3. Using gate electrode 3 and silicon oxide layer 20 thereon as a mask, n-type impurity ions are implanted at a relatively low dose to form n-type regions 14 and 16 with relatively low impurity concentration.

[0040] Thereafter, for example, a layer of about 120 nm thick is applied onto the surface.
A silicon oxide layer of m is formed by CVD, and the silicon oxide layer on the flat portion is removed by performing anisotropic etching such as reactive ion etching. This anisotropic etching leaves the silicon oxide layer deposited on the side surfaces of the gate electrode 3, leaving the sidewall oxide film 21.
form.

Using the gate electrode 3 and sidewall oxide film 21 as a mask, ions are implanted at a relatively high dose to form n-type regions 15, 1 with a relatively high impurity concentration.
form 7. In this way, source region 4 and drain region 5 are formed on the surface of semiconductor substrate 1. This state is shown in FIG. 4(C).

Thereafter, as shown in FIG. 5D, a silicon oxide film 23 with a thickness of about 30 nm is formed on the surface by CVD, and a silicon oxide film 25 with a thickness of about 500 nm is formed on the surface by spin-on glass. Form. These oxide films 23 and 25 constitute the insulating layer 12.

Note that the spin-on glass oxide film 25 is
After coating the surface of the semiconductor substrate 1 to form a substantially flat surface, water and the like are evaporated at, for example, about 450° C. to form a silicon oxide film having a flat surface. The thickness of this silicon oxide film 25 is not critical.

Note that the reason why the surface of the semiconductor substrate is first covered with the CVD oxide film 23 is to protect the semiconductor surface with a high-quality silicon oxide film.

In this way, a semiconductor structure with a flat surface is created. If the insulating layer 12 is then etched from the surface to expose the gate electrode 3, the basic configuration shown in FIG. 4 can be created. The etching is
This can be carried out by ion milling or anisotropic dry etching. In the case of ion milling, the surface is etched almost uniformly regardless of the difference in material. Anisotropic dry etching is performed using, for example, C in an ozone atmosphere.
This can be done using Cl4 as an etchant.

Next, a method for reducing the resistance of the gate electrode 3 configured as shown in FIG. 4 will be explained.

FIG. 6 shows a step of reducing the resistance of the gate electrode by silicidation. From the structure shown in FIG. 5(D), the gate electrode 3 is exposed by etching the surface portion to obtain the structure shown in FIG. 6(A).

Next, as shown in FIG. 6B, a titanium (Ti) layer 27 having a thickness of, for example, about 60 nm is formed by sputtering.

When rapid thermal annealing (RTA) is performed with the surface covered with the Ti layer 27, the polysilicon on the surface of the gate electrode 3 reacts with Ti to form TiSi2.

After that, the unreacted Ti film 27 is removed, and as shown in FIG.
The structure shown in (C) is obtained. The gate electrode is formed by a lower polysilicon gate electrode 3a and an upper Ti silicide film 28. Polysilicon has a specific resistance of approximately 1 at most.
In contrast, Ti silicide can have a specific resistance of about 1×10 −5 Ω·cm, and the resistance of the gate electrode 3 can be effectively and significantly reduced. Note that even after silicidation, the surface remains substantially flat.

Thereafter, as shown in FIG. 6(D), a photoresist layer 30 is formed on the surface, openings 31 for forming source and drain electrodes are created, and the insulating layer 6 below is formed.
By etching, the source region 4 and drain region 5 are exposed. Thereafter, a transistor structure is obtained by forming an aluminum layer and forming a source electrode and a drain electrode using a conventional method.

FIG. 7 shows another method for reducing the effective resistance of the gate electrode. By performing etching from the state shown in FIG. 5(D), the surface of the gate electrode 3 is exposed and the etching is stopped. After that, FIG. 7(A)
As shown in FIG. 3, a photoresist layer 33 is formed on the surface, and openings 34 are formed above the source region 4 and drain region 5. Using the photoresist layer 33 as a mask, the lower insulating layer 6 is
By anisotropic etching using IE, an opening 11 is formed in the insulating layer 6 and the source region 4 and drain region 5 are exposed. The photoresist layer 33 is then removed.

Next, as shown in FIG. 7B, an Al layer is formed to a thickness of about 0.6 μm by sputtering and patterned to form the source electrode 7 on the source region 4 and the source electrode 7 on the drain region 5. Gate metal 36 on drain electrode 8 and gate electrode 3 is formed. Al layer 7,
A low resistance contact is formed by alloying 8,36 at a temperature of about 450°C.

Al is a metal with low specific resistance, and since the Al electrode 36 is in low resistance contact with the entire surface of the gate electrode 3, the lateral resistance of the polysilicon gate electrode 3 can be ignored.

FIG. 8 shows a method for further flattening the surface. FIG. 8A corresponds to the state in which the photoresist layer 33 is removed after the opening 11 is formed in the insulating layer 6 in FIG. 7A. However, before forming the photoresist layer, the semiconductor substrate is oxidized at about 850° C. for 30 minutes to form an oxide film with a thickness of about 10 nm on the surface of the gate electrode 3.

Next, as shown in FIG. 8B, tungsten (
W) is selectively grown. For example, WF6 + SiH4 or WF6 + H2 is used as a source gas to selectively grow W only on the Si surface. here,
Since an oxide film is formed on the surface of the gate electrode 3,
W does not grow. In this way, the W layers 37 and 38 are grown within the opening 11, reducing the step difference in the opening. Preferably, the W layers 37 and 38 are grown to approximately the same height as the surface of the insulating layer 6.

Thereafter, as shown in FIG. 8C, the silicon oxide film on the gate electrode 3 is removed, an Al layer is formed on the entire surface, and patterned by photolithography to form the W source electrode 37 and the W drain. Al electrodes 41, 42, and 35 connected to the electrode 38 and the polysilicon gate electrode 3 are obtained.

According to this structure, the influence of the step caused by the opening 11 on the source region 4 and drain region 5 is reduced. Note that the specific resistance of W is as low as approximately 1 x 10-6 Ωcm, and W
resistance is not a problem.

Although the present invention has been described above with reference to examples, the present invention is not limited to these examples. For example, the insulating layer 6 is not limited to spin-on glass as long as it can form a flat surface. If more than half of the initial level difference can be reduced, it can be said that a nearly flat surface is created. Also, in the configurations shown in FIGS. 7 and 8, the gate electrode 3
The surface can also be silicided. Siliciding of the gate electrode surface was performed after burying the gate electrode with the insulating layer 6 and exposing the gate electrode again by etching to form an almost flat surface as a whole, but siliciding was performed before patterning the gate electrode. The gate electrode whose surface is silicided may be patterned and subsequent steps may be performed.

It will be obvious to those skilled in the art that various other changes, improvements, combinations, etc. are possible.

[0061]

[Effects of the Invention] As explained above, according to the present invention,
Level differences during semiconductor device manufacturing are reduced, and accuracy in photolithography is improved.

Furthermore, even if the thickness of the gate electrode is reduced, the resistance of the gate electrode can be effectively reduced.

Therefore, it becomes easy to manufacture a semiconductor device including a miniaturized transistor.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 1(A) is a sectional view showing the configuration, and FIG. 1(B) is a sectional view showing the intermediate configuration.

FIG. 2 shows a conventional technique. FIG. 2(A) is a cross-sectional view showing the formation of an insulating layer covering the gate electrode, FIG. 2(B) is a cross-sectional view showing the state in which an aluminum electrode is formed, and FIG. 2(C) is a cross-sectional view showing the formation of an insulating layer covering the gate electrode. FIG.

FIG. 3 shows a conventional technique. FIG. 3(A) is a plan view showing an Al lining structure for reducing the resistance of the gate electrode.
B) is a plan view showing the case of CMOS.

FIG. 4 shows a basic configuration according to an embodiment of the present invention. Figure 4 (
A) is a plan view, and FIGS. 4(B) and 4(C) are sectional views.

FIG. 5 illustrates a process for creating a flat surface structure according to an embodiment of the invention. Figures 5 (A), (B), (C), (D)
are sectional views at main steps during the fabrication of a semiconductor device.

FIG. 6 shows resistance reduction of a gate electrode by silicidation according to an embodiment of the present invention. Figure 6 (A), (B), (C
) and (D) are cross-sectional views of main steps in manufacturing a semiconductor device.

FIG. 7 illustrates the creation of an aluminum layer backing structure according to an embodiment of the invention. FIGS. 7A and 7B are cross-sectional views of main steps.

FIG. 8 illustrates a method for achieving more complete planarization according to an embodiment of the present invention. FIGS. 8(A), 8(B), and 8(C) are cross-sectional views showing the main steps of manufacturing a semiconductor device, respectively.

[Explanation of symbols]

1 Semiconductor substrate 2 Gate insulating film 3 Gate electrodes 4, 5 Second conductivity type region (source/drain region) 6
Insulating layers 7, 8 Current electrode (source/drain electrode) 9 Metal electrode 11 Opening 12 Insulating layer 18 Element isolation region 28 Ti silicide layer 36 Al electrode 38 W electrode

Claims (6)

[Claims] Claim 1: A semiconductor substrate (1) of a first conductivity type;
a gate insulating film (2) formed on the semiconductor substrate;
a gate electrode (3) formed on the gate insulating film;
A pair of second electrodes formed on the surface of the semiconductor substrate on both sides of the gate electrode and having a second conductivity type opposite to the first conductivity type.
conductive type regions (4, 5), surrounding the gate electrode, formed on the semiconductor substrate, having an opening (11) above the second conductive type region, and having approximately the same height as the gate electrode; and a pair of current electrodes (7, 8) connected to the second conductivity type region through an opening on the second conductivity type region. 2. The semiconductor device according to claim 1, wherein the gate electrode (3) is formed of a polycrystalline semiconductor, and a metal word line (9) is in contact thereon. 3. The pair of current electrodes (7, 8) are arranged in the opening (6) and have a first metal formed part (7a, 8a) and a second metal part (7a, 8a) arranged thereon. 2. The parts (7b, 8b) formed of a metal of claim 1 or 2.
The semiconductor device described. 4. A step of forming a gate insulating film (2) and a gate electrode (3) thereon on a semiconductor substrate (1) of a first conductivity type, and using the gate electrode (3) as a mask, Implanting impurities of the second conductivity type on both sides of the electrode,
A step of forming a pair of second conductivity type regions (4, 5), forming an insulating layer (12) having a substantially flat surface on the surface of the semiconductor substrate (1), and also forming the gate electrode (3). embedding, etching back the insulating layer (12) and shaping it into an insulating layer (6) having a substantially flat surface exposing the gate electrode (3), and forming the insulating layer (6) by photolithography. A method for manufacturing a semiconductor device, comprising: forming an opening in the semiconductor device; and forming a current electrode (7, 8) in contact with the second conductivity type region (4, 5) through the opening. 5. The gate electrode (3) is made of polycrystalline silicon, and further, after forming the gate electrode or shaping the insulating layer, a metal layer that causes a silicidation reaction is formed on the surface of the gate electrode (3), 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of siliciding the surface of the gate electrode (3) by heating and removing an unreacted metal layer. 6. The current electrode (7, 8) forming step comprises:
selectively growing a first metal layer (7a, 7b) on the second conductivity type region (4, 5) exposed in the opening;
6. The method of manufacturing a semiconductor device according to claim 4, further comprising forming and patterning a second metal layer (7b, 8b) on the surface.