JPH04291643A - Information storage device - Google Patents

Abstract

PURPOSE:To continue the operation of a system without generating system down even when reset due to noise or the like is generated. CONSTITUTION:Data are successively recorded in two storage areas in an A system memory 13 and two storage areas in a B system memory 14 in a bus synchronous duplex system at a fixed period. When a reset signal is generated due to the generation of abnormality, the validity/ invalidity of the reset signal is judged from the up-to-date recorded information and the information judged as valid is outputted. Consequently a CPU can continue operation without generating system down again due to invalid information on the way of recording.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information storage device.

0002

2. Description of the Related Art For example, in recent years, control systems using computers have been widely introduced in railway signal safety equipment and the like in order to cope with the increasing density of traffic. Some of these control systems are equipped with a restart function to protect devices within the system. For example, when the CPU malfunctions due to the intrusion of unexpected noise such as external noise, the system itself detects this and automatically resets the CPU to return to its initial state. In this system, the system is operated again by performing initial processing without clearing the information (see Japanese Patent Application No. 1-2757, etc.).

0003

By the way, in such an information storage device, if a reset occurs while information is being recorded in the memory, the information being recorded will be incomplete and will be invalid information. Therefore, if the CPU uses such invalid information at the time of restart, there is a risk that the system will go down again due to the rationality verification check.

[0004] The present invention has been made in view of such conventional problems, and an object of the present invention is to provide an information storage device that can continue operation without causing a system down even if a reset occurs due to noise or the like. do.

[0005]

[Means for Solving the Problems] Therefore, the present invention has the following features:
As shown in , after an error occurs during system operation, C
In an information storage device configured to automatically restart a CPU by outputting a reset signal to a PU, the information storage means has a plurality of storage areas for storing information, and the information storage means has a plurality of storage areas for storing information. information recording means for sequentially recording, and determining means for sequentially determining whether or not information in a plurality of storage areas of the information storage means is correct or not, starting from the latest information when a reset signal for restarting the CPU is generated;
and information output means for outputting information determined to be correct by the determination means.

[0006]

[Operation] According to the above structure, information is sequentially recorded by the information recording means in a plurality of storage areas of the information storage means. When the reset signal for restarting is generated, the information being recorded is incomplete and becomes invalid information, but the determining means sequentially determines whether the information in the plurality of storage areas is correct or not, starting from the latest information,
The information output means outputs information determined to be correct. Therefore, the CPU can continue operating without the system going down again due to fraudulent information.

[0007]

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In FIG. 2 showing this embodiment, an information storage device 1
For example, information such as the traveling distance and speed of the train is constantly inputted from the information input device 2. The information storage device 1 is composed of a bus synchronous dual system having two control systems, an A system and a B system, which perform the same processing in synchronization.The information storage device 1 compares the input information via the bus and checks if it matches. If the system is determined to be normal, the A system generates a control output for the controlled object, and if there is a mismatch, it is determined to be abnormal.

The A-system and B-system control systems include CPUs 11 and 12 that execute the same process on the same information in synchronization with each other and generate control outputs, and a memory that is an information storage means for storing information. 13, 14, and input/output interfaces (denoted as I/O in the figure) of the A system and B system that input information from the information input device 2 and output control outputs from the CPUs 11 and 12 to control targets (not shown). 15, 16. The collation circuit 17 sends information input and output to the A-system and B-system control systems to the buses D1 and D, respectively.
When the input/output information does not match, it is sent to the CPU 11 via buses D3 and D4, respectively.
, 12 to output a reset signal to stop the operation. Further, the memory 13 has a plurality of storage areas, for example, two storage areas 13-1 and 13-.
2, and the memory 14 similarly has two storage areas 14.
-1, 14-2. In addition, the information storage device 1 includes a restart circuit (not shown) that generates a reset signal for restarting the CPUs 11 and 12 when the CPUs 11 and 12 stop operating due to some abnormality.

Next, the operation will be explained. The aforementioned information such as the traveling distance and speed of the train is continuously input as the same information from the information input device 2 via the input/output interfaces 15 and 16, respectively. Next, the recording operation to the memories 13 and 14 will be explained based on the flowchart of FIG. Step 1 (
In the figure, it is marked "S", and the same applies hereafter).
Based on the input information, control information corresponding to the input information is output.

In step 2, the input information including the check code is recorded in the memories 13 and 14 as the same information. The storage areas for storing information are storage areas 13-1 and 14-1 at the time of first recording, and sequentially storage areas 13-2 and 14-2, 13-1 and 14-1, and so on.
Recording of this information is performed at regular intervals. In step 3, it is checked whether the processing operations of the CPUs 11 and 12 have been completed. If the operations are to be continued, the process returns to step 1; if the operations are to be ended, the process is to proceed to the end.

Note that steps 1 to 3 correspond to information recording means. In the unlikely event that, for example, due to noise etc., the CPU 11,
If an abnormality occurs in the information output from the bus D3, D
4, a reset signal is output to the CPUs 11 and 12, and when the CPUs 11 and 12 operate, this is detected and a reset signal for restart is output from a restart circuit (not shown) to perform restart. .

Next, the restart operation of the A-system CPU 11 will be explained based on the flowchart of FIG. 4. In step 11, a reset signal from the verification circuit 17 is input to the CPU 11, the recording operation to the memory 13 is interrupted, and the restart circuit performs restart. That is,
The CPU 11 performs initial processing without clearing the information stored in the memory 13.

In step 12, the latest information is input to check the information in the memory 13. In step 13, the correctness of the information is determined using the information and its check code. That is, if a reset signal for stopping the CPU operation is generated during recording of information, the information being recorded will be incomplete and will become fraudulent information. If this incorrect information is output, the verification circuit 17 outputs a reset signal again and the system goes down, so it is determined whether the information is correct or not so that the correct information is output. If the stored information is correct, proceed to step 17 and output the information.
If not correct, proceed to step 14.

[0014] In step 14, since it is determined that the latest information is fraudulent information, the fraudulent information is stored in the storage area 13.
-1, the information stored in another storage area 13-2 is input. In step 15, similarly to step 13, it is determined whether the information stored in the storage area 13-2 is correct or not. If the stored information is determined to be correct, the process proceeds to step 17 and the information is output; if it is not correct, the information in the two storage areas of system A is all invalid information, so the process proceeds to step 16 and the system shuts down. let

[0015] In step 17, step 13 or 1
The information determined to be correct in step 5 is output and the process returns. The output information is checked for rationality including the check code by the verification circuit 17, and then sent to the CPU 11.
, 12 use the retained information to resume control operations. Therefore, the CPUs 11 and 12 can use correct information to continue operating without system failure.

Note that steps 12 to 15 correspond to determination means, and step 17 corresponds to information output means. Further, this restart operation is the same for the B-system CPU 12 as well. According to this configuration, information is sequentially recorded in each of the two storage areas of the memories 13 and 14, and when a reset signal is generated due to noise or the like, the correctness or incorrectness of the information can be determined from the latest recorded information at the time of restarting. Since each determination is made individually, the CPU can always output the correct signal and continue operation without system failure.

[0017]

As explained above, according to the present invention, information is sequentially recorded in a plurality of storage areas of the information storage means, and when an abnormality occurs and a reset signal for restarting is generated,
Since the correct information is determined based on the latest information in a plurality of storage areas and the correct information is output, operation can be continued without system downtime, and the performance of the information storage device can be improved.

[Brief explanation of the drawing]

[Figure 1] Block diagram showing the configuration of the present invention

[Figure 2]
A block diagram showing an example of a control system equipped with an information storage device according to the present invention

FIG. 3 is a flowchart showing the recording operation of FIG. 2.

FIG. 4 is a flowchart showing the restart operation of FIG. 2;

[Explanation of symbols]

1 Information storage device 2 Information input device 11, 12 CPU 13, 14 Memory 15, 16 Input/output interface (I/O) 17
Verification circuit

Claims (1)

[Claims] [Claim 1] CP after an abnormality occurs during system operation.
In an information storage device that outputs a reset signal to U to automatically restart a CPU, the information storage means has a plurality of storage areas for storing information, and the information storage means stores information in the plurality of storage areas of the information storage means. information recording means for sequentially recording the information, and determining means for sequentially determining whether or not the information in the plurality of storage areas of the information storage means is correct or not, starting from the latest information when a reset signal for restarting the CPU is generated; An information storage device comprising: information output means for outputting information determined to be correct by the determination means.