JP2010140173A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor preventing such a situation from occurring a stop of a process of high importance. <P>SOLUTION: The information processor, which has a plurality of operation means and can detect the abnormality of at least some of the plurality of operation means by lock-step manner, includes: an output comparing means which compares the outputs of the plurality of operation means and if the outputs of the plurality of operation means are different, which writes error information to a predetermined address of a storage means when the importance of the process done by the plurality of operation means is above a predetermined level while which writes the error information to an address other than the predetermined address in the storage means when the importance of the process done by the plurality of operation means is below the predetermined level; and an error processing means which performs a predetermined error process when the error information is written in the predetermined address in the storage means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus capable of detecting at least some abnormalities among a plurality of computing means by a lockstep method.

  Conventionally, research on information processing devices in which a plurality of arithmetic means (such as CPUs) execute parallel processing based on the same clock input and can detect malfunctions and out-of-synchronization of each arithmetic means based on output differences has been advanced. Has been put to practical use. Here, the loss of synchronization means that the processing of a plurality of computing means is not completely synchronized due to the recent increase in clock frequency.

  In this regard, in a fault-tolerant computer comprising a plurality of CPU units that issue IO instructions and an IO unit that performs IO processing based on the IO instructions, each is issued from each of the plurality of CPU units. From the IO comparison unit, which outputs a match signal if they match, and outputs a mismatch signal if they do not match, and the IO comparison unit When a mismatch signal is output, it is determined whether or not the priority indicating the reliability of the CPU unit that issued the previously input IO instruction has the highest priority among the plurality of CPU units. When a match signal is output from the FT control unit that outputs a priority signal and outputs a low priority signal if it is not the highest, and the IO comparison unit, an IO command is sent to the IO unit. A fault tolerant computer having an IO control unit that transfers an IO command to the IO unit when a high priority signal is output from the FT control unit when a mismatch signal is output from the IO comparison unit Is disclosed (for example, see Patent Document 1).

A plurality of processing units that execute predetermined processes; and a plurality of abnormality detection circuits that are respectively provided in the plurality of processing units and that detect abnormality of the plurality of processing units and generate an abnormality detection signal; In response to the abnormality detection signal from any of the plurality of abnormality detection circuits, at least one normal processing unit in a normal state other than the abnormality processing unit in an abnormal state among the plurality of processing units Is disclosed for a processing apparatus including an abnormality monitoring control unit that controls to perform abnormality relief processing (see, for example, Patent Document 2). By performing the abnormal process as in the device described in Patent Document 2, it is possible to deal with a malfunction of the arithmetic means that is not simply out of synchronization.
JP 2008-225752 A JP 2007-011426 A

  By the way, in consideration of the case where this type of information processing apparatus is mounted on a vehicle, for example, when an abnormality of the arithmetic unit relating to processing with a low degree of importance as an accessory is detected, the arithmetic unit is more important. It is not preferable to stop high-level processing.

  In this regard, in the apparatus described in Patent Document 1, instruction transfer is stopped based on the priority indicating the reliability of the CPU unit, but is not based on the importance of the processing being performed. A process with higher importance may be stopped due to an abnormality in the calculation means related to a process with a lower degree.

  Further, even if an attempt is made to replace the processing of the arithmetic means in which an abnormality has occurred by the method described in the above-mentioned Patent Document 2 with a normal arithmetic means, the alternative processing may not be performed due to the processing load.

  The present invention is intended to solve such a problem, and a main object thereof is to provide an information processing apparatus capable of suppressing the occurrence of a situation where processing with high importance stops.

In order to achieve the above object, one embodiment of the present invention provides:
An information processing apparatus having a plurality of calculation means and capable of detecting at least part of the abnormality among the plurality of calculation means by a lock step method,
When the outputs of the plurality of calculation means are compared, and the outputs of the plurality of calculation means are different, the importance of the processing performed by the plurality of calculation means is greater than or equal to a predetermined level. Output comparison means for writing error information to a predetermined address, and writing error information to an address other than the predetermined address in the storage means when the importance of processing performed by the plurality of arithmetic means is less than a predetermined level; ,
Error processing means for performing predetermined error processing when error information is written at a predetermined address in the storage means;
Is an information processing apparatus.

  According to this aspect of the present invention, when the outputs of the plurality of computing means are different, the predetermined address in the storage means when the importance of processing performed by the plurality of computing means is greater than or equal to a predetermined level. Error information is written in, and when the importance of processing performed by a plurality of arithmetic means is less than a predetermined level, the error information is written to an address other than the predetermined address in the storage means, and the predetermined address in the storage means is stored. Since predetermined error processing is performed when error information is written, it is possible to suppress the occurrence of a situation in which highly important processing stops due to error processing or the like.

  The error processing means may not perform any processing corresponding to the error processing when the error information is written at an address other than the predetermined address, and does not affect processing with high importance. A degree of recovery processing may be performed.

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus which can suppress generation | occurrence | production of the situation which a process with high importance stops is provided.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the accompanying drawings.

  Hereinafter, an information processing apparatus 1 according to an embodiment of the present invention will be described. FIG. 1 is a system configuration example of an information processing apparatus 1 according to an embodiment of the present invention. The information processing apparatus 1 includes, as main components, a master CPU 10, an inspection CPU 12, a ROM 20, a RAM 22, a peripheral I / 030, an interrupt processing unit 40, an output comparison unit 50, a primary storage device 60, an error And a processing unit 70. The master CPU 10 and the inspection CPU 12 are connected to the ROM 20, RAM 22, peripheral I / 030, and interrupt processing unit 40 by a bus 80 and can mutually refer to input / output signals.

  The interrupt processing unit 40, the output comparison unit 50, and the error processing unit 70 are configured as an electronic circuit or a microcomputer.

  In addition, although master CPU10 and test | inspection CPU12 were illustrated as an example of a several calculating means, you may provide another calculating means.

  The master CPU 10 and the inspection CPU 12 are configured by an ALU (logical operation unit), a control device, a register, and the like. The master CPU 10 and the inspection CPU 12 operate based on a clock signal supplied from a common clock generator (not shown). The same input signal is input to the master CPU 10 and the inspection CPU 12. Therefore, as long as these are operating normally, the same output signal is output.

  The ROM 20 stores programs executed by the master CPU 10 and the inspection CPU 12. In the RAM 22, data to be processed when the master CPU 10 and the inspection CPU 12 execute the program is written. The primary storage device 60 is, for example, an EEPROM (Electronically Erasable and Programmable Read Only Memory) such as a flash memory, and error information is written by the output comparison unit 50.

  Peripheral I / 030 functions as an interface with the outside. When the information processing apparatus 1 is used as an in-vehicle ECU (Electronic Control Unit), the peripheral I / 030 is a multiplex communication in which vehicle signals (including vehicle speed signals, acceleration signals, yaw rate signals, steering steering angle signals, etc.) are transmitted and received. It is connected to a line or the like and transmits / receives a signal to / from a control target (engine, brake device, steering device, etc.)

  The interrupt processing unit 40 outputs various interrupt instruction signals to the master CPU 10 and the inspection CPU 12.

  The output comparison unit 50 receives an output signal output from the master CPU 10 to the ROM 20, RAM 22, peripheral I / 030, interrupt processing unit 40, and an output signal for inspection output from the inspection CPU 12. With this configuration, the output comparison unit 50 detects an abnormality in the master CPU 10 and the inspection CPU 12 by the lock step method. That is, the outputs of the master CPU 10 and the inspection CPU 12 are compared, and when the outputs of the master CPU 10 and the inspection CPU 12 are different, the abnormality of the master CPU 10 and / or the inspection CPU 12 is detected and error information is written in the primary storage device 60. . Note that the output comparison unit 50 may also receive a clock signal supplied to the master CPU 10 or the inspection CPU 12.

  The output comparison unit 50 always keeps track of the importance of processing performed by the master CPU 10 and the inspection CPU 12, and changes the write address in the primary storage device 60 based on this importance. Specifically, when the importance of processing performed by the master CPU 10 and the inspection CPU 12 is not less than a predetermined level, error information is written to a predetermined address 60A in the primary storage device 60, and the master CPU 10 and the inspection CPU 12 perform the processing. If the importance of the processing being performed is less than a predetermined level, error information is written to an address 60B other than the predetermined address 60A in the primary storage device 60.

  Ascertaining the level of importance of processing performed by the master CPU 10 and the inspection CPU 12, for example, a signal related to the degree of importance may be periodically transmitted from the master CPU 10 and / or the inspection CPU 12, or the program ID being executed, etc. The output comparison unit 50 may include a table in which importance is associated.

  The error processing unit 70 performs predetermined error processing when error information is written at a predetermined address 60A in the primary storage device 60. As the predetermined error processing, for example, processing such as shutting down and restarting the entire information processing apparatus 1 is performed. Note that the error processing unit 70 itself may perform such processing (error processing in a narrow sense), or may output an error signal to the outside and perform processing.

  On the other hand, the error processing unit 70 does not perform predetermined error processing when error information is written in an address 60B other than the predetermined address 60A in the primary storage device 60.

  With such a configuration and processing, it is possible to suppress the occurrence of a situation in which the entire apparatus is stopped by performing error processing with a minor error, and processing with high importance is stopped. Therefore, particularly when used as an in-vehicle ECU, it is possible to prevent a more important process such as route guidance from stopping due to an error related to accessory processing such as content reproduction.

  According to the information processing apparatus 1 of the present embodiment, it is possible to suppress the occurrence of a situation where processing with high importance stops.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  For example, the error processing unit 70 does not perform predetermined error processing when error information is written in an address 60B other than the predetermined address 60A in the primary storage device 60. You may perform the recovery process of the grade which does not affect.

  Specifically, the recovery process is not performed until the predetermined number of times the error information is written to the address 60B, but the recovery process may be performed when the predetermined number of times is reached.

  In addition, a process for recovering such a minor error may be included in advance in an execution program for performing a process having the next highest importance.

  The present invention can be used in the automobile manufacturing industry, the automobile parts manufacturing industry, and the like.

1 is a system configuration example of an information processing apparatus 1 according to an embodiment of the present invention.

Explanation of symbols

1 Information processing device 10 Master CPU
12 Inspection CPU
20 ROM
20A, 20B Address 22 RAM
30 Peripheral I / 0
40 interrupt processing unit 50 output comparison unit 60 primary storage device 70 error processing unit 80 bus

Claims (1)

An information processing apparatus having a plurality of calculation means and capable of detecting at least part of the abnormality among the plurality of calculation means by a lock step method,
When the outputs of the plurality of calculation means are compared, and the outputs of the plurality of calculation means are different, the importance of the processing performed by the plurality of calculation means is greater than or equal to a predetermined level. Output comparison means for writing error information to a predetermined address, and writing error information to an address other than the predetermined address in the storage means when the importance of processing performed by the plurality of arithmetic means is less than a predetermined level; ,
Error processing means for performing predetermined error processing when error information is written at a predetermined address in the storage means;
An information processing apparatus comprising:

Images