JP2983221B2 - Memory configuration setting method - Google Patents

Description

The present invention relates to a memory configuration setting method in a system having a plurality of slots in which a memory board having storage capacity information can be mounted.

(Prior art) In systems where multiple memory boards can be mounted in addition to the CPU board and I / O board, consider the total capacity of the memory boards to be mounted so that it does not exceed the allowable capacity of the system. It is necessary to add more. If a memory board having a capacity exceeding the allowable capacity of the system is mounted, the normal operation of the system is hindered, and an abnormal operation occurs during operation.

Since the capacity of a memory board is often different for each board, the work for recognizing the capacity of each memory board is very troublesome. Therefore, conventionally, it has been difficult to efficiently perform system construction, system installation, memory expansion, and the like.

(Problems to be Solved by the Invention) The present invention has been made in view of the above-described circumstances, and has been improved in that conventionally it was necessary to recognize the capacity of each mounted memory board every time a memory was added. A memory configuration setting that allows only memory boards that are suitable for the system's capacity to be automatically set to an operable state among multiple memory boards, and simplifies each task at the time of system construction, system installation, and memory expansion. The aim is to provide a method.

[Configuration of the Invention] (Means for Solving the Problems) The present invention relates to a system having a plurality of slots in which a memory board having storage capacity information can be mounted. Based on the storage capacity information obtained by this recognition and the permissible storage capacity of this system, a memory board operable in the system is selected from a plurality of mounted memory boards. An address is assigned only to the selected memory board, and the address is set to be operable.

(Operation) According to this memory configuration setting method, only a memory board suitable for the allowable capacity of the system among a plurality of memory boards is automatically set to an operable state. Therefore, at the time of system construction, system installation, and memory expansion,
The work of recognizing the relationship between the allowable capacity of the system and the total capacity of the mounted memory boards and the work of setting the switches of the memory boards can be made unnecessary.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a system configuration for realizing a memory configuration setting method according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a system bus, which has a slot in which a plurality of memory boards can be mounted, and allows data to be exchanged between the boards. 2, 3A, 3B, 4, 3C are function boards connected to the slots of the system bus 1, 2 is a CPU board, 3A to 3C are memory boards, and 4 is an I / O controller board.

The CPU board 2 has a register (R) for a system configuration management table, a memory number counter (CTR), and an enable memory number counter (EMC) in a RAM, and is connected to the slot # 01. Each of the memory boards 3A, 3B, and 3C has a bus interface function described later, and is connected to slots # 02, # 03, and # 05. The I / O controller board 4 controls input / output between the system bus 1 and the I / O device, and is connected to the slot # 04.

FIG. 2 shows the structure of transmission / reception data of a configuration recognition command which is a command on the system bus 1. In FIG. 2 (A)
The transmission data DS transmitted from the CPU board 2 to the system bus 1 is shown, and the reception data DR to be taken into the CPU 2 from the system bus 1 is shown in FIG. 2 (B).

START ADDR in the transmission data DS is data for setting a start address and a last memory board identification flag for the memory. The MMU EN transferred at the same time as the START ADDR is data for setting the memory to the enable state. When the MMU EN receives the configuration recognition command with “1”, the memory access other than the configuration recognition command You have the right to respond to commands.

The CAPACITY of the reception data DR is an area in which the capacity information sent from each memory board is placed, and this capacity information is read from a capacity / ID sending circuit 13 provided in a bus interface circuit described later in FIG. BORD ID is the area where the ID for board recognition from each memory board is placed, STAR
T ADDR is an area in which the set memory start address is read from the start address setting register 12 shown in FIG. 3 and loaded, and SLOT No. is a slot (SLOT # 01, SLOT # 02, SLO).
T @ 03,...) Is an area in which slot numbers (# 01, # 02, # 03,...) Are placed.

FIG. 3 is a block diagram showing a main configuration of a bus interface (BUS-IF) circuit provided in each of the mounted memory boards 3A, 3B, 3C.

In the figure, 11 is a flip-flop for identifying whether the memory board can respond to a memory access command other than the configuration recognition command, and 12 is a start address for setting a start address and a final memory board identification flag. A register 13 is a capacity / ID sending circuit for sending a memory capacity and a board recognition ID.

FIGS. 4 and 5 are state diagrams of the configuration register (R) constituting the system configuration management table provided in the RAM of the CPU 2, respectively. 4 shows the state of the configuration register (R) when the system configuration command shown in FIG. 1 has been sent and the system configuration shown in FIG. 1 has been recognized. FIG. 5 shows the required memory (here, 3A, 3B) shows the state of the configuration register (R) after the start address is set and the memory operation enable flag (MMU EN) is set.

Next, the operation of the system described in FIGS. 1 to 5 will be described with reference to the flowchart in FIG.

When the self-diagnosis at the time of system startup is completed, CPU2
After registering its own board recognition ID and slot number in the configuration register (R), it sends out a configuration recognition command to each slot in the slot order via the system bus 1 (step S1).

The configuration recognition command sent from CPU 2 is first sent to slot # 02. The mounting board in slot # 02 is memory 3A, and the memory capacity (CAPACITY =
“0010”) and the board identification ID of the memory (BORD ID = “10
00 ") and the slot number (SLOTNo. =" 0010 ") are returned to the CPU 2 via the system bus 1 and registered in the configuration register (R) (step S2).

Next, in step S3, it is determined whether or not there is a final board or no response. If neither the final board nor no response, the processes of steps S1 and S2 are repeatedly executed. Thereby, the information of each board is registered in the configuration register (R). Therefore, the configuration register (R) contains the fourth
Data indicating the configuration of the system as shown in the figure is registered.

Next, the CPU 2 reads the memory capacity information in the configuration register (R), determines the type of each board based on the information (step S4), and determines whether the total capacity of the memory board is within the maximum capacity of the system. (Step S5).
Here, if the area of CAPACITY is "1111", it is determined that the area is an I / O controller, and if the area is not "1111", it is determined that the area is a memory. The allowable memory capacity of the system that can operate is set from “0010” to “0100”.

The CPU 2 determines whether or not the CAPACITY of the slot # 02 is "1111" (Step S4). Slot ♯02 ie SL
Since the CAPACITY of the board with the OT No. of “0010” is “0010”, the CPU 2 recognizes that the board is a memory. Then, the capacity of the board is compared with the maximum capacity “0100” of the system (step S5). Memory board 3A
Is less than the maximum capacity, the capacity is transferred to a predetermined register as a memory board that can be enabled, and the enable memory number counter (EMC) is counted up (+1) (step S6).

Next, the enable memory number counter (EMC) and the memory number counter (CTR) are compared, and if they are equal, it is confirmed that the total capacity is larger than the system allowable minimum capacity (here, “0010”), and the memory capacity check ends. .

If the memory capacity of one board exceeds the maximum capacity of the system or is recognized as an inappropriate memory board, the CAPACITY of the corresponding slot in the configuration register (R) will be used.
Is “1111”, the slot is the start address,
The memory enable flag is excluded from being set (step S6).

Next, the CPU 2 recognizes that this board is also a memory from the CAPACITY = "0010" of the slot # 03, and compares the maximum capacity of the system with this board capacity. Also in this case, since the capacity is within the system maximum capacity, the capacity of this board is added to the register storing the memory capacity up to then, and the result is compared with the system maximum capacity. At this time, the two are "010
0 ", so the enable memory number counter (EM
C) is updated (+1), the memory capacity check is completed, and a memory enable flag, a start address, and a last memory board identification flag setting routine (step S7)
~ Enter S9).

In this process, the contents of the CAPACITY in the configuration register (R) are determined, and if the board is other than “1111”, the enable memory number counter (EMC) is counted down (−1) and the memory enable flag is set to “1”. And sends the start address to the memory board via the system bus 1.

In the configuration of FIG. 1, the memory mounted in slot # 02
When sending a configuration recognition command with the memory enable flag on 3A, the enable memory number counter (EM
C) is not "0", so the start address is START ADD
Assuming that R = “0000”, the CPU 2 sends the transmission data DS to the system bus 1. The memory 3A sends received data DR having a memory enable flag and a start address “0000” from the system bus 1 to the CPU 2 via the system bus 1.

The CPU 2 confirms that the start address in DR is equal to the start address DS at the time of transmission, and registers the start address in the configuration register (R). At this time, the next start address “0010” is calculated from the set start address and the memory capacity and held.

Next, the process proceeds to slot # 03. Since CAPACITY = "0010", the CPU 2 recognizes the memory 3B as a memory board and decrements the enable memory number counter EMC by one. At this time, EMC =
Since it becomes “0”, the start address “00
A final memory board identification flag "1" is added to the most significant bit of "10", and sent as a start address "10101" to the memory board 3B via the system bus 1 together with the memory enable flag.

After that, the memory board 3B sets the memory enable flag and the start address in the same manner as 3A, and then returns the received data DR including the start address and the last board identification flag to the CPU 2. The CPU 2 confirms that the start address in DR is equal to DS, and registers the start address of 3B in the configuration register (R).

In this way, the memories 3A and 3B are given the start address and have the right to respond to the memory access. Since the memory board 3c exceeds the system maximum allowable capacity, the memory board 3c enters a standby state.

In this way, the CPU 2 can select and operate only the necessary memory in the system.

Here, the normal state has been described as an example, but if a parity error or the like occurs in the memory 3B of the slot # 03, the CAPACITY of the slot # 03 in the configuration register (R) =
By reconfiguring the memory as “1111”, the memory 3C in the slot # 05 can be used instead of the memory 3B in the slot # 03.
Can also be used. Further, even if a failure occurs during the configuration recognition and there is a board that cannot be recognized among the boards mounted on the system bus, the system can be operated with the memory that can be recognized.

[Effects of the Invention] As described above, according to the present invention, only a memory board suitable for the allowable capacity of a system among a plurality of memory boards can be automatically set to an operable state. Simplification of each operation at the time of memory expansion can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration according to one embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a configuration recognition command used in the above embodiment, and FIG. 3 is a bus interface on the memory side in the above embodiment. Block diagram showing the configuration of FIG.
FIG. 5 and FIG. 5 are diagrams showing the state of the configuration register (R) in the above embodiment, and FIG. 6 is a flowchart for explaining the operation of the above embodiment. 1 ... system bus, 2 ... CPU, 3A, 3B, 3C ... memory, 4 ... I / O controller, R ... configuration register, CTR
…… Memory number counter, EMC …… Enable memory number counter.

Claims (1)

(57) [Claims] In a system having a plurality of slots in which a memory board having storage capacity information can be mounted, the storage capacity of each memory board mounted in the plurality of slots is recognized, and the storage obtained by this recognition is recognized. Based on the capacity information and the permissible storage capacity of this system, a memory board that can operate in the system is selected from a plurality of mounted memory boards, and addresses are assigned only to the selected memory boards to operate it. A memory configuration setting method, wherein the setting is made possible.