JPH04291613A - Circuit unit capable of connecting/disconnecting active line - Google Patents

Abstract

PURPOSE:To simply, rapidly and surely store the contents of a volatile memory at the time of disconnecting a system bus for a body from a circuit unit capable of connecting/disconnecting an active line for executing data processing in the connected state to the system bus. CONSTITUTION:The circuit unit 2 is constituted of the volatile memory 5, a disconnecting means 3 for disconnecting the unit 2 from the system bus 1, a disconnection switch 7 for controlling the means 3, a rewritable non-volatile memory 6, and an address/timing signal generating means 8 for generating a control signal including an address signal so as to transfer the contents of the memory 5 to the memory 6 correspondingly to the control of disconnection from the bus 1 by the switch 7.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hot-swappable circuit unit in a system including a hot-swappable circuit unit. When a hot-swappable circuit unit is disconnected from the main system (bus), the contents of the RAM within the circuit unit must be preserved without being lost.

0002

2. Description of the Related Art Conventionally, in order to store the contents of a RAM in a circuit unit when a circuit unit that can be hot-swappable is disconnected, for example, an RA that can supply current for a sufficiently long time has been used.
Considerations include providing an M backup battery, transferring data to a bubble memory, etc., and storing the data.

0003

However, it is troublesome to perform the above transfer operation before disconnecting the circuit unit. In addition, in recent years, RAM in circuit units
In response to the increase in capacity, large amounts of data must be reliably transferred, which poses a problem in that the time required for transfer processing also increases.

Therefore, the present invention provides a hot-swappable circuit unit that does not require any special additional operations when disconnecting the circuit unit, and that can quickly and reliably save the contents of volatile memory. The purpose is to provide.

[0005]

[Means for Solving the Problems] FIG. 1 shows the basic configuration of the present invention. In FIG. 1, 1 is a system bus of the main body, 2 is a hot-swappable circuit unit that is connected to the system bus 1 and performs data processing, 3 is a disconnection means,
5 is a volatile memory, 6 is a writable non-volatile memory, 7 is a disconnection switch, and 8 is an address/timing generating means.

The disconnecting means 3 disconnects the circuit unit 2 from the system bus (1). Disconnection switch 7
controls the separating means 3. In response to the disconnection control from the system bus 1 being performed by the disconnection switch 7, the address/timing signal generation means 8
Control signals including address signals are generated and supplied to the volatile memory 5 and the nonvolatile memory 6 so as to transfer the contents of the volatile memory 5 to the nonvolatile memory 6.

In addition to the above configuration, after the above separation,
A simple charging circuit 24 may be provided to supply power to the volatile memory 5, nonvolatile memory 6, and address/timing signal generating means 8 at least until the transfer is completed. Further, the volatile memory 5 includes a plurality of R
AM chips 111, 112, . . . may be provided, and during the transfer, the address signal may be applied simultaneously to the plurality of RAM chips 111, 112, . .

[0008] For each chip of the volatile memory 5, a plurality of EEPROMs 121 included in the nonvolatile memory (6) are provided.
, 122, . . . are connected in parallel, and generate a chip select signal for cyclically selecting the plurality of EEPROMs 121, 122, . . . for consecutive addresses in each chip of the volatile memory 5. A chip select signal generating means 15 can be provided.

[0009]

According to the present invention, when the disconnection switch 7 is operated to disconnect the circuit unit 2 from the system bus 1, the circuit unit 2 is disconnected from the system bus 1 by the disconnection means 3. At the same time, address/
The timing signal generating means 8 is activated, generates a control signal including the address signal, and supplies it to the volatile memory 5 and the nonvolatile memory 6. As a result, the contents of volatile memory 5 are transferred to nonvolatile memory 6. That is, the contents of the volatile memory 5 are automatically transferred to and saved in the nonvolatile memory 6 only by operating the disconnection switch 7.

At this time, by providing the above-mentioned simple charging circuit 24, the volatile memory 5, the non-volatile memory 6, and the address/timing signal generation means can be maintained after the above-mentioned disconnection at least until the above-mentioned transfer is completed. 8 can be powered. Furthermore, as shown in FIG. 4, the nonvolatile memory 6 requires a waiting time between writing times, so the plurality of By providing chip select signal generating means 15 for generating a chip select signal for cyclically selecting the EEPROMs 121, 122, . . . , the overall transfer time can be shortened.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram showing a schematic configuration of a hot-swappable circuit unit according to an embodiment of the present invention, which roughly corresponds to the configuration of FIG. In FIG. 2, 20 is a circuit unit, 21 is a tri-state buffer circuit, 2
2 is a bus disconnection switch, 23 is a power supply line, 24 is a charging circuit, 40 is a bus in the unit, 100 is an EEPR
OM, 110 is a RAM, 150 is an address/timing signal generation circuit, and 170 is a system bus.

Before disconnecting the circuit unit 20 from the system bus 170, the operator manually sets the bus disconnection switch 22 to the bus disconnection state. As a result, the bus disconnection signal is
70 and the local bus 40 in the circuit unit as a control signal, the tristate buffer circuit 21 enters a high impedance state. That is, the system bus 17
0 and the local bus 40 within the circuit unit.

Here, after manually operating the bus disconnection switch 22, the operator disconnects the circuit unit 2.
0 from the system bus 170, for example from a slot in the back panel. As a result, the circuit unit 20
The system will no longer be able to receive power supply, but
For example, a simple charging circuit 24 including a large-capacity capacitor can charge the RAM 110, EEPROM
100, and address/timing signal generation circuit 1
50.

[0014] Furthermore, by the above bus disconnection signal,
Address/timing signal generation circuit 150 is activated,
The contents of RAM 110 are transferred to EEPROM 100. FIG. 3 is a diagram showing a more detailed configuration of the embodiment (FIG. 2) of the present invention. In FIG. 3, 111, 112,...
・ is SRAM chip, 121, 122,... is EEP
ROM chip, 13 is an adder circuit, 141, 142,...
. is a subtraction value register, 15 is a decoding circuit, 16 is an address counter, 17 is a data bus, and 18 is an address bus.

As shown in FIG. 3, a plurality of SRAM chips 111, 112, ... (only the SRAM chips 111, 112, are not shown in FIG. 3) are connected as the RAM 110. SRAM chip 11
Each chip SRAM chip 11i of 1,112,...
For each (i=1, 2,...), multiple EEPROM12
i1, 12i2, 12i3, and 12i4 are connected in parallel.

The address bus line 18 of the system bus 170 is directly applied to the SRAM chip 111 as an address signal, and the other SRAM chips 11i (i=
2, 3, . . . ), the address bus line 18 of the system bus 170 is applied as an address signal via the adder circuit 13. In the adder circuit 13, a subtracted value register 14i (
The values held are subtracted from i=2, 3, . . . ). The value held in the subtraction value register 142 (i=2, 3,...) is equal to the total number of addresses of the SRAM chip 111, and the value held in the subtraction value register 143 (i=2, 3,...) is equal to the sum of all addresses of SRAM chips 111 and 112, and is determined similarly below. This causes the address on the address bus line 18 to
If the maximum address of the RAM chip 111 is exceeded,
When SRAM chip 112 2 is accessed and the address on address bus line 18 exceeds the maximum address value of SRAM chip 112 2 , SRAM chip 113 2 is accessed, and so on. In this way, RAM
A plurality of SRAM chips 111, 112, each having a capacity of 110,
It is getting bigger due to...

Address counter 16 and decode circuit 15 are similar to address/timing signal generation circuit 15 in FIG.
By receiving the bus disconnection signal, the address counter 16 starts counting in synchronization with the clock signal, and sequentially outputs the addresses from 0 to the maximum value of each SRAM chip 11i. Further, the decoding circuit 15 is a chip that decodes the lower 4 bits of the output of the address counter 16 and cyclically selects a plurality of (four) EEPROM chips connected to each SRAM chip 11i every time the address is updated. A select signal CSj (j=1 to 4) is generated. That is, the chip select signal CSj (j=1
~4) are EEPROMs 12i1, 12i2, 12i3, and 12i3 connected to each SRAM chip 11i, respectively.
12i4 cyclically select and write enable. The timing of these signals is shown in FIG. As a result, as shown in FIG. 6, consecutive addresses A in each SRAM chip 11i
1, B1, C1, D1, A2, B2, C2, D2...
The data of EEPROM12i1, 12i2, 12
Written cyclically to i3 and 12i4. In this way, the waiting time between write times in each EEPROM chip as shown in FIG. 4 can be effectively utilized, so that the overall data transfer efficiency is improved and the transfer time is shortened. Further, with the above configuration, data transfer from a plurality of SRAM chips 11i is performed in parallel, so that the overall data transfer efficiency is improved and the transfer time is shortened in this respect as well.

[0018]

[Effects of the Invention] As explained above, according to the present invention,
No special additional operation is required when a circuit unit is disconnected, and the contents of a volatile memory are quickly and reliably saved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of a circuit unit of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a hot-swappable circuit unit in an embodiment of the present invention.

FIG. 3 is a diagram showing a more detailed configuration of an embodiment of the present invention.

FIG. 4 is a diagram showing the timing of writing and waiting in a general EEPROM.

FIG. 5 is a diagram showing the timing relationship between the SRAM read address and the EEPROM chip select signal in the configuration of FIG. 3;

[Fig. 6] Data of each address of each SRAM in Fig. 3 and E
FIG. 2 is a diagram showing a relationship with a write destination address in an EPROM.

[Explanation of symbols]

1...System bus 2...Circuit unit 3...Disconnection means 5...Volatile memory 6...Nonvolatile memory 7...Disconnection switch 8...Address/timing generation means 111, 112,...SRAM 121, 122,... EEPROM 13... Addition circuit 141, 142,... Subtraction value register 15... Decode circuit 16... Address counter 17... Data bus 18... Address bus 20... Circuit unit 21... Tri-state buffer circuit 22... Bus isolation switch 23... Power supply Line 24...Charging circuit 40...Bus in unit 100...EEPROM 110...RAM 150...Address/timing signal generation circuit 170...System bus

Claims (1)

[Claims] 1. In a hot-swappable circuit unit that is connected to a system bus (1) of a main body and performs data processing, a volatile memory (5) and a disconnection unit that disconnects the circuit unit from the system bus (1) are provided. means (3) and a disconnection switch (7) for controlling said disconnection means (3).
), a writable non-volatile memory (6), and the contents of the volatile memory (5) in response to the disconnection control from the system bus (1) being performed by the disconnection switch (7). address/timing signal generating means () which generates and supplies control signals including address signals to the volatile memory (5) and the non-volatile memory (6) so as to be transferred to the non-volatile memory (6); 8
) A circuit unit characterized by comprising: