JPH04291096A - Semiconductor device - Google Patents

Abstract

PURPOSE:To secure the information communication line between a non-volatile memory and an external terminal interface by connecting an external terminal interface and a writable non-volatile storing means through an internal bus. CONSTITUTION:When reading and writing are performed from an external part to an EPROM 2 by an EPROM writer 8, etc., connection is performed through gate decoders 3a, 4a, and 6a and an internal address data bus 7 connected to a clock generating part, a CPU 4 and other peripheral module 6. In such a case the internal address data bus 7 is used as an address bus.data bus to connect directly the section between the EPROM 2 and an external terminal interface 5, the providing of the private wiring to read and write for the EPROM 2 becomes unnecessary, and while the wiring quantity is suppressed, the information communication line between the EPROM 2 and the external terminal interface 5 can be secured.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more specifically, for example, an MCU (micro control device).
The present invention relates to a semiconductor device with a reduced amount of internal wiring, suitable for use in fields such as lerunit.

In recent years, as a system configuration of a microcomputer, a large number of semiconductor devices such as MCUs have been developed in which a system configured by a multi-chip system is integrated into a single chip.

[0003] By converting a system configured from a multi-chip system into a single chip, the number of parts for the target system can be reduced, reducing system cost, improving reliability, reducing power consumption, etc. The benefits are as follows.

By the way, most 4-bit microcomputers are used as MCUs in control circuits for home appliances, and 8-bit and 16-bit high-performance MCUs are also used as A.
It is expected that it will be widely used in new application fields such as V equipment and OA equipment.

[0005]

[Background Art] Conventional semiconductor devices of this type include devices such as MCUs, which are typified by one-chip microcomputers built into control circuits of home appliances such as fully automatic washing machines and vacuum cleaners. .

[0006] In such a semiconductor device, a CPU (ce
central processing unit )+R
OM (read only memory) + RAM (
It is constructed by integrating a multi-chip system consisting of multiple modules such as random access memory (random access memory) + peripherals into one chip, and by integrating the system into one chip, external signals can be exchanged between multiple modules. The signal that was previously processed as an internal signal becomes an internal signal, improving processing speed.

[0007]Generally, the program for controlling the operation of the CPU is stored in the ROM, but recently, in order to provide better products, there have been many program changes due to detailed version upgrades, and the ROM is For example, EPROM (erasab
It uses writable non-volatile memory such as LE programmable ROM.
This reduces the program writing processing time.

Furthermore, in the recent market, as applied equipment becomes lighter, thinner, and smaller, there is a demand for system simplification and lower cost. Therefore, unnecessary terminals and unnecessary modules are removed from the general-purpose EPROM, resulting in a customized product.

[0009]

[Problems to be Solved by the Invention] However, such conventional semiconductor devices have a built-in customized EPROM (hereinafter referred to as customized EPROM) in order to store a program for controlling the operation of the CPU. (EPROM is called a built-in EPROM), so when an external EPROM writer or the like writes or reads a program to the built-in EPROM in a semiconductor device, the writing and reading are in the same format as a general-purpose EPROM. The problem was that it could not be done.

Therefore, the EPRO inside the semiconductor device can be accessed from the outside.
When accessing M, it is conceivable to provide an information transmission path that directly connects the external terminal interface of the semiconductor device and the built-in EPROM so that writing and reading can be performed in the same format as a general-purpose EPROM. To write to and read from, at least an address bus and a data bus are required, so placing all these buses between the external terminal interface and the built-in EPROM will require a large amount of wiring area. As a result, there is a problem in that the cost increases due to an increase in device area.

[Objective] Therefore, it is an object of the present invention to provide a semiconductor device that secures an information transmission path between a writable nonvolatile memory and an external terminal interface while suppressing the amount of wiring.

0012

[Means for Solving the Problems] In order to achieve the above object, a semiconductor device according to the present invention includes an internal bus serving as a common transmission path within a system, and a plurality of internal buses that control the input/output of address signals and data signals to the internal bus. a gate decoder,
In a semiconductor device comprising a plurality of modules each connected to the plurality of gate decoders and connected to the internal bus via the gate decoder, the module includes:
Arithmetic control means for controlling at least the inside of the system;
A writable nonvolatile storage means for storing predetermined information for the operation of the arithmetic control means, and an external terminal interface for externally reading and writing predetermined information from the writable nonvolatile storage means. and, when reading or writing from or to the writable non-volatile storage means, disconnects the internal bus from a gate decoder connected to a module other than the writable non-volatile storage means and the external terminal interface. , the external terminal interface and the writable nonvolatile storage means are connected via the internal bus.

[0013] Further, in the case where one of the modules is provided with a clock generation section that supplies multiphase clock signals to each module based on an external clock signal, and reading and writing is performed on the writable nonvolatile storage means. , stopping all the multiphase clocks supplied by the clock generation unit to the writable nonvolatile storage means and the gate decoder connected to a module other than the external terminal interface to bring the gate decoder into an inactive state. By doing so, the gate decoder and the internal bus are disconnected from each other.

[0014]

[Operation] In the present invention, when reading or writing is performed on a writable non-volatile storage means, the connection between the writable non-volatile storage means and a gate decoder connected to a module other than an external terminal interface and an internal bus. is disconnected, and the external terminal interface and writable nonvolatile storage means are connected via an internal bus.

That is, when reading or writing is performed on the writable non-volatile storage means, the internal bus is used as an information transmission path that directly connects the external terminal interface and the writable non-volatile storage means. This eliminates the need for dedicated wiring for reading and writing to non-volatile storage means, which reduces the amount of wiring while ensuring an information transmission path between the writable non-volatile memory and the external terminal interface. be done.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. 1 and 2 are diagrams explaining the principle of a semiconductor device according to the present invention.

First, the configuration will be explained. The semiconductor device 1 is
Broadly divided, EPROM2, clock generator 3, CPU4
, an external terminal interface 5, other peripheral modules 6, an internal address/data bus 7, and gate decoders 2a to 6a.
The ROM 2, clock generator 3, CPU 4, external terminal interface 5, and other peripheral modules 6 are connected to an internal address/data bus 7 via gate decoders 2a to 6a, respectively.

Note that 8 is an EPR0M writer. Next, the operation will be explained based on FIG. 2. First, in the normal operation mode, processing is executed by the CPU 4 based on a program stored in the EPROM 2, and all information transmission in this case is performed via the internal address/data bus 7.

[0019] Then, EPRO is input to EPROM2 from the outside.
When reading and writing is performed by M writer 8 etc., the operation mode changes from normal operation mode to EPROM mode,
Modules other than the EPROM 2 and the external terminal interface 5, that is, the clock generator 3, the CPU 4,
Gate decoders 3a, 4a, 6a connected to other peripheral modules 6 are disconnected from internal address/data bus 7, and only EPROM 2 and external terminal interface 5 are connected via internal address/data bus 7. Ru.

That is, the internal address/data bus 7 is used as an address/data bus that directly connects the EPROM 2 and the external terminal interface 5.
It is no longer necessary to provide dedicated wiring for reading and writing to EPROM2, and while reducing the amount of wiring, it is possible to
2 and the external terminal interface 5 can be secured.

FIG. 3 is a block diagram showing the overall configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a block diagram for explaining an example of the operation of FIG. 3. In addition, in FIGS. 3 and 4, the same numbers as those attached to the principle explanatory diagrams shown in FIGS. 1 and 2 indicate the same parts.

In this embodiment, EPROM 2 is externally programmed with EP.
A gate decoder 3a, which is connected to the clock generator 3, the CPU 4, and other peripheral modules 6 when reading and writing is performed by the ROM writer 8 or the like, that is, when the operation mode changes from the normal operation mode to the EPROM mode.
The control for disconnecting the internal address/data bus 7 from the internal address/data bus 7 will be explained in detail.

As shown in FIG. 3, the clock generator 3
A multiphase clock signal is supplied to each module based on a clock signal supplied from outside the semiconductor device 1 (not shown).

That is, as shown in FIG. 4, when the EPROM writer 8 is connected to the external terminal interface 5 to read and write to the EPROM 2, the gate decoder 2a of the EPROM 2 is transmitted from the external terminal interface 5.
An EPROM mode signal is output.

When the EPROM mode signal is output, the usage status of the internal address/data bus 7 is checked;
When it is confirmed that it is in an unused state, EPROM2,
and gate decoders 3a, 4a, 6 connected to modules other than the external terminal interface 5, that is, the clock generator 3, the CPU 4, and other peripheral modules 6.
All the multiphase clocks supplied from the clock generator 3 to a are stopped, and the gate decoders 3a, 4a, 6a are brought into an inactive state.
, 6a and the internal address/data bus 7 are disconnected.

In this way, in this embodiment, when reading and writing to the writable non-volatile storage means, the internal bus is used as an information transmission path that directly connects the external terminal interface and the writable non-volatile storage means. This makes it possible to eliminate the need for dedicated wiring for reading and writing to the writable nonvolatile storage means.

Therefore, it is possible to secure an information transmission path between the writable nonvolatile memory and the external terminal interface while suppressing the amount of wiring. Note that the above embodiment uses EPRO as a writable nonvolatile storage means.
Although the explanation was given using M as an example, it is not limited to this.
Other writable non-volatile storage means include EEPROM (Electrical Eraser).
possible programmable ROM).

[0028]

[Effects of the Invention] In the present invention, when reading and writing to writable nonvolatile storage means, the internal bus is used as an information transmission path that directly connects the external terminal interface and the writable nonvolatile storage means. This makes it possible to eliminate the need for dedicated wiring for reading and writing from and to the writable nonvolatile storage means.

Therefore, it is possible to secure an information transmission path between the writable nonvolatile memory and the external terminal interface while suppressing the amount of wiring.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of a semiconductor device of the present invention.

FIG. 2 is a diagram illustrating the principle of the semiconductor device of the present invention.

FIG. 3 is a block diagram showing the overall configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a block diagram for explaining the operation example of FIG. 3;

[Explanation of symbols]

1 Semiconductor device 2 EPROM 2a Gate decoder 3 Clock generation section 3a Gate decoder 4 CPU 4a Gate decoder 5 External terminal interface 5a Gate decoder 6 Other peripheral modules 6a Gate decoder 7 Internal bus 8 EPROM writer

Claims (2)

[Claims] 1. An internal bus serving as a common transmission path within the system, a plurality of gate decoders that control the input/output of address signals and data signals to the internal bus, and a plurality of gate decoders each connected to the plurality of gate decoders and connected to the plurality of gate decoders respectively. a plurality of modules connected to the internal bus via gate decoders;
In the semiconductor device, the module includes at least an arithmetic control means for controlling the inside of the system, a writable nonvolatile storage means for storing predetermined information for the operation of the arithmetic control means, and a writable an external terminal interface for reading and writing predetermined information from the outside into the nonvolatile storage means, and when reading and writing from the writable nonvolatile storage means, the writable nonvolatile storage means , and disconnecting the internal bus from a gate decoder connected to a module other than the external terminal interface, and connecting the external terminal interface and the writable nonvolatile storage means via the internal bus. Characteristic semiconductor devices. 2. In the case where one of the modules includes a clock generation section that supplies multiphase clock signals to each module based on an external clock signal, and reads and writes to the writable nonvolatile storage means. , stopping all the multiphase clocks supplied by the clock generation unit to the writable nonvolatile storage means and the gate decoder connected to a module other than the external terminal interface to bring the gate decoder into an inactive state. 2. The semiconductor device according to claim 1, wherein the gate decoder and the internal bus are disconnected by doing so.