JPH04290011A - Phaselocked loop circuit - Google Patents

Abstract

PURPOSE:To prevent a jump of a frequency of a VCO at the restoration of an input clock by using a N/2 frequency division pulse of the VCO so as to keep an output of a coupling circuit to a required control voltage level at the clock input interruption. CONSTITUTION:When an input interruption detection circuit 1 detects a clock interrupt, A phase comparator circuit 4 segmenting a signal with a pulse of 1/N frequency division via a 1/N frequency divider circuit 2 segments an output of a VCO 9 by using a pulse of N/2 frequency division by a N/2 frequency divider circuit 10. On the other hand, a phase comparator 5 inhibits the set of an FF 21 at the interruption and uses the N/2 frequency division pulse of the VCO 9 to repeat the inversion of a FF 21. Thus, a duty of an input pulse to a coupling circuit 8 is close to 50% and an output level of the circuit 8 reaches a level at which the VCO 9 outputs a center frequency and jump of an output frequency is prevented when the input clock is restored.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention is applied to digital transmission equipment. In particular, it relates to PLL circuits.

0002

[Prior Art] A conventional double-loop PLL circuit is shown in FIG.
As shown in the figure, there is an input disconnection detection circuit 1 that monitors the input state of the input clock, an N frequency divider circuit 2 that divides the input clock by N, and an N frequency divider circuit that divides the output of the voltage controlled oscillator 9 by N. Pulse output from frequency divider circuit 15 and N frequency divider circuit 2
A phase comparator circuit 4 that compares the phases of pulses output from the
and a phase comparison circuit 5, and a low-pass filter 6 for smoothing the outputs of the phase comparison circuit 4 and the phase comparison circuit 5, respectively.
and a low-pass filter 7, a coupling circuit 8 that couples the outputs of the low-pass filters 6 and 7, and an analog that selects the output of the coupling circuit 8 and the output of the reference voltage generation circuit 13 based on the output of the input disconnection detection circuit 1. switch 1
4, and a voltage controlled oscillator 9 that changes the oscillation frequency according to the output of the analog switch 14. When the input clock is not disconnected, this circuit controls the oscillation frequency of the voltage controlled oscillator 9 based on the result of phase comparison between a pulse obtained by dividing the input clock by N and a pulse obtained by dividing the output of the voltage controlled oscillator 9 by N. , when the input clock is off, the oscillation frequency of the voltage controlled oscillator 9 is controlled by the output of the reference voltage generating circuit 13.

0003

[Problem to be solved by the invention] In this conventional example circuit,
While the input clock is disconnected and the input of the voltage controlled oscillator is being supplied from the reference voltage generation circuit, the output of the coupling circuit becomes the power supply voltage level or ground level, and the clock is restored from the input clock disconnected state and the voltage increases. When the input of the controlled oscillator is switched to be supplied from the output of the coupling circuit, if the switching speed is fast, the output level of the coupling circuit has not recovered to the steady state, so the output frequency of the voltage controlled oscillator will jump. be.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase-locked loop circuit that eliminates such drawbacks and can prevent frequency jumps in a voltage controlled oscillator.

[0005]

[Means for Solving the Problems] The present invention provides a voltage controlled oscillator, N frequency dividing means for dividing the output of the voltage controlled oscillator by N, and a pulse output from the N frequency dividing means and a predetermined pulse. A first phase comparison circuit and a second phase comparison circuit are provided, and the outputs of the first phase comparison circuit and second phase comparison circuit are respectively smoothed, and the smoothed signals are combined and sent to the voltage controlled oscillator. A coupling means for providing a signal that changes the oscillation frequency, and a coupling means for applying the input clock as a signal that changes the oscillation frequency.
In a phase-locked loop circuit comprising an N frequency dividing circuit that divides the frequency and an input disconnection detection circuit that monitors the input state of the input clock, the N frequency dividing means divides the output of the voltage controlled oscillator by N/2. It consists of an N/2 frequency divider circuit that divides the frequency and a 2 frequency divider circuit that divides the output of the N/2 frequency divider circuit by 2. When the input disconnection detection circuit detects a clock disconnection, the
The first phase comparator circuit includes a selector for selecting a pulse output by the frequency divider by 2 circuit, and a selector for selecting a pulse output by the N frequency divider when no clock disconnection is detected, and the first phase comparator circuit selects a pulse output by the N frequency divider. The pulse to be output is given to the input terminal,
The second phase comparison circuit includes a flip-flop whose clock terminal receives the pulse output from the selector, and the second phase comparison circuit includes a differentiating circuit that differentiates the pulse obtained by dividing the output of the voltage controlled oscillator by N, and a signal output from the differentiating circuit. A prohibition circuit that prohibits passage of the input clock when the input clock is disconnected and permits it when the input clock is disconnected, and a signal output from this prohibition circuit is applied to the set terminal, and the output is a pulse obtained by dividing the input clock by N. The present invention is characterized in that it includes a flip-flop in which a signal is inverted.

[0006]

[Operation] When the input clock is not interrupted, one phase comparator circuit of the double-loop type phase-locked loop circuit punches out a pulse obtained by dividing the output of the voltage controlled oscillator by N with a pulse obtained by dividing the input clock by N. Further, a pulse obtained by frequency-dividing the output of the voltage-controlled oscillator by N is punched out by a pulse obtained by dividing the frequency of the output of the voltage-controlled oscillator by N/2. Switching between these two pulses is performed by a selector. The other phase comparator circuit sets a flip-flop by differentiating the pulse obtained by dividing the output of the voltage controlled oscillator by N when the input clock is not interrupted, and inverts the flip-flop at the rising edge of the pulse obtained by dividing the input clock by N. Furthermore, when the input clock is off, setting of the flip-flop is prohibited, and the flip-flop is repeatedly inverted using a pulse obtained by dividing the output of the voltage controlled oscillator by N/2. The outputs of these two phase comparator circuits are combined via a low-pass filter and supplied to the voltage controlled oscillator as its control voltage.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of this embodiment.

As shown in FIG. 1, this embodiment includes a voltage controlled oscillator 9, an N frequency dividing means for dividing the output of the voltage controlled oscillator 9 by N, and a pulse output from the N frequency dividing means and a predetermined frequency. a phase comparator circuit 4 and a phase comparator circuit 5 to which a pulse of
A coupling circuit 8, a low-pass filter 6, and a low-pass filter 7, which are coupling means for smoothing the outputs of the input terminals and coupling the smoothed signals and supplying the smoothed signals to the voltage-controlled oscillator 9 as a signal for changing its oscillation frequency; The N frequency dividing circuit 2 divides the frequency of the input clock by N, and the input disconnection detection circuit 1 monitors the input state of the input clock. , consists of an N/2 frequency divider circuit 10 that frequency divides the output of the voltage controlled oscillator 9 by N/2, and a 2 frequency divider circuit 11 that frequency divides the output of the N/2 frequency divider circuit 10 by 2. The circuit 1 includes a selector 3 that selects the pulse output from the N/2 frequency divider circuit 10 when the circuit 1 detects a clock disconnection, and selects the pulse output from the N frequency divider circuit 2 when the circuit 1 does not detect a clock disconnection. , the phase comparator circuit 4 includes a flip-flop 2 whose input terminal receives the pulse output from the N frequency dividing means, and whose clock terminal receives the pulse output from the selector 3.
1, the phase comparator circuit 4 includes a differentiation circuit 20 for differentiating a pulse obtained by dividing the output of the voltage controlled oscillator 9 by N, and a differentiation circuit 20 that prohibits passage of the signal output from the differentiation circuit 20 when the input clock is disconnected. A prohibition circuit 18 that enables when the input clock is disconnected, and a flip-flop 22 in which the signal output from the prohibition circuit 18 is applied to a set terminal and the output signal is inverted by a pulse obtained by dividing the input clock by N.
Equipped with

Next, the operation of this embodiment will be explained. As shown in FIGS. 3 and 5, when the input clock is not cut off, the phase comparator circuit 4 punches out the pulse obtained by dividing the output of the voltage controlled oscillator 9 by N with the pulse obtained by dividing the input clock by N when the input clock is cut off. In this case, the output of the voltage controlled oscillator 9 is punched out using a pulse whose frequency is divided by N/2. Further, as shown in FIGS. 4 and 6, when the input clock is not disconnected, the phase comparator circuit 5 differentiates the pulse obtained by dividing the output of the voltage controlled oscillator 9 by N and sets a flip-flop.
It is inverted at the rising edge of the pulse obtained by dividing the input clock by N, and when the input clock is disconnected, the setting of the flip-flop is prohibited, and the inversion operation of the flip-flop is performed by the pulse of the frequency divided by N/2 of the voltage controlled oscillator 9. It is a repeating structure. In this way, the operation of the two phase comparison circuits 4 and 5 makes it possible to bring the duty of the pulse input to the coupling circuit 8 close to 50% even when the input clock is off, so that the output level of the coupling circuit 8 can be controlled by voltage control. If the oscillator 9 is maintained at a level at which it can output the center frequency and the input clock is restored and the input of the voltage controlled oscillator 9 is switched to the output of the coupling circuit 8, the output of the voltage controlled oscillator 9 will not cause a frequency jump. It can be prevented.

0010

[Effects of the Invention] As explained above, the present invention inputs the N/2 frequency-divided pulse of the voltage controlled oscillator instead of inputting the N-divided pulse of the input clock to two phase comparator circuits when the clock input is interrupted. This makes it possible to maintain the output of the coupling circuit during clock input interruption at a voltage level such that the oscillation frequency of the voltage controlled oscillator is close to the center frequency, so that when the input clock is restored, the oscillation frequency of the voltage controlled oscillator is It has the effect of preventing jumping.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing the configuration of a conventional example.

FIG. 3 is a circuit diagram showing a partial configuration of an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a partial configuration of an embodiment of the present invention.

FIG. 5 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 6 is a flowchart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

1 Input disconnection detection circuit 2 N frequency divider circuit 3 Selector 4 Phase comparison circuit 5 Phase comparison circuit 6 Low pass filter 7 Low pass filter 8 Coupling circuit 9 Voltage controlled oscillator 10 N/2 frequency divider circuit 11 Divide-by-2 circuit 13 Reference voltage generation circuit 14 Analog switch 15 N frequency divider circuit 16 Phase comparison pulse 17 Phase comparison pulse 18 Prohibited circuit 19 Clock input disconnection information 20 Differential circuit 21 Flip-flop 22 Flip-flop

Claims (1)

[Claims] 1. A voltage controlled oscillator, N frequency dividing means for dividing the output of the voltage controlled oscillator by N, a first phase comparator circuit to which a pulse output from the N frequency dividing means and a predetermined pulse are applied, and The outputs of the second phase comparison circuit, the first phase comparison circuit, and the second phase comparison circuit are each smoothed, and the smoothed signals are combined and given to the voltage controlled oscillator as a signal for changing its oscillation frequency. a coupling means, an N-divider circuit that divides the input clock by N;
In the phase-locked loop circuit including an input disconnection detection circuit that monitors the input state of the input clock, the N frequency dividing means divides the output of the voltage controlled oscillator by N/2.
It consists of a /2 frequency divider circuit and a 2 frequency divider circuit that divides the output of the N/2 frequency divider circuit by 2. When the input disconnection detection circuit detects a clock disconnection, the N/2 frequency divider circuit The first phase comparator circuit is provided with a selector that selects a pulse to be outputted, and a selector that selects a pulse to be outputted by the N frequency dividing circuit when a clock disconnection is not detected, and the first phase comparison circuit is configured to receive the pulse outputted from the N frequency dividing means as input. The second phase comparator circuit includes a flip-flop that is applied to a terminal and a pulse output from the selector is applied to a clock terminal, and the second phase comparison circuit is a differentiation circuit that differentiates a pulse obtained by dividing the output of the voltage controlled oscillator by N; A prohibition circuit that prohibits the passage of the signal output from the circuit when the input clock is disconnected and allows it when the input clock is disconnected, and a signal output from this prohibition circuit is applied to the set terminal and the input clock is divided by N. 1. A phase-locked loop circuit characterized by comprising a flip-flop whose output signal is inverted by a pulse generated by the phase-locked loop circuit.