JPH04289594A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate a futile power consumption by making a through current not to flow between self and another semiconductor memory devices even in the case of parallel connection. CONSTITUTION:This device is provided with a control circuit 38 for output circuit active period to make the active period of output circuit shorter than the chip selecting period per one access.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices such as ROMs that are used in parallel connection.

0002

2. Description of the Related Art Conventionally, a ROM, the main part of which is shown in FIG. 7, has been proposed. In the figure, 1 is the chip body, 21 to 2n are address signal input terminals to which address signals A1 to An are input, 3 is a sense amplifier, 4 is a chip select signal input terminal to which a chip select signal CS bar is input, 5 to 11 is pMOS, 12 to 18 are nMOS,
19 is an output terminal to which the output signal OUT is output, p
The output circuit 20 is composed of MOS 11 and nMOS 18, and includes pMOSs 5 to 7, 9 and nMOSs 12, 13,
15 and 16 constitute an output circuit active period control circuit 21.

In this ROM, when the chip select signal CS bar is set to the H level, the node 22 goes to the L level.
level, node 23 becomes H level. As a result, pM
OS7 is turned on, nMOS15 is turned off, and node 24 becomes H level. Also, pMOS9 is OFF, n
The MOS 16 is turned on and the node 25 goes to L level. Therefore, in this case, pMOS11, nMO
Since both S18 are turned off, the output terminal 19 is in a high impedance state regardless of the output of the sense amplifier 3.

After that, the chip select signal CS becomes L.
When the level is inverted, the node 22 becomes the H level and the node 23 becomes the L level. As a result, pMOS7 is turned off.
, nMOS15 is turned on, pMOS7, 8 and nM
The circuit consisting of OS14 and 15 is pMOS8 and nMOS
This is equivalent to an inverter consisting of 14 inverters. Therefore, the output of the sense amplifier 3 is supplied to the gate of the pMOS 11 via an inverter made up of the pMOS 8 and the nMOS 14.

[0005] Also, in this case, pMOS9 is ON, nM
OS16 turns OFF, pMOS9, 10 and nMO
The circuit consisting of S16 and 17 is pMOS10 and nMOS
This is equivalent to an inverter consisting of 17 inverters. Therefore, the output of the sense amplifier 3 is supplied to the gate of the nMOS 18 via an inverter made up of the pMOS 10 and the nMOS 17.

In this case, when the output of the sense amplifier 3 is at the H level, the voltages at the nodes 24 and 25 are at the L level, so the pMOS 11 is turned on and the nMOS 18 is turned on.
It becomes an FF, and an H level is output to the output terminal 19. Furthermore, when the output of the sense amplifier 3 is at L level, the voltages at nodes 24 and 25 are at H level, so pMOS1
1 is OFF, nMOS18 is ON, and output terminal 1
9 outputs an L level.

FIG. 8 is a time chart showing the operation of such a ROM, and shows the relationship among the address signals A1 to An, the chip select signal CS bar, and the output data OUT.

By the way, such ROMs are sometimes used in parallel connection, and FIG. 9 shows two ROMs 26 and 27.
This shows the case when connected in parallel. In this case, the address signals A1 to An and the chip select signal CS1 bar,
Chip select signal CS2 bar and output data OUT1
, OUT2 are ideally as shown in FIG.

[0009]

However, when the conventional ROMs 26 and 27 are connected in parallel as shown in FIG. 9, if there are variations in the delay characteristics of the ROMs 26 and 27, the address signals A1 to An and the chip select The relationship between the signal CS1 bar, the chip select signal CS2 bar, and the output data OUT1 and OUT2 may end up as shown in FIG. 11. That is, ROM26 and 27
There is a problem in that the periods in which the output circuit is active overlap, and for example, a through current I flows as shown in FIG. 12, resulting in wasted power consumption. In addition,
In FIG. 11, the period T shows a case where the periods in which the output circuits of the ROM 26 and the ROM 27 are active overlap.

[0010] In view of this point, the present invention prevents a through current from flowing between semiconductor memory devices and other semiconductor memory devices even when they are used in parallel connection, thereby preventing wasted power consumption. The purpose is to provide a semiconductor memory device.

[0011]

[Means for Solving the Problems] A semiconductor memory device according to the present invention is an improvement on a semiconductor memory device in which chips are selected by a chip select signal, and the active period of an output circuit is made shorter than the chip select period per access. It is constructed by providing an output circuit active period control circuit to shorten the output circuit active period.

0012

[Operation] In the present invention, the active period of the output circuit can be made shorter than the chip select period per access, so when these are connected in parallel, variations in the delay characteristics of semiconductor memory devices are avoided. Even if there is, it is possible to avoid overlapping the periods in which the output circuits are active.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment and application example of the present invention will be described below with reference to FIGS. 1 to 6. Note that this embodiment is an improvement on the ROM shown in FIG. 7, and parts in FIG. 1 corresponding to those in FIG. 7 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

Embodiment of the present invention: FIGS. 1 and 2 FIG. 1 is a diagram showing the main part of an embodiment of the present invention, and this embodiment is shown in FIG. 7.
The difference from the conventional ROM shown in is that pMOS28 to 32
, 5-7, 9 and nMOS33-37, 12, 13, 1
Output circuit active period control circuit 38 consisting of 5 and 16
RO in Figure 7.
It is configured similarly to M.

In this embodiment, when the chip select signal CS bar is set to H level, the pMOS 32 becomes O
Since the FF and nMOS37 are turned on, the node 22 becomes L.
become the level. As a result, pMOS7 is turned on, and nMOS
15 becomes OFF, and node 24 becomes H level. In addition, in this case, since the node 23 is at H level, pM
OS9 turns OFF, nMOS16 turns ON, and node 2
5 becomes L level. Therefore, in this case, pM
Since both the OS 11 and the nMOS 18 are turned off, the output terminal 19 is in a high impedance state regardless of the output of the sense amplifier 3.

After that, the chip select signal CS becomes L.
When the level is reversed, pMOS32 is immediately turned on, but the level of node 39 is the same as that of pMOS28 and nMOS.
33, the delay time of the inverter consisting of pMOS29 and nMOS34, and pM
It becomes L level with a delay of the delay time of the inverter made up of OS30 and nMOS35 and the delay time of the inverter made up of pMOS31 and nMOS36, and as a result,
The pMOS5 is turned on, and the level of the node 22 becomes H level.

[0017] As a result, pMOS7 is OFF and nMOS7 is OFF.
15 becomes ON, pMOS7, 8 and nMOS14,
A circuit consisting of 15 is equivalent to an inverter consisting of 8 pMOSs and 14 nMOSs. Therefore, the output of the sense amplifier 3 is supplied to the gate of the pMOS 11 via an inverter made up of the pMOS 8 and the nMOS 14.

Further, in this case, since the node 23 becomes L level, the pMOS9 is turned on and the nMOS16 is turned off, so that the circuit made up of the pMOS9, 10 and the nMOS16, 17 becomes equivalent to an inverter made up of the pMOS10 and nMOS17. Therefore, the output of the sense amplifier 3 is supplied to the gate of the nMOS 18 via an inverter made up of the pMOS 10 and the nMOS 17.

Here, when the output of the sense amplifier 3 is at H level, nodes 24 and 25 are at L level, so p
The MOS 11 is turned on, the nMOS 18 is turned off, and an H level is output to the output terminal 19. Furthermore, when the output of sense amplifier 3 is at L level, nodes 24 and 25 are at H level.
level, so pMOS11 turns OFF and nMOS1
8 is turned on, and an L level is output to the output terminal 19.

FIG. 2 is a time chart showing the operation of this embodiment. In this embodiment, when the chip select signal CS bar is inverted from H level to L level,
The start timing of the output circuit active period is determined by the delay time of the inverter consisting of pMOS28 and nMOS33, and the pMOS28 and nMOS33.
The inverter delay circuit consisting of S29 and nMOS34, the delay time of the inverter consisting of pMOS30 and nMOS35, and the delay time of the inverter consisting of pMOS31 and nMOS36 are delayed compared to the case of the ROM shown in FIG. 7, and the output circuit active period ends. is the same as in FIG. That is, in this embodiment, the active period of the output circuit is made shorter than the chip select period per one access. Note that in FIG. 2, the broken line indicates the case of the conventional ROM shown in FIG.

First application example of one embodiment of the present invention...FIG. 3,
Figure 4 Figure 3 shows the first application example of this embodiment, that is, the ROM of this embodiment.
40 and 41 are connected in parallel. In this case, address signals A1 to An and chip select signal CS
The relationship between bar 1, bar chip select signal CS2, and output data OUT1 and OUT2 is as shown in FIG. In addition, in FIG. 4, the broken line indicates the conventional ROM shown in FIG.
This shows the case where . In this way, according to this embodiment, the active period of the output circuit is configured to be shorter than the chip select period per access, so even if there is some variation in the delay characteristics of the ROMs 40 and 41, , it is possible to avoid overlapping the periods in which the output circuits are active. therefore,
It is possible to prevent a through current from flowing between the output circuits of the ROMs 40 and 41, and to prevent unnecessary power consumption.

Second application example of one embodiment of the present invention...FIG. 5,
FIG. 6 shows a second application example of this embodiment, that is, a ROM of this embodiment.
42 to 45 are connected in parallel. In this case, NAND circuits 46 to 46 correspond to ROMs 42 to 45.
49 are provided, and two chip select signals CS1, C
It is configured to decode S2 and select a chip. Note that the NAND circuits 46 to 49 are connected to the ROMs 42 to 45.
It can also be built into.

FIG. 6 is a time chart showing the operation of this second application example. In this second application example, address signals A1 to An and chip select signals CS1 and CS
2 is supplied at the timing shown in FIGS. 6a to 6c, the outputs OUT1 to 4 of the ROMs 42 to 45 are as shown in FIG.
d to 6g, and the output data OUT outputted to the output terminal 50 is as shown in FIG. 6h. In addition,
In FIG. 6, the broken line indicates the case where the conventional ROM shown in FIG. 7 is used. Therefore, also in this case, RO
Even if there is some variation in the delay characteristics of M42 to M45, the periods during which the output circuits are active do not overlap. Therefore, a through current can be prevented from flowing between the output circuits of the ROMs 42 to 45, and unnecessary power consumption can be prevented.

In the above-described embodiment, the present invention was applied to a ROM, but the present invention can also be widely applied to a RAM, etc.

[0025]

Effects of the Invention According to the present invention, the active period of the output circuit can be reduced by adopting a configuration in which an output circuit active period control circuit is provided that makes the active period of the output circuit shorter than the chip select period per access. Since it can be made shorter than the chip select period per access, when the semiconductor memory devices of the present invention are connected in parallel, even if there are variations in the delay characteristics of the semiconductor memory devices, the output circuit remains active. Since it is possible to avoid overlapping the periods where , it is possible to prevent a through current from flowing between the semiconductor memory devices and other semiconductor memory devices, and it is possible to prevent wasteful power consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing essential parts of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of an embodiment of the present invention.

FIG. 3 is a first application example of an embodiment of the present invention.

FIG. 4 is a time chart showing the operation of a first application example of an embodiment of the present invention.

FIG. 5 is a diagram showing a second application example of an embodiment of the present invention.

FIG. 6 is a time chart showing the operation of a second application example of an embodiment of the present invention.

FIG. 7 is a diagram showing main parts of a conventional ROM.

FIG. 8 is a time chart showing the operation of a conventional ROM.

FIG. 9 is a diagram showing an example of application of a conventional ROM.

FIG. 10 is a time chart showing the operation of a conventional ROM application example.

FIG. 11 is a time chart for explaining problems that conventional ROMs have.

FIG. 12 is a diagram for explaining problems that conventional ROMs have.

[Explanation of symbols]

1 Chip body 21~2n　Address signal input terminal 3 Sense amplifier 4 Chip select signal input terminal 19 Output terminal 20 Output circuit

Claims (1)

[Claims] 1. A semiconductor memory device whose chip is selected by a chip select signal, the semiconductor memory device comprising an output circuit active period control circuit that makes the active period of the output circuit shorter than the chip select period per access. A semiconductor memory device characterized by: