JPH04287377A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which can be improved in such a performance as driving ability, etc., and its manufacturing method. CONSTITUTION:A MOS transistor is constituted in such a way that the first n-type source and drain regions 6a and 6b are formed on the surface of a p-type silicon substrate 1 and the first polycrystalline silicon gate electrode 5 is formed in the first channel region between the regions 6a and 6b with the first gate oxide film 4 in between. Then a TFT type transistor is constituted in such a way that a p-type polycrystalline silicon layer 8 is formed on the electrode 5 with the second gate oxide film 7 in between and the second polycrystalline silicon gate electrode 10 is formed in the second channel region between the second n<+>-type source and drain regions 11a and 11b at both ends of the layer 8 with the third gate oxide film 9 in between.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a field effect transistor and a method of manufacturing the same.

0002

[Prior Art] The mainstream of current field effect transistors is MOS (Metal Oxide Semiconductor).
It is a conductor ) type transistor. FIG. 6 shows a cross-sectional view of a MOS transistor with a conventional structure. For example, a field oxide film 22 is formed on a p-type silicon substrate 21, and a p + -type channel stopper region 23 is formed under this field oxide film 22 for element isolation. Then, on the surface of the p-type silicon substrate 21 in the element region,
N+ type source and drain regions 26a and 26b are formed facing each other. On the channel region sandwiched between these n+ type source and drain regions 26a and 26b,
A polycrystalline silicon gate electrode 25 is formed with a gate oxide film 24 interposed therebetween. This polycrystalline silicon gate electrode 25 is covered with an insulating film 32. Also, n+
A source electrode 33a made of, for example, Al (aluminum) is formed on the type source region 26a and is in ohmic contact through a contact hole.
A drain electrode 33b made of Al is formed on the + type drain region 26b to make ohmic contact with it through a contact hole.

0003

[Problem to be solved by the invention] In this way, the conventional M
An OS type transistor has only one channel through which current flows, and there is a limit to improving its driving ability. By the way, TFTs (Th) are transistors that utilize field effects like MOS transistors and are applied to large-area flat panel display devices combined with liquid crystals.
n Film Transistor) type transistor. FIG. 7 shows a cross-sectional view of the most common inverted staggered TFT transistor.

A polycrystalline silicon gate electrode 42 is formed on an insulating substrate 41, and a gate oxide film 43 is formed on this polycrystalline silicon gate electrode 42. On this gate oxide film 43 and on the insulating substrate 41, there are TFTs.
A polycrystalline silicon layer 44 is formed to serve as a type transistor substrate. Moreover, on this polycrystalline silicon layer 44,
Source and drain electrodes 45a in ohmic contact
, 45b are formed opposite to each other.

Therefore, the gate voltage applied to the polycrystalline silicon gate electrode 42 causes the source and drain electrodes 45 to
A polycrystalline silicon layer 4 is used as a channel region between a and 45b.
4 can be controlled. That is, current-voltage characteristics similar to those of a MOS transistor can be obtained. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can achieve higher performance such as improved driving ability as a transistor by combining a MOS transistor with a TFT transistor.

[0006]

[Means for Solving the Problems] The above object is to provide a semiconductor substrate, a first source region and a first drain region formed opposite to the surface of the semiconductor substrate, and a first source region and a first drain region formed opposite to the surface of the semiconductor substrate. a first gate electrode formed on a first channel region sandwiched between a first drain region and a first gate insulating film;
a polycrystalline semiconductor layer formed through a gate insulating film;
a second source region and a second drain region formed opposite to the polycrystalline semiconductor layer; and a second channel region sandwiched between the second source region and the second drain region. , a second gate insulating film formed through a third gate insulating film.
This is achieved by a semiconductor device characterized in that it has a gate electrode.

Further, in the above semiconductor device, the first source region and the second source region are connected,
This is achieved by a semiconductor device characterized in that the first drain region and the second drain region are connected. Further, in the above semiconductor device, the second
A semiconductor device characterized in that the channel length of the channel region is set shorter than the channel length of the first channel region, and the travel time of carriers flowing through the first and second channel regions is approximately equal. achieved by.

[0008] The present invention is also achieved by the semiconductor device described above, characterized in that the first gate electrode and the second gate electrode are connected. Furthermore, the above problem is solved by a first step of forming a first gate electrode on a semiconductor substrate via a first gate insulating film, and implanting impurity ions using the first gate electrode as a mask. a second step of forming a first source region, a first drain region, and a first channel region sandwiched between the first source region and the first drain region facing the semiconductor substrate surface; a third step of forming a polycrystalline semiconductor layer on the first gate electrode via a second gate insulating film; and forming a second polycrystalline semiconductor layer on the polycrystalline semiconductor layer via a third gate insulating film. a fourth step of forming a gate electrode, and implanting impurity ions using the second gate electrode as a mask, forming a second source region, a second drain region, and a second drain region facing the polycrystalline semiconductor layer; A fifth step of forming a second channel region sandwiched between the second source region and the second drain region is achieved by a method for manufacturing a semiconductor device.

[0009] In the above method for manufacturing a semiconductor device, the third step may include a step in which both ends of the polycrystalline semiconductor layer extend beyond the first gate electrode and above the first source region and into the first source region. This is a step of forming the polycrystalline semiconductor layer so as to reach above the drain region, and by selective etching, the polycrystalline semiconductor layer is formed on the first source region and the second source region, and on the first drain region and the first source region. 2
After forming contact holes on the respective drain regions, a source electrode connecting the first source region and the second source region through the contact hole, and a source electrode connecting the first drain region and the second drain region. This is achieved by a method for manufacturing a semiconductor device characterized by comprising a sixth step of forming a drain electrode thereon.

[0010] Furthermore, in the above method for manufacturing a semiconductor device, the fifth step may include forming the second gate electrode so that the second gate electrode has a channel length shorter than the channel length of the first channel region. A method for manufacturing a semiconductor device, the method comprising controlling the channel length of the second channel region so that carriers flowing through the first and second channel regions have approximately equal travel time. achieved.

[0011]

The present invention focuses on the fact that the element region of a TFT transistor is formed in a polycrystalline semiconductor layer, and provides a transistor with a three-dimensional structure in which a TFT transistor is stacked on top of a MOS transistor. That is, a first source region and a first drain region formed facing the surface of the semiconductor substrate, and a first channel region sandwiched between these regions with a first gate insulating film interposed therebetween. 1 constitutes a MOS type transistor, and above this MOS type transistor, a polycrystalline semiconductor layer, a second source region and a second drain formed opposite to the polycrystalline semiconductor layer are formed. area and the second area sandwiched between these areas.
A TFT type transistor having a second gate electrode formed on the channel region of the TFT type transistor through a third gate insulating film is provided, and the first gate electrode of the MOS type transistor is connected to the other gate of the TFT type transistor. It has a double gate structure that serves as an electrode.

[0012] As a result, a field effect transistor having a multi-channel structure is formed, and it is possible to improve the performance of the transistor, such as greatly improving the drain current driving ability.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained based on illustrated embodiments. FIG. 1 is a sectional view showing a field effect transistor according to an embodiment of the present invention. A field oxide film 2 is formed on a p-type silicon substrate 1, and a p-type silicon substrate 2 is formed under this field oxide film 2.
A + type channel stopper region 3 is formed. A p-type silicon substrate 1 in an element region separated by these field oxide films 2 and p+ type channel stopper regions 3.
On the surface, n+ type first source and drain regions 6a, 6
b are formed facing each other. A first polycrystalline silicon gate electrode with a thickness of 300 nm is placed on the first channel region sandwiched between these n+ type first source and drain regions 6a and 6b via a first gate oxide film 4 with a thickness of 20 nm. 5 is formed.

A p-type polycrystalline silicon layer 8 having a thickness of 50 nm and serving as a TFT type transistor substrate is formed on the first polycrystalline silicon gate electrode 5 via a second gate oxide film 7 having a thickness of 50 nm. has been done. Both ends of this p-type polycrystalline silicon layer 8 extend beyond the first polycrystalline silicon gate electrode 5 to form n+-type first source and drain regions 6a, 6.
b Extends until it reaches above.

At both ends of the p-type polycrystalline silicon layer 8, n+
Type second source and drain regions 11a and 11b are formed facing each other. And these n+ type second sources,
The length of the second channel region sandwiched between drain regions 11a and 11b is the length of the n+ type first source, drain region 6a,
The length is controlled to be a predetermined length shorter than the channel length of the first channel region between 6b. Furthermore, a second polycrystalline silicon gate electrode 10 with a thickness of 300 nm is formed on the second channel region with a third gate oxide film 9 having a thickness of 50 nm interposed therebetween. Furthermore, a second polycrystalline silicon gate electrode 10
is covered with an insulating film 12 having a thickness of 400 nm.

Furthermore, the n+ type first source region 6a and the n+ type first source region 6a and n
A source electrode 13a made of, for example, Al (aluminum) is formed on the + type second source 11a and is in ohmic contact with it via a contact hole, and similarly, the n+ type first drain region 6b and the n+ type second drain region 6b are connected to each other. A drain electrode 13b made of Al is formed on the region 11b to make ohmic contact through a contact hole.

Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be explained using FIGS. 2 to 5. See Figure 2 (a): LOCOS (Local Oxid
Element isolation is performed using the cation of silicon method. That is, after forming a silicon nitride film (not shown) on p-type silicon substrate 1, field ion implantation is performed using a resist (not shown) formed only in the element region by photo process as a mask. Subsequently, by etching using the same resist as a mask, a silicon nitride film is left only in the element region, and then selective oxidation is performed using this silicon nitride film as a mask to form field oxide film 2. The implanted field ions are activated by the heat treatment at this time, and a p+ type channel stopper region 3 is formed under the field oxide film 2. Then, the silicon nitride film is removed.

Refer to FIG. 2(b): Thermal oxidation is performed at a temperature of 1000° C. in an oxygen atmosphere for 10 minutes and in a nitrogen atmosphere for 10 minutes to remove the p-type silicon substrate 1 in the element region separated by the field oxide film 2. A first gate oxide film 4 having a thickness of 20 nm is formed thereon. Refer to Figure 2(c): After depositing a polycrystalline silicon layer with a thickness of 300 nm on the entire surface by CVD method, RIE (Reactive Ion Etchi
ng) to form a first polycrystalline silicon gate electrode 5.

Refer to FIG. 3(a): Using the first polycrystalline silicon gate electrode 5 as a mask, As+ (arsenic) ions are implanted to form n+ type first source and drain regions 6a and 6b. At the same time, As+ ions are implanted into the first polycrystalline silicon gate electrode 5 so that it becomes conductive.

Refer to FIG. 3(b): Humid oxidation is performed at a temperature of 900° C. for 30 minutes to form a second gate oxide film 7 with a thickness of 50 nm. See FIG. 3(c): After depositing a polycrystalline silicon layer with a thickness of 50 nm over the entire surface by CVD, RIE is performed using a resist patterned into a predetermined shape by photo process as a mask. At this time, both ends of this polycrystalline silicon layer extend beyond the first polycrystalline silicon gate electrode 5 to n+
It is made to reach above the first source and drain regions 6a and 6b. After implanting B+ (boron) ions at a predetermined dose, annealing is performed at a temperature of 850° C. for about 30 minutes to form a p-type polycrystalline silicon layer 8 that will become a TFT-type transistor substrate.

Refer to FIG. 4(a): After performing humidified oxidation at a temperature of 900° C. for 30 minutes, thermal oxidation was performed for 10 minutes in a nitrogen atmosphere to form a 50 nm thick layer on the p-type polycrystalline silicon layer 8.
A third gate oxide film 9 is formed. Refer to FIG. 4(b): After depositing a polycrystalline silicon layer with a thickness of 300 nm on the entire surface by CVD method, RIE is performed using a resist patterned into a predetermined shape by photo process as a mask to form a second polycrystalline silicon gate electrode. form 10. At this time, the length of the second polycrystalline silicon gate electrode 10 is controlled to be shorter than the channel length of the first channel region between the n+ type first source and drain regions 6a and 6b. This means that the length of the second channel region formed in the p-type polycrystalline silicon layer 8 in a later step is longer than the channel length of the first channel region between the n+ type first source and drain regions 6a and 6b. This is to make it a short predetermined length.

Refer to FIG. 4(c): Using the second polycrystalline silicon gate electrode 10 as a mask, the p-type polycrystalline silicon layer 8 is
After implanting As+ ions into the
Annealing is performed for about 10 minutes to form n+ type second source and drain regions 11a and 11b. At the same time, As+ ions are implanted into the second polycrystalline silicon gate electrode 10 so that it becomes conductive.

Refer to FIG. 5(a): 400 nm thick on the entire surface.
An insulating film 12 is deposited by CVD. Refer to FIG. 5(b): By selective etching using a resist patterned into a predetermined shape by a photo process as a mask, the n+ type first source and drain regions 6a,
Insulating film 12 and first gate oxide film 4 on 6b, and n
The insulating film 12 and the third gate oxide film 9 on the + type second source and drain regions 11a and 11b are removed by etching,
Open a contact hole.

Refer to FIG. 5(c): After depositing, for example, an Al metal film with a thickness of about 1 μm on the entire surface by the PVD method, it is patterned into a predetermined shape to form the n+ type first source region 6.
A source electrode 13a is formed in ohmic contact with the a and n+ type second source 11a, and a drain electrode 13b is formed in ohmic contact with the n+ type first drain region 6b and the n+ type second drain region 11b.

As described above, according to this embodiment, the first gate oxide is formed on the n+ type first source and drain regions 6a and 6b on the surface of the p-type silicon substrate 1 in the element region and the first channel region sandwiched therebetween. The first polycrystalline silicon gate electrode 5 formed through the film 4 constitutes a MOS transistor. Above this MOS transistor, an n+ type second transistor is formed in the p type polycrystalline silicon layer 8.
A TFT type transistor is configured having source and drain regions 11a and 11b and a second channel region sandwiched therebetween. Moreover, this TFT type transistor
Above and below it, a third gate oxide film 9 and a second gate oxide film 7
respectively, a second polycrystalline silicon gate electrode 10
and a first polycrystalline silicon gate electrode 5 are formed, forming a so-called double gate structure.

Therefore, the second polycrystalline silicon gate electrode 1
By applying the same gate voltage to the 0 and first polycrystalline silicon gate electrodes 5, three channels through which drain current flows are formed between the source electrode 13a and the drain electrode 13b, and the transistor can significantly improve the driving capacity of the Furthermore, by separately controlling the gate voltages applied to the second polycrystalline silicon gate electrode 10 and the first polycrystalline silicon gate electrode 5, the number of drain current channels can be freely changed from 1 to 3. It can be used to improve the performance of transistors.

In this embodiment, the first channel region formed on the surface of the p-type silicon substrate 1 and the second channel region formed on the p-type polycrystalline silicon layer 8 are separated by bulk movement depending on the crystal structure. Since the speed is different, the carrier velocity also differs. Therefore, by controlling the impurity concentration of the second channel region and its channel length,
Specifically, the dose of B+ ions implanted into the p-type polycrystalline silicon layer 8 is controlled (see FIG. 3(c)).
Furthermore, by controlling the length of the second polycrystalline silicon gate electrode 10 (see FIG. 4(b)), the travel time of carriers flowing through the first and second channel regions is made to be approximately equal. .

[0028]

As described above, according to the present invention, there is provided a semiconductor substrate, a first source region and a first drain region formed opposite to the surface of the semiconductor substrate, and a first drain region sandwiched therebetween.
A MOS type transistor is formed by a first gate electrode formed on the channel region of the MOS transistor via a first gate insulating film, and above this MOS type transistor,
a polycrystalline semiconductor layer formed on the first gate electrode via a second gate insulating film, a second source region and a second drain region formed opposite to the polycrystalline semiconductor layer;
By configuring a TFT type transistor with a double gate structure having a second gate electrode formed on the second channel region sandwiched between these with a third gate insulating film interposed therebetween, the electric field of the multi-channel structure can be reduced. An effect transistor can be formed.

[0029] This not only greatly improves the drain current driving ability but also contributes to higher performance of the transistor.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a field effect transistor according to an embodiment of the present invention.

FIG. 2 is a process diagram (Part 1) for explaining the method for manufacturing the field effect transistor shown in FIG. 1;

3 is a process diagram (part 2) for explaining the method for manufacturing the field effect transistor shown in FIG. 1; FIG.

4 is a process diagram (Part 3) for explaining the method for manufacturing the field effect transistor shown in FIG. 1; FIG.

5 is a process diagram (part 4) for explaining the method for manufacturing the field effect transistor shown in FIG. 1; FIG.

FIG. 6 is a cross-sectional view showing a conventional MOS transistor.

FIG. 7 is a cross-sectional view showing a conventional TFT transistor.

[Explanation of symbols]

1...p-type silicon substrate 2...Field oxide film 3...p+ type channel stopper region 4...First gate oxide film 5...First polycrystalline silicon gate electrode 6a...n+ type first source region 6b...n+ type first drain region 7...Second gate oxide film 8...p-type polycrystalline silicon layer 9...Third gate oxide film 10...Second polycrystalline silicon gate electrode 11a...n+ type second source region 11b...n+ type second drain region 12...Insulating film 13a...source electrode 13b...Drain electrode 21...p-type silicon substrate 22...Field oxide film 23...p+ type channel stopper region 24...Gate oxide film 25...Polycrystalline silicon gate electrode 26a...n+ type source region 26b...n+ type drain region 32...Insulating film 33a...source electrode 33b...Drain electrode 41...Insulating substrate 42...Polycrystalline silicon gate electrode 43...Gate oxide film 44...Polycrystalline silicon layer 45a...source electrode 45b...Drain electrode

Claims (7)

[Claims] 1. A semiconductor substrate, a first source region and a first drain region formed opposite to the surface of the semiconductor substrate, and a semiconductor substrate sandwiched between the first source region and the first drain region. A first gate electrode is formed on the first channel region with a first gate insulating film interposed therebetween, and a polygonal electrode is formed on the first gate electrode with a second gate insulating film interposed therebetween. a crystalline semiconductor layer, a second source region and a second drain region formed opposite to the polycrystalline semiconductor layer, and a second region sandwiched between the second source region and the second drain region. A semiconductor device comprising: a second gate electrode formed on a channel region of the semiconductor device with a third gate insulating film interposed therebetween. 2. The semiconductor device according to claim 1,
A semiconductor device, wherein the first source region and the second source region are connected, and the first drain region and the second drain region are connected. 3. The semiconductor device according to claim 1, wherein the channel length of the second channel region is equal to that of the first channel region.
A semiconductor device characterized in that the channel length of the channel region is set to be shorter than that of the channel region, and the travel time of carriers flowing through the first and second channel regions is approximately equal. 4. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are connected. 5. A first step of forming a first gate electrode on a semiconductor substrate via a first gate insulating film, and implanting impurity ions using the first gate electrode as a mask. a second step of forming a first source region, a first drain region, and a first channel region sandwiched between the first source region and the first drain region facing the substrate surface; , a third step of forming a polycrystalline semiconductor layer on the first gate electrode via a second gate insulating film; and forming a second polycrystalline semiconductor layer on the polycrystalline semiconductor layer via a third gate insulating film. A fourth step of forming a gate electrode, and implanting impurity ions using the second gate electrode as a mask, forming a second source region, a second drain region, and the second drain region facing the polycrystalline semiconductor layer. A method of manufacturing a semiconductor device, comprising a fifth step of forming a second channel region sandwiched between a second source region and the second drain region. 6. The method of manufacturing a semiconductor device according to claim 5, wherein in the third step, both ends of the polycrystalline semiconductor layer extend above the first source region and above the first gate electrode. This step is a step of forming the polycrystalline semiconductor layer so as to reach above the first drain region, and selectively etching the polycrystalline semiconductor layer to form the first source region and the second source region.
After forming contact holes on the source region, the first drain region, and the second drain region, respectively, the first source region and the second source region are connected through the contact holes. A method for manufacturing a semiconductor device, comprising a sixth step of forming a drain electrode on a source electrode, the first drain region, and the second drain region. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the fifth step includes forming the first channel region such that the second gate electrode is shorter than the channel length of the first channel region. a step of forming a second gate electrode, and the channel length of the second channel region is controlled so that the travel time of carriers flowing through the first and second channel regions is approximately equal. Method of manufacturing the device.