JPH04287376A - Insulated-gate transistor and semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the junction capacitance of an insulating gate transistor so as to make the transistor higher in processing speed by eliminating the cause of carrier scattering and bringing the mobility of the carriers closer to that peculiar to a semiconductor material. CONSTITUTION:An area 5 is an insulating film which is used as the insulating film for the gate of an MOS transistor and SiO2, Si3N4, TiO2, TaO2, etc., and their composite film are used from forming the insulating film 5. A region 6 is a gate electrode made of p<+> or n<-> polysilicon. While the n<-> polysilicon is preferable for short channels, but n<+> polysilicon can also be used. It is important to allow carrier electrons 20 to run in the region 6 apart from the boundary between the film 5 and a semiconductor. Therefore, the scattering of carriers caused by the unevenness of the boundary can be reduced. In addition, the cause of the scattering of the carriers can be eliminated by controlling the width and impurity concentration of the carrier running region.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate transistor and a semiconductor integrated circuit equipped with the same.

0002

[Background Art] An enhancement type MOS transistor (Tr) is one of conventional MOS transistors.
It has been known.

0003

[Problem to be solved by the invention] Conventional MOS Tr
Then, the width of the inversion channel where carriers are induced is ~10
It is a narrow region of about 0 Å, and the electrolytic EV perpendicular to the surface of that part is steep, and the carrier mobility easily decreases to 106
It will be about V/cm. Therefore, the influence of EV is directly reflected on carrier mobility, which is slower than the mobility inherent in semiconductors. FIG. 11 shows the vertical electric field EV and carrier mobility. At low electric fields, Crohn scattering determined by impurities in the substrate dominates, and at medium electric fields, phonon scattering,
At high electric fields, the mobility is determined by scattering due to surface roughness. For example, the electron mobility μ in the Si semiconductor itself is originally around 300°K and μ≒1500cm.
2/V・sec, but in MOS Tr, it is at most 300 to 700 cm in the medium and high electric field region of operation.
It only goes up to about 2/V・sec.

Therefore, an object of the present invention is to improve the carrier mobility, which is an important parameter determining the characteristics of a MOS transistor.

Another object of the present invention is to provide a MOS type transistor exhibiting improved carrier mobility.

[0006]

[Means for Solving the Problems] The above-mentioned cause of carrier scattering can be removed, carrier mobility can be approximated to that inherent in semiconductor materials, and the present invention provides the following 1.
~3 is achieved.

1. In order to eliminate Coulomb scattering, the impurity concentration of the substrate in the carrier movement region is lowered to increase the mobility in the low electric field region.

2. Lower the electric field strength in the carrier conduction region,
In addition, by expanding the range of carrier containment area,
Increase mobility in medium electric field region.

3. Mobility in the high electric field region is improved by not allowing carriers to exist near the interface between the oxide film and the semiconductor, and by reducing scattering due to the surface roughness of the interface.

0010

[Example] Figure 1 shows a MOS that best represents the features of the present invention.
2 shows a cross-sectional view of a type transistor.

[0011] Region 1 is a P-type substrate, and contains 1014 to 1014.
Good up to 1018 cm-3.

Region 2 is an n-region and has a size of 1×10 17
It is necessary to make the concentration lower than cm-3 and reduce the mobility by Coulomb scattering. Region 3 has a higher impurity concentration than region 2 to prevent inverted carriers from being trapped near the surface. Concentration is 1015-101
It is in the range of 9 cm-3.

Region 4 is an n+ region in the vicinity of 1018 to 1021 cm-3, which becomes the source or drain of the MOS transistor.

Region 5 is an insulating film, which is an insulating film for the gate of the MOS Tr. SiO2, Si3N4, TiO2,
TaO2 and other films and composite films thereof can be used.

Region 6 is a gate electrode and is P+ or n+
polysilicon, n+ is desirable for short channels, but n+
Poly-Si may also be used. Alternatively, silicide, polycide, high melting point metal, or a composite film thereof can be used.

The region 200 uses a material such as AL, Al--Si, Cu, poly-Si, or silicide, which becomes the ohmic electrode wiring for the source and drain.

FIG. 2 shows a potential diagram of the section AA' in FIG.

In the figure, 20 schematically represents an electron, which is a carrier. What is important in the present invention is the carrier electron 20
It is important that the insulator travels away from the insulating film and semiconductor interface. This makes it possible to reduce carrier scattering due to the unevenness of the interface.

Furthermore, the cause of carrier scattering can be removed by controlling the width of the carrier travel region and the impurity concentration.

The drain current of a MOS transistor is approximately expressed by the following equation. In the linear region IDL=μeff・W/L・εOX/TOX・VD
(VG-Vth) (1) In the saturation region IDS=1/2μeff・W/L・εOX/TOX
(VG-Vth)2 (2) However, ID2, ID5:
Linear, saturated, region drain current μeff: effective mobility, W: gate width, L: gate length εOX: dielectric constant of oxide film, TOX: thickness of oxide film VD: drain voltage, VG: gate voltage, Vth: threshold voltage

In MOS transistors that are highly integrated, the most important thing is generally to reduce the gate width L. Accordingly, the TOX film is made thinner, and
The impurity density in the channel portion is also controlled to prevent source/drain punch-through. Carrier mobility is reduced because the impurity density is increased.

[0022] We improve the carrier mobility μeff in order to increase the driving force of the above device.

Furthermore, by improving μeff, the transit time of carriers is shortened, which greatly contributes to speeding up the device.

The present invention will be explained by describing carrier scattering, which is generally mentioned in a MOS transistor.

The most well-known carrier scattering is
The first is scattering due to lattice vibrations, that is, phonons, and the second is scattering due to impurity ions in the substrate. In scattering by phonons, when the drift electric field is low, it is proportional to the temperature T to the -3/2 power as μLα (m*) -5/2T-3/2 (3), and the effective mass (m*) is -5
/proportional to the square. Mobility μi due to impurity ion scattering
is proportional to T3/2, as μiα(m*)-1/2N-1IT3/2 (4), and the ionized impurity concentration NI
is inversely proportional to.

The mobility μ when both are mixed is μ=(1
/μl+1/μi)−1 (5) At low temperatures, μi is dominant, and at high temperatures, μl is dominant. FIG. 4 shows carrier mobility versus impurity density.

[0027] Unless it is desirably 1016α or less, a mobility close to that inherent in semiconductors cannot be achieved. 1017c
It is clear that the mobility decreases significantly above m-3. Regarding the mobility inside the semiconductor substrate, since the MOS transistor is a surface device, other unique phenomena appear.

The potential diagram in the direction perpendicular to the surface near the surface of a normal MOS is as shown in FIG. /2mvx2. That is, the electrons are accelerated in the direction of the valley of x. Therefore, high-energy electrons accelerated by the electric field in the x direction collide with the surface, lose kinetic energy, return to a thermal equilibrium state, and are scattered in random directions. Therefore, the mobility of carriers flowing in the y direction decreases. This is called the distributed scattering model, and according to the model, μSS/μB=1−e×p(α2)[1−erf(
α)] (6) However, μB: bulk mobility, μSS:
Dispersion scattering mobility

[0029]

[Outside 1] k: Boltzmann constant attack, T: absolute temperature, EX: vertical electric field,
τ: Relaxation time. As the vertical electric field Ex increases, scattering increases and μeff decreases.

Scattering due to surface undulations is also an important scattering mechanism unique to the surface. Si-SiO
2 The interface cannot be said to be completely flat, with a height of several nm and a period of ~1
There are slight undulations of 0 nm. Since the degree of this undulation is a value that cannot be ignored compared to the wavelength of the electron wave (~10 nm) on the surface, electrons are scattered by this undulation.

Qualitatively, the electric field dependence is as shown in FIG. The present invention attempts to solve all these problems. The impurity distribution of the gate electrode F is created as shown in the cross-sectional view of FIG. 1, the potential distribution is made as shown in FIG. 2, and the carriers are caused to travel at a position away from the interface. The essential point is to create a region where the impurity concentration is low in the carrier travel region. The impurity concentration is 1017cm-
It is preferably 3 or less, more preferably 1016 cm-3 or less. By keeping the concentration below this level, impurity scattering is reduced. The depth of the n- region must be at least shallower than that of the source and drain regions, and punch-through of the source and drain must be suppressed.

The n-region is an enhancement type transistor that is depleted when the gate voltage is off, making it a normally off type MOS transistor. Unlike conventional embedded MOS Tr, if the n-region gate voltage application and the Fermi potential of the electrode and semiconductor are not taken into account,
It is only necessary to consider the expansion of the depletion layer due to the semiconductor Pn junction. The thickness of the depletion layer extending to the n-type region of the Pn junction is

[0033]

It is expressed as [Example 2]. Vbi: diffusion potential, NA, ND: P, n
Type impurity concentration, εS: permittivity, q: charge

Since it is an n-type, if the P-type impurity concentrations of regions 1 and 3 are P1 and P2, the thickness of the n-type region is
At least xn(ND)<xnl(ND, NAl)+xn2(
ND, NA2) (9).

[0035] The P+ high concentration region (3) on the surface is 50 to 10
The thickness should be 0 Å or more. It is better to minimize the probability of scattering at the interface between SiO2 and Si by making the mean free path at least greater than the mean free path of the traveling carriers. Regarding the impurity concentration, it is better to set it to one digit or more of that in region 2. The interface between the oxide film and the semiconductor may be depleted or neutral.

If region 3 is also depleted, the gate capacitance will be lower and high speed operation will be possible, which is superior. When voltage is applied to the gate electrode, induced carriers must not be generated in region 3. Must be generated in area 2. In other words, in order to generate free carriers, the Fermi level φF, which is originally determined by the impurity concentration in the region, is required to generate free carriers.
When the value is set to -2φF or more, a strong inversion occurs, and carriers that operate the MOS transistor are generated. In the case of an n-type region, free carriers begin to be generated if the region is above the middle of the forbidden band.

FIG. 5 shows the horizontal axis temperature (°K) for Si;
The vertical axis shows changes in the Fermi level. In the figure, n-type,
The impurity density for P type is used as a parameter. In the n-type semiconductor region of region 2, if the Fermi level expressed by EF-Ei is above the middle, free carriers are
Supplied from the source of the transistor. EF-Ei is 0
．． At about 3 lV, free carriers of about 1015 cm-3 are supplied. In order to generate free carriers in the P+ region of region 3, for example, if P+ = 1018 cm-3, it is explained from FIG. can.

FIG. 6 shows an ideal impurity density distribution in the cross section in the direction A→A' of FIG. The surface consists of three regions: a P+ region with a high concentration, a carrier traveling region with a low concentration, and a substrate region with an intermediate concentration. (In Figure 6, the solid line is the ideal stepwise distribution,
The dashed line is the actual impurity distribution).

The threshold voltage can be approximately expressed as follows.

First, take the integral value DI of impurities in two regions on the surface.

[0041]

[Outer 3]

The amount of change in the threshold voltage can be approximately determined by equation (11). However, this is the case where the depletion layer thickness x0l is deeper than x2 and the P+ surface layer is depleted. The final threshold can be expressed as Vth=Vth(N3)+ΔVth (12). Vth(
N3) by ΔVth.

It is easy to set ΔVth=0, and DI=
This can be done by setting N1, N2, x1, and x2 to be 0. In that case, Vth can be determined depending on the concentration of the substrate. Also, depending on the material used for the electrode,
Although the Fermi level difference φms with respect to the semiconductor is different, the threshold value can be easily controlled according to the difference by controlling the concentration thickness of P+ on the surface using equation (11).

Manufacturing process in FIG. 1 (1) After a P-type substrate 1 (1014 to 1018 cm-3) or a P-type region is created by a diffusion method or the like, an impurity concentration of 1017 is formed to a thickness of about 1 μm or less by an epitaxial method.
Create n region 2 below cm-3. (2) Create element isolation region 50 using selective oxidation method etc. (
3) Create a gate oxide film or insulating layer 5 by an oxidation method or the like. (4) BF+2 is applied to the surface at 5KlV by ion implantation method.
~1E11~1E13 at an accelerating voltage of about 100KlV
Ion implantation is performed at a dose of about cm-2. Heat treatment is 8
This is carried out by heat treatment at 00 to 900°C or rapid heating (RTA) method at about 950 to 1050°C. (5) Gate electrode 6 is created by patterning after depositing P+ polysilicon. (6) Created after ion implantation of impurities such as phosphorus (P+) or arsenic (A+S) by self-alignment using the gate electrode 6 as a mask, followed by RTA heat treatment. (7) After estimating the insulating film 200 for interlayer separation and wiring separation,
After annealing, drill the contact holes. (8) Metal electrodes are sputtered or chemically deposited (CVD)
) method, and then patterned and created.

The device of FIG. 1 is fabricated by the process described above.

However, in processes such as CMOS and B:CMOS, improvements are becoming more complex.

What is most important in the present invention is the impurity concentration and thickness of regions 2 and 3, and in order to maintain the impurity distribution, low-temperature epitaxial method (800-950°C), low-temperature heat treatment (800-950°C), RTA Application of the law is necessary.

FIG. 7 shows the mobility of the MOSFET of the present invention. (Characteristic curve 71 in the figure).

This is improved compared to a conventional normal n-type MOSFET (the characteristic of the conventional MOS is a characteristic curve 72).

(Other Embodiments) FIG. 8 shows a second embodiment.

When the concentration of the n- region is extremely low, for example lower than 1015 cm-3, the depletion layer X tends to expand, so the n- region may be deeper than the source and drain.

In such a device, it becomes necessary to insert a channel stop region 10 under the element isolation region. The capacitance of the depletion layer X under the source/drain is also significantly reduced, making it possible to increase the speed. A similar effect occurs as in SOI.

In FIG. 9, an n region is further formed above the region 2, and the electric field in the P+n region is made steeper. However, n-n
-The entire region is completely depleted. It doesn't matter if 2 and 2' are opposite.

FIG. 10 shows an embodiment of a recessed MOS transistor. This is advantageous in shortening the channel. Similarly, the channel region is at least depleted in n-.

Although the present invention has been described with respect to an n-type MOS transistor, it is of course applicable to a p-type MOS transistor. In that case, in embodiments of the present invention, the n and p types are all opposites.

[0056]Although only the Si material has been described, other G
It is clear that other materials such as aAS and GaP can also be used.

[0057]

[Effects of the invention] - Mobility increases by reducing interface scattering, electric field relaxation, and ion scattering. -gm becomes large.

- Since the electric field on the drain side is also relaxed, the withstand voltage between the source and drain also increases. Therefore, when a short channel device is used, fewer hot carriers are generated. The electric field distribution between the gate and drain can be made gentle. Unlike the LDD structure, the series resistance does not increase. The LDD has an n-region series resistance in the source on the source side. In the present invention, n- is a depleted channel and does not act as a series resistance.

[0059] In a type of MOS transistor in which the region below the drain is also depleted, the junction capacitance is reduced and the device becomes compatible with ultra-high speed. In addition, this type also further increases drain breakdown voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a MOS transistor of the present invention.

FIG. 2 is a potential diagram of the section AA' in FIG. 1;

FIG. 3 is an explanatory diagram of kinetic energy.

FIG. 4 is a diagram of carrier mobility versus impurity density.

FIG. 5 is a diagram showing changes in Fermi level with respect to temperature (°/C) in Si.

6 is an impurity density distribution diagram of a cross section taken along line A-A' in FIG. 1. FIG.

FIG. 7 is a diagram showing carrier mobility of the MOSFET of the present invention.

FIG. 8 is a sectional view of a second embodiment of the invention.

FIG. 9 is a sectional view of a third embodiment of the invention.

FIG. 10 is a sectional view of a fourth embodiment of the present invention.

FIG. 11 is a diagram showing carrier mobility versus effective electric field.

Claims (6)

[Claims] 1. A source and drain region of at least a first conductivity type and high impurity density, a channel region between the source and drain, an insulating layer at least covering the channel region, and a conductive layer adjacent to the insulating layer. In an insulated gate transistor having a gate electrode made of a material, the channel region includes a first channel region of a low resistance second conductivity type opposite the first conductivity type and close to the insulating layer, and the first channel region An insulated gate transistor comprising: a high-resistance second channel region of a first conductivity type adjacent to the second channel region; and a third channel region of the second conductivity type adjacent to the second channel region. 2. A source and drain region of at least a first conductivity type and high impurity density, a channel region between the source and drain, an insulating layer at least covering the channel region, and a conductive layer adjacent to the insulating layer. In a semiconductor integrated circuit including an insulated gate transistor having a gate electrode made of a material, the channel region is a first channel region of a low resistance second conductivity type opposite to the first conductivity type and adjacent to the insulating layer. , a semiconductor comprising an insulated gate transistor having a high resistance second channel region of a first conductivity type adjacent to the first channel region, and a third channel region of a second conductivity type adjacent to the second channel region. integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit includes an MIS transistor in which the second channel region is depleted at least when the gate applied voltage is zero. 4. An MIS having a fourth channel region of the first conductivity type between the first channel region and the second channel region.
4. The semiconductor integrated circuit according to claim 2, which is an integrated circuit including a transistor. 5. MIS in which the potential distribution of the channel portion is high at the surface during operation with gate voltage applied, and carriers are flowed at a depth deeper than the interface and at least the mean free path of the carriers.
3. The semiconductor integrated circuit according to claim 2, which is an integrated circuit including a transistor. 6. The semiconductor integrated circuit according to claim 5, wherein said MIS transistor is a current enhancement type MIS transistor.