JP3119370B2 - Insulated gate transistor and semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulated gate transistor and a semiconductor integrated circuit having the same.

[0002]

2. Description of the Related Art As one of conventional MOS transistors, an enhancement MOS transistor (Tr) is used.
It has been known.

[0003]

In the conventional MOS Tr, the width of the inversion channel in which carriers are induced is up to 100.
A narrow region of about Å, electrolyte E _V perpendicular to the surface of the part is steep, easy mobility of the carrier is 10 ⁶ V /
cm. For this reason, the influence of the E _V is not directly reflected in the mobility of the carrier, which is slower than the semiconductor-specific mobility. Shows the mobility of the vertical field E _V and carrier 11. On the low electric field side, clone scattering mainly determined by impurities in the substrate is predominant, and the mobility is determined by phonon scattering in a medium electric field and scattering by surface roughness in a high electric field. For example, the electron mobility μ in the Si semiconductor itself
Is originally about 300 ° K and μ ≒ 1500 cm ² /
Although it is about V · sec, in the MOS Tr, it is at most 300 to 700 cm ² / V in the middle and high electric field region which is the operation region.
・ It only goes up to about sec.

Accordingly, an object of the present invention is to improve carrier mobility, which is an important parameter that determines the characteristics of a MOS transistor.

It is another object of the present invention to provide a MOS type transistor exhibiting improved carrier mobility.

[0006]

SUMMARY OF THE INVENTION An insulated gate transistor and a semiconductor integrated circuit having the insulated gate transistor according to the present invention have the following configurations. That is, the insulated gate transistor of the present invention includes a source region and a drain region of the first conductivity type, a channel region formed between the source region and the drain region, an insulating layer covering the channel region, and an insulating layer. An insulated gate transistor having a gate electrode provided in close proximity to the insulating layer, wherein the channel region is adjacent to the insulating layer and has a second channel type having a second conductivity type different from the first conductivity type and a low resistance. A second channel region adjacent to the first channel region and having a first conductivity type and a high resistance; and a third channel region adjacent to the second channel region and having a second conductivity type. A second channel region extends below the source and drain regions;
Over the regions, the impurity concentration of the second channel region is 10 ¹⁵ cm ⁻³ or less, and the depth of the first channel region is shallower than the depths of the source region and the drain region. It is a feature. A semiconductor integrated circuit according to the present invention includes a source region and a drain region of a first conductivity type, a channel region formed between the source region and the drain region, an insulating layer covering the channel region, and A channel region, wherein the channel region is adjacent to the insulating layer and has a second conductivity type and a low resistance which is different from the first conductivity type. One channel region;
A second channel region adjacent to the first channel region and having a first conductivity type and high resistance; and a third channel region adjacent to the second channel region and having a second conductivity type. A two-channel region is provided below and beyond the source region and the drain region, the impurity concentration of the second channel region is 10 ¹⁵ cm ⁻³ or less, and the depth of the first channel region is Is shallower than the depth of the source region and the drain region. According to the present invention, the cause of the carrier scattering can be eliminated, and the mobility of carriers inherent in the semiconductor material can be approximated. According to the present invention, the following 1 to 3 are achieved.

[0007] 1. In order to eliminate Coulomb scattering, the mobility in the low electric field region is increased by lowering the impurity concentration of the substrate in the carrier movement region.

[0008] 2. Lower the electric field strength in the carrier conduction region,
In addition, by expanding the width of the carrier and confinement area,
Increase the mobility in the middle electric field region.

3. The mobility in the high electric field region is improved by reducing the scattering of the surface roughness of the interface without the presence of carriers near the interface between the oxide film and the semiconductor.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
FIG. 2 shows a cross-sectional view of a type transistor.

The region 1 is a P-type substrate, and 10 ¹⁴ -1
Good to 0 ¹⁸ cm ^-3 .

The region 2 is an n ^- region, which is 1 × 10 ¹⁷ c
It is necessary to make the concentration lower than m ^{−3 and} to lower the mobility by Coulomb scattering. The region 3 has an impurity concentration higher than that of the region 2 so that inversion carriers are not trapped near the surface. The concentration is 10 ¹⁵ -10 ¹⁹ cm ^-3
Range.

The region 4 is an n ⁺ region in the vicinity of 10 ¹⁸ to 10 ²¹ cm ^-3 which becomes the source or drain of the MOS transistor.

A region 5 is an insulating film, and is a gate of the MOS Tr.
It is an insulating film for use. SiO_Two, Si_ThreeN _Four, TiO_Two, TaO
_TwoOthers and composite films thereof can be used.

The region 6 is a gate electrode, and is preferably P ⁺ or n ⁺ polysilicon, and n ⁺ is preferably a short channel, but may be n ⁺ poly Si. Alternatively, silicide, polycide, a refractory metal or a composite film thereof can be used.

The region 200 is made of an insulating film for separating wirings, interlayers, etc., and the region 100 is made of a material such as AL, Al-Si, Cu, poly-Si, silicide, etc., which becomes ohmic electrode wirings for the source and drain.

FIG. 2 shows a potential diagram of the section AA 'in FIG.

In the figure, reference numeral 20 denotes an electron which is a carrier. It is important in the present invention that the carrier electrons 20
Is important to travel away from the interface between the insulating film and the semiconductor. As a result, carrier scattering due to unevenness at the interface can be reduced.

Further, by controlling the width of the traveling region of the carrier and the impurity concentration, the cause of carrier scattering can be eliminated.

The drain current of a MOS transistor is approximately expressed by the following equation. Linear region _{I DL = μ eff · W /} L · ε OX / T OX · V D (V G -V th) (1) saturation region in _{I DS = 1 / 2μ eff ·} W / L · ε OX / T ^{_{OX (V G -V th) 2}} (2) where, I _D2, I _D5: linear, saturated, the drain current of the region mu _eff: effective mobility, W: gate width, L: gate length epsilon _OX: oxide film dielectric constant, T _OX: thickness of oxide film V _D: drain voltage, V _G: gate voltage, V _th: threshold voltage

In MOS transistors that are to be highly integrated, reducing the gate width L is generally regarded as the most important. Accordingly, in order to reduce the _thickness of T _OX and prevent punch-through of the source / drain, the impurity density of the channel portion is also increased. The carrier mobility is reduced because the impurity density is increased.

We improve the carrier mobility μ _eff in order to increase the driving force of the device described above.

Further, by improving μ _eff , the traveling time of carriers is shortened, which greatly contributes to speeding up of the device.

The present invention will now be described with reference to carrier scattering generally described in MOS transistors.

The best known carrier scattering is
First, there is scattering due to lattice vibration, that is, phonons, and second, there is scattering due to impurity ions on the substrate. Proportional to the -3/2 power of the temperature T as in the scattering by phonons is when low drift field _{^{μ L α (m *) -5/2}} T -3/2 (3), the effective mass (m *)
Is proportional to −5/2 power. As the mobility mu _i due to the impurity ions scattering _{^{μ i α (m *) -1/2}} N -1 I T 3/2 (4), proportional to T ^3/2, contrary to the impurity concentration N _I ionized Proportional.

The mobility mu of when both are mixed represented by _{μ = (1 / μ l +} 1 / μ i) -1 (5). At low temperatures, μ _i dominates and at high temperatures μ _l dominates. FIG. 4 shows the carrier mobility with respect to the impurity density.

If it is not less than 10 ¹⁶ α, mobility close to intrinsic to the semiconductor cannot be obtained. 10 ¹⁷ cm ^-3
In the above, it is clear that the mobility is significantly reduced. This is an explanation of the mobility inside the semiconductor substrate. However, since the MOS transistor is a surface device, another unique phenomenon appears.

A potential diagram in the direction perpendicular to the surface near the surface of the normal MOS is as shown in FIG. 3 (the left diagram is an enlarged view of a portion F in the right diagram), and the carrier has potential energy φ (x) and transport energy 1 / represented by the sum of 2mvx ^2. That is, the electrons are accelerated in the direction of the valley of x. Therefore, electrons having high energy accelerated by the electric field in the x direction collide with the surface, lose kinetic energy, return to a thermal equilibrium state, and are scattered in random directions. As a result, the mobility of carriers flowing in the y direction decreases. This is called a dispersion scattering model, and according to the model, μ _SS / μ _B = 1−ep × (α ² ) [1-erf (α)] (6) where μ _B : bulk mobility, μ _SS : dispersion Scattering mobility

[0029]

[Outside 1] k: Boltzmann TeiOsamu, T: absolute temperature, E _X: vertical electric field,
τ: relaxation time. When the vertical electric field E _x is large, it becomes scattered large, mu _eff decreases.

Scattering due to unevenness of the surface is also an important mechanism as a scattering mechanism peculiar to the surface. Si-SiO
_{2 The} interface is not completely flat, several nanometers in height, period ~ 1
There is a slight undulation of 0 nm. Since the degree of the undulation is not negligible compared to the wavelength of the electron wave (〜１０10 nm) on the surface, the electrons are scattered by the undulation.

Qualitatively, there is an electric field dependence as shown in FIG. The present invention seeks to solve all these problems. As shown in the cross-sectional view of FIG. 1, an impurity distribution of the gate electrode F is created, the potential distribution is made as shown in FIG. 2, and carriers are caused to travel at a position away from the interface. The essential point is that it is formed in a region where the impurity concentration is low in the carrier traveling region. The impurity concentration is preferably 10 ¹⁷ cm ^-3 or less, and more preferably 10 ¹⁶ cm ^-3 or less.
By setting the concentration to be equal to or less than this concentration, impurity scattering is reduced. It is necessary that the depth of the n ⁻ region is at least shallower than that of the source and drain regions, and that the punch through of the source and drain is suppressed.

The n ^- region is an enhancement type transistor which is depleted at the time of an off-gate voltage and is a normally-off type MOS transistor. Unlike the conventional buried MOS Tr, when the application of the n-region gate voltage and the Fermi potential of the electrode and the semiconductor are not taken into account, only the expansion of the depletion layer due to the semiconductor Pn junction needs to be taken into account. The thickness of the depletion layer extending to the n-type region of the Pn junction is

[0033]

[Outside 2] Is represented by V _bi : diffusion potential, N _A , N _D : P, n-type impurity concentration, ε _S : dielectric constant, q: electric charge

Since the region 1 and the region 3 have the P-type impurity concentrations of P ₁ and P ₂ , the thickness of the n-type region is at least x _n (N _D ) <x _nl (N _D , N _Al ) + x _n2 (N _D , N _A2 ) (9)

The P ⁺ high concentration region (3) on the surface is 50 to 10
0 ° or more. It is better to reduce the probability of scattering at the interface between SiO ₂ and Si by at least the mean free path of the traveling carrier. It is preferable that the impurity concentration be one digit or more in the region 2. The interface between the oxide film and the semiconductor may be depleted or neutral.

When the region 3 is also depleted, the gate capacitance is reduced, and high-speed operation is possible, which is excellent. When a voltage is applied to the gate electrode, induced carriers must not be generated in the region 3. Must be created in region 2. That is, in order to generate free carriers, the Fermi level φ _F which is originally determined by the impurity concentration of the region.
Is set to −2φ _F or more, strong inversion occurs, and carriers for operating the MOS transistor are generated. In the case of the n-type region, if it is above the middle of the forbidden band, generation of free carriers starts.

FIG. 5 shows the temperature (° K) on the horizontal axis with respect to Si,
The vertical axis indicates a change in Fermi level. In the figure, n-type,
The impurity density for the P type is used as a parameter. If above the Fermi level than the intermediate in the n-type semiconductor region of the region 2 represented by E _F -E _i, free carriers supplied from the source of the MOS transistor. E _F -E _i is 0.3
_At about ₁ V, free carriers of about 10 ¹⁵ cm ^-3 are supplied. To generate the free carriers in the P ⁺ region of the region 3, for example, P ⁺ = 10 ¹⁸ When cm ^-3, generated free carriers region 3 when To 12Fai _F is not about +1.0 _l V The inability to do so can be explained from FIG.

FIG. 6 shows an ideal impurity density distribution in a section taken along the line A → A ′ in FIG. On the surface, there are three regions: a high concentration P ⁺ region, a low concentration carrier traveling region, and a medium concentration substrate region. (In FIG. 6, the solid line is the ideal stepwise distribution,
The broken line is the actual impurity distribution).

The threshold voltage can be approximately expressed as follows.

First, an integral value D _I of impurities in two regions on the surface is obtained.

[0041]

[Outside 3]

From equation (11), the change in threshold voltage can be approximately determined. However, this is the case where the depletion layer thickness x _0l is deeper than x ₂ and the P ⁺ surface layer is depleted. The final threshold can be expressed as V _th = V _th (N ₃ ) + ΔV _th (12) V determined by substrate concentration N _3
This is close to shifting _th (N ₃ ) by ΔV _th .

It is easy to set ΔV _th = 0, and D _I = 0
N ₁ , N ₂ , x ₁ , and x ₂ can be set as follows. In that case, V _th can be determined by the concentration of the substrate. In addition, the difference of the Fermi level with the semiconductor φ _ms differs depending on the material used for the electrode.
The threshold value control can also be easily performed by controlling the P ⁺ concentration thickness on the surface by using the equation (11).

Manufacturing Process of FIG. 1 (1) P-type substrate 1 (10 ¹⁴ to 10 ¹⁸ cm ⁻³ ) or P
After forming a mold region by a diffusion method or the like, an n region 2 is formed by an epitaxial method with a thickness of about 1 μm or less and an impurity concentration of 10 ¹⁷ cm ⁻³ or less. (2) The element isolation region 50 is formed by a selective oxidation method or the like. (3) The gate oxide film or the insulating layer 5 is formed by an oxidation method or the like. (4) The BF ⁺ ₂ 5K _l V~ the surface by ion implantation
At an accelerating voltage of about 100K _l V, 1E11~1E13c
Ion implantation is performed at a dose of about m ^-2 . Heat treatment is 800
It is performed by a heat treatment at about 900 ° C. or a rapid heating (RTA) method at about 950 to 1050 ° C. (5) The gate electrode 6 is formed by patterning after depositing P ⁺ polysilicon. (6) Self-aligned ion implantation of impurities such as phosphorus (P ⁺ ) or arsenic (A ⁺ _S ) using the gate electrode 6 as a mask, and RTA heat treatment. (7) After depositing the insulating film 200 for interlayer separation and wiring separation,
After annealing, make contact holes. (8) Sputter metal electrodes or chemical deposition (CV
D) Produced by patterning after deposition by the method.

The device shown in FIG. 1 is manufactured by the above process.

However, processes such as CMOS and B: CMOS are more complicated and improved.

The most important factors in the present invention are the impurity concentration and the thickness of the regions 2 and 3, and the low-temperature epitaxial method (800 to 950 ° C.), the low-temperature heat treatment (800 to 950 ° C.), the RTA It is necessary to apply the law.

FIG. 7 shows the mobility of the MOSFET of the present invention. (Characteristic curve 71 in the figure).

This is improved as compared with the conventional ordinary n-type MOSFET (the characteristic of the conventional MOS is a characteristic curve 72).

(Other Embodiment) FIG. 8 shows a second embodiment.

When the concentration of the n ⁻ region is extremely low, for example, when it is lower than 10 ¹⁵ cm ⁻³ , the depletion layer X tends to spread, so that the n ⁻ region may be deeper than the source and drain.

In such a device, it is necessary to insert the channel stop region 10 below the element isolation region. The capacity of the depletion layer X under the source / drain is also extremely reduced, and the speed can be increased. The same effect as in SOI occurs.

FIG. 9 shows that an n-region is further formed in the upper layer of the region 2 and the electric field in the P ⁺ n region is increased. However, n ^- n ^-
The entire area is completely depleted. It does not matter if 2 and 2 'are reversed.

FIG. 10 shows an embodiment of a recess type MOS transistor. This is advantageous in shortening the channel. Similarly, the channel region is at least depleted during n ⁻ .

Although the present invention has been described with reference to an n-type MOS transistor, it is naturally applicable to a p-type MOS transistor. In that case, in the embodiment of the present invention, n and P types are all opposite.

Although only the Si material has been described,
aA _S, GaP, etc., it is apparent also applicable to other materials.

[0057]

According to the present invention, the mobility increases due to the reduction of interface scattering, electric field relaxation and ion scattering. -G _m is large.

Since the electric field on the drain side is also reduced, the breakdown voltage between the source and the drain also increases. Therefore, when a short channel device is used, generation of hot carriers is reduced. The electric field distribution between the gate and the drain can be made gentle. The series resistance does not increase unlike the LDD structure. The LDD has an n-region series resistance in the source on the source side. In the present invention, n ⁻ is a depleted channel and does not act as a series resistor.

In a MOS transistor in which the area under the drain is depleted, the junction capacitance is reduced, and the device can respond to ultra-high speed operation. In this type, the drain withstand voltage is further increased.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a MOS transistor according to the present invention.

FIG. 2 is a potential diagram of an AA 'part of FIG.

FIG. 3 is an explanatory diagram of kinetic energy.

FIG. 4 is a graph of carrier mobility with respect to impurity density.

FIG. 5 is a diagram showing a change in Fermi level with respect to temperature (° / C) in Si.

FIG. 6 is an impurity density distribution diagram of a cross section taken along line AA ′ of FIG. 1;

FIG. 7 is a graph showing carrier mobility of a MOSFET according to the present invention.

FIG. 8 is a sectional view of a second embodiment of the present invention.

FIG. 9 is a sectional view of a third embodiment of the present invention.

FIG. 10 is a sectional view of a fourth embodiment of the present invention.

FIG. 11 is a diagram showing carrier mobility with respect to an effective electric field.

Claims (6)

(57) [Claims] 1. A source region and a drain region of a first conductivity type, a channel region formed between the source region and the drain region, an insulating layer covering the channel region, and an insulating layer provided in proximity to the insulating layer. An insulated gate transistor having a gate electrode, wherein the channel region is adjacent to the insulating layer and has a second conductivity type and a low resistance, which is different from the first conductivity type; A second channel region adjacent to the region and having a first conductivity type and high resistance;
A third channel region of a second conductivity type, adjacent to the second channel region, wherein the second channel region is provided below and beyond the source and drain regions. And an impurity concentration of the second channel region is 10 ¹⁵ cm ⁻³ or less, and a depth of the first channel region is smaller than a depth of the source region and the drain region. 2. A source region and a drain region of a first conductivity type, a channel region formed between the source region and the drain region, an insulating layer covering the channel region, and an insulating layer provided close to the insulating layer. A semiconductor integrated circuit having an insulated gate transistor having a gate electrode, wherein the channel region is adjacent to the insulating layer and has a second conductivity type different from the first conductivity type and a low resistance first channel region. And a second channel region adjacent to the first channel region and having a first conductivity type and high resistance; and a third channel region adjacent to the second channel region and having a second conductivity type. the second channel region over the lower of the source and drain regions, and et provided beyond these region, the impurity concentration of the second channel region is at 10 ¹⁵ cm ^-3 or less, said first channel region The semiconductor integrated circuit having an insulated gate transistor depth is equal to or shallower than the depth of the source and drain regions. 3. The semiconductor integrated circuit according to claim 2, further comprising an MIS transistor having a gate applied voltage of zero and said second channel region being depleted. 4. An MIS having a first conductivity type fourth channel region between the first channel region and the second channel region.
4. The semiconductor integrated circuit according to claim 2, comprising a transistor. 5. The MIS transistor according to claim 1, wherein the potential distribution of the channel region is higher on the surface side when the voltage is applied to the gate electrode, and the carrier includes an MIS transistor flowing from the interface at least deeper than the mean free path of the carrier. 3. The semiconductor integrated circuit according to item 2. 6. The semiconductor integrated circuit according to claim 5, wherein said MIS transistor is an enhancement type transistor.