JPH04286124A - Manufacture of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To simplify manufacturing steps and to improve uniformity, and reproducibility of element characteristics by epitaxially growing a base electrode metal on an outer base layer of a heterojunction bipolar transistor. CONSTITUTION:When a heterojunction bipolar transistor having a structure in which main layers of a collector layer 3, a base layer 4, and an emitter layer 5 are laminated on a semiconductor substrate, is manufactured, a step of etching an outer region of the transistor to expose the base layer or a base layer sectional part, a step of regrowing an outer base layer, and a step of epitaxially growing a metal single crystal on the outer base layer, are included.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method for reducing the base resistance of a heterojunction bipolar transistor with good reproducibility and achieving high uniformity of the maximum oscillation frequency fmax on a wafer.

0002

[Prior Art] Heterojunction bipolar transistor (H
In order to improve the current gain cutoff frequency (fT), which is one index of high-speed characteristics, in BT), the base layer and collector layer, which are active layers, are being made thinner. Molecular beam epitaxy (MBE) and metal organic vapor phase epitaxy (
In recent years, ultra-thin film base layers of 500 angstroms or less have become commonplace due to thin film crystal growth technology using MOCVD (MOCVD), but on the other hand, an increase in base resistance due to thinning of the base layer has become a problem. As is well known, the maximum oscillation frequency (
The relationship between fmax) and current gain cutoff frequency (fT) is

[
Number 1]

0003

It is given by: Here RB is the base resistance,
CBC represents base-collector junction capacitance. According to the above equation, it can be seen that an increase in base resistance directly degrades fmax. Therefore, methods of reducing the base resistance while improving fT by making the base layer thinner are being considered.

Using FIGS. 4 and 5, fT, fma
A conventional example that aims to improve both x will be explained.

As shown in FIG. 4(a), semi-insulating GaA
On the s-substrate wafer 1, n+-GaAs (
Silicon impurity doping concentration: 5 x 1018 cm-3
), a 5000 angstrom thick collector layer 3 made of n--GaAs (silicon impurity doping concentration: 5 x 1016 cm-3), and a 5000 angstrom-thick collector layer 3 made of p+-GaAs (beryllium impurity doping concentration: 2 x 1019 cm). -3) with a thickness of 500 angstroms 4, N-
2500 angstrom thick emitter layer 5 made of Al0.3Ga0.7As (silicon impurity doping concentration: 5 x 1017 cm-3), 1500 angstrom thick emitter cap made of n+-GaAs (silicon impurity doping concentration: 5 x 1018 cm-3) Layers 6 are grown sequentially. Next, 2000 angstroms of heat-resistant electrode material WSi was deposited on the wafer by sputter deposition.
After forming a silicon oxide film 8 of 2000 angstroms, the emitter electrode 71 is processed by reactive ion etching (RIE) using SF6 gas.

As shown in FIG. 4(b), the emitter cap layer 6 and the emitter layer 5 are etched by reactive ion beam etching (RIBE) using Cl2 gas, and the etching is performed before the base layer 4 is exposed. Stop. Here, the emitter layer 5 left up to the base layer 4 has a thickness of about 50 mm.
0 angstrom to prevent damage to the crystal caused by dry etching from reaching the base layer 4. Next, a side wall 8s made of a silicon oxide film and having a thickness of 2500 angstroms is provided on the side surface of the convex portion of the emitter, and as shown in FIG.
As shown in c), the remaining emitter layer 5 and base layer 4 are completely removed by wet etching using a mixture of phosphoric acid, hydrogen peroxide, and water using the insulating film 8 and sidewall 8s as a mask.

Next, as shown in FIG. 5(d), trimethylgallium (C
GaAs is grown using a gas consisting of H3Ga) and arsine (As3H). At this time, the growth substrate temperature is set to 6, for example.
If a temperature of 00° C. is selected, regrowth will proceed only on the GaAs surface and GaAs will not grow on the silicon oxide film. In addition, in the regrown GaAs, carbon atoms (C) of CH3Ga are efficiently incorporated into arsenic (As) sites in a state of bonding with gallium atoms (Ga), so that the concentration is extremely high (approximately 1021C).
m-3) p-type external base layer 41 is formed. Here, the thickness of the external base layer 41 is set to be sufficiently thick at 2000 angstroms in order to reduce the series resistance within the base layer.

Next, as shown in FIG. 5E, a base electrode 72 made of titanium, platinum, and gold is deposited by a lift-off method using photoresist 9.

Finally, as shown in FIG. 5(f), the sub-collector layer 2 is exposed and a collector electrode 73 made of a gold germanium alloy is deposited by lift-off method as in FIG. 5(e) to complete the HBT. ing.

In this conventional HBT, the base layer 4 in the intrinsic region is sufficiently thin, so that a large fT can be obtained. On the other hand, since the external base layer 41 is thick and the series resistance within the base layer is reduced, and it is heavily doped, even a non-alloy base electrode can achieve a very low electrode contact resistivity on the order of 10-8 cm2.Ω. This contributes to the improvement of fmax.

0012

[Problems to be Solved by the Invention] The above HBT manufacturing method includes a crystal regrowth step, a crystal regrowth step,
The drawback is that it requires at least three steps: a photoresist step for electrode formation and an electrode metal vapor deposition step, and the number of steps is large. As shown in equation 1, fmax is inversely proportional to the square root of the base resistance RB, so the fluctuation of RB and fm
The relationship with the variation of ax is given by the following equation.

[0013]

[Math 2]

[0014]

[0015] Here, ΔRB and Δfmax are RB and fmax, respectively.
It represents the minute fluctuation range of max. Although the statistical average value of the contact resistance of the electrode is significantly reduced when using the extrinsic base regrowth method, the conventional method increases variations in the manufacturing process, as explained below. This will be explained using an energy band diagram near the semiconductor/metal interface shown in FIG. 6. In general, carriers 10 flowing perpendicularly to the semiconductor-metal interface have a path that passes over the Schottky barrier 11 (position 12a in the figure) and a path that crosses the Schottky barrier by a tunnel mechanism (position 12b in the figure). ) There are two possible routes. Note that 13 indicates the Fermi level. In the case of a very highly doped semiconductor, this internal tunneling mechanism becomes dominant, so the oxide film at the interface, surface contamination, etc. greatly affect the carrier tunneling mechanism. In the conventional method of forming a base electrode by normal vacuum evaporation, the GaAs surface is exposed to the atmosphere before the evaporation, so it is difficult to control the surface condition before the electrode is formed. Furthermore, the influence of residual photoresist in the photoresist opening cannot be ignored. These clearly contribute to intra-wafer and inter-wafer variations in base resistance. The impurity concentration of these external base layers was not very high (1019c
m-3 units), the absolute value of the base resistance was relatively large and did not pose much of a problem.

An object of the present invention is to provide a method for manufacturing a heterojunction bipolar transistor that eliminates the above-mentioned drawbacks.

[0017]

Means for Solving the Problems The present invention provides a method for manufacturing a heterojunction bipolar transistor having a structure in which main layers such as a collector layer, a base layer, and an emitter layer are laminated on a semiconductor substrate. etching an external region of the base layer to expose the base layer or a cross section of the base layer; regrowing an external base layer in the external region; and epitaxially growing a metal single crystal on the external base layer. It is characterized by containing.

[0018]

[Operation] Since the base electrode is epitaxially grown on the external base layer, a very stable semiconductor-metal interface is obtained, and a good and reproducible electrode contact resistance is obtained.

[0019]

[Embodiment] An embodiment of the present invention will be shown using FIGS. 1 and 2. The steps in FIGS. 1(a) to 1(c) are similar to those shown in FIGS. 4(a) to 4(c) in the conventional example.
This is exactly the same as the step (c).

In the step of FIG. 1(c), after removing the base layer 4 grown by MBE, a gas source MBE apparatus (referred to as GSMBE, MOMBE, etc.) which is equipped with a gas source in addition to an ordinary MBE apparatus using a solid source is used.
The wafers were loaded into the chamber.

As shown in FIG. 2(d), first, trimethylgallium (CH3Ga) and arsine (As3H)
A p-type external base layer 41 was formed by growing carbon (C)-doped GaAs to a thickness of 2,000 angstroms using a gas source consisting of . Next, an aluminum molecular beam is irradiated from an aluminum cell to form an aluminum thin film 72.
A was epitaxially grown to a thickness of 2000 angstroms. Aluminum and GaAs have different lattice constants, but after starting to grow aluminum on GaAs, aluminum becomes a single crystal after several atomic layers, and it has been confirmed that a thermally stable and ideal semiconductor-metal interface can be obtained. It was done. GaAs does not adhere to the silicon oxide film, but aluminum adheres to the silicon oxide film 8, as shown in Fig. 2(e).
), a photoresist 9 was applied to the wafer, and the aluminum 72a deposited on the silicon oxide film 8 was removed using phosphoric acid using oxygen plasma.

Next, as shown in FIG. 2(f), the unnecessary base electrode (aluminum thin film) 72a and the external base layer 41, as well as the collector layer 3 below them, are removed, and a collector electrode is formed on the sub-collector layer 3. 73 was installed and the HBT was completed.

In FIG. 3, a base layer 4 grown by MBE, which is almost the same as the embodiment of FIGS. 1 and 2, is shown.
without completely removing the external base layer 4 in the external region.
An example in which 1 was regrown is shown below. This increases the contact area between the regrown base layer 41 and the base layer 4, further reducing the contact resistance between the two base layers.

In each of the above embodiments, only the case where the emitter layer is located on the base layer is shown, but the present invention can also be applied to a collector top type HBT where the collector layer is located on the base layer. Further, the present invention is applicable not only to NPN type transistors but also to PNP type transistors. In addition, in the examples, the external base layer and base electrode metal were grown in a crystal growth chamber equipped with both a gas source and a solid source for deposition, but the external base layer and base electrode metal were grown without breaking the vacuum. The wafers may be grown in separate crystal growth chambers that can transport the wafers to each other. Further, after the growth of the external base layer, there is no problem in exposing the wafer to the atmosphere and then epitaxially growing the base electrode again, as long as the wafer surface treatment such as thermal cleaning is sufficiently performed before the growth. Although the embodiment has been described in which carbon is used as the p-type impurity in the external base layer, it goes without saying that the present invention is not limited to this, and other impurities such as beryllium, zinc, magnesium, and others may be used.

[0025]

Effects of the Invention As explained above, by the manufacturing method of the present invention, the current gain cutoff frequency fT, the maximum oscillation frequency fm
An HBT with excellent ax can be manufactured with good uniformity within a wafer in terms of characteristics and good reproducibility between wafers. Since the base electrode is formed at the same time as the external base regrowth process, there is an effect of shortening the manufacturing process period and reducing the number of man-hours.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a manufacturing process of an HBT according to a first embodiment.

FIG. 2 is an explanatory diagram showing the manufacturing process of the HBT according to the first example.

FIG. 3 is an explanatory diagram showing a manufacturing process of an HBT according to a second embodiment.

FIG. 4 is an explanatory diagram showing a conventional HBT manufacturing process that does not use the present invention.

FIG. 5 is an explanatory diagram showing a conventional HBT manufacturing process that does not use the present invention.

FIG. 6 is an explanatory diagram showing the energy band structure near the valence band at the semiconductor/metal interface.

[Explanation of symbols]

1 Semiconductor substrate 2 Sub-collector layer 3 Collector layer 4 Base layer 5 Emitter layer 6 Emitter cap layer 8 Insulating film 8s Side wall 9 Photoresist 10 Carrier 11 Schottky barriers 12a, 12b Carrier flow path 13 Fermi level 41 External base layer 71, 72, 73 Electrode 72a Base electrode (single crystal aluminum)

Claims (1)

[Claims] 1. A method for manufacturing a heterojunction bipolar transistor having a structure in which main layers such as a collector layer, a base layer, and an emitter layer are laminated on a semiconductor substrate, wherein an external region of the heterojunction bipolar transistor is etched. A heterojunction comprising the steps of exposing a base layer or a cross section of the base layer, regrowing an external base layer in the external region, and epitaxially growing a metal single crystal on the external base layer. A method of manufacturing bipolar transistors.