JPH04286043A - Command check device - Google Patents

Abstract

PURPOSE:To supply a superior automatic answering telephone system which detects the sound/silence of recorded ICM(In Coming Message), picture-displays the presence or absence of ICM in a display unit and displays the outline of an answer message. CONSTITUTION:ICM transmitted from a line is recorded in a tape recording part 20 and the silence of ICM is detected in a silence detection circuit 22. The result of detection is stored in ROM 13 and a content which is read from ROM 13 is converted into character information in a character information generation circuit 14. Then, it is displayed in the display unit 17 by using a display controller 15. CPU 11 selects only ICM detected to be 'present', and it is operated in a keyboard 16. Then, ICM recorded in the tape recording part 20 from a reproduction part 21 is reproduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a command check device in a protocol controller used when connecting peripheral devices of a computer.

0002

2. Description of the Related Art Protocol controllers are used to connect computer peripherals. When peripheral devices are connected in this way, instructions (commands) are transmitted between the devices. When transmitting commands in this way, it is necessary to check the commands.

[0003] Conventional command checking is based on SCSI (SCSI)
mall computer system I
Since the protocol controller (interface) did not have this function, it was performed using a CPU program.

FIG. 2 is a block diagram showing a system for implementing a conventional command check method. Figure 2
, the target T has a central processing unit (CPU).
) 1 and a SCSI protocol controller 2. The CPU 1 has a built-in program and executes this program. This CPU 1 is connected to a SCSI protocol controller 2. The SCSI protocol controller 2 is provided with a buffer 3. In addition, the SCSI protocol controller 2
It is connected to the initiator 5 via 4.

[0005] In a system configured in this way, the SC
When the SI protocol controller 2 receives a command from the initiator 5 and stores it in the buffer 3, the CPU
Program No. 1 checks the bit in the reserved area of the command, and if the bit is "1", switches the transfer phase to the status phase, transfers the status indicating an error, and transfers a message indicating the end of the command. Ta.

[0006]

[Problems to be Solved by the Invention] However, in the conventional command check method described above, since the check is performed by a CPU program, there is a drawback that the processing time becomes long, and a command check routine must be incorporated into the program. However, it also had the drawbacks of lengthening the development period and increasing program capacity.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a command check device that can shorten command check processing time.

[0008]

[Means for Solving the Problems] The present invention provides an apparatus comprising a target including a protocol controller that performs protocol control and a central processing unit that performs predetermined processing, and an initiator connected to this target via an interface. It includes a memory into which a bit pattern of a reserved area for each command can be written in advance according to a command from the central processing unit, a buffer for storing the command from the initiator, and a comparison means for comparing the contents of this buffer with the contents of the memory. This comparison means outputs a status indicating an error when a bit in the reserved area of the received command has a predetermined logical value.

[0009]

[Operation] The central processing unit writes the bit pattern of the reserved area for each command into the target memory in advance by a program, or configures the memory as a read-only memory, and the bit pattern of the reserved area for each command at the time of manufacturing. Write it down. The target then receives the command from the initiator and stores the command in a buffer. Next, the contents of this buffer are read from the beginning, and the contents of the built-in memory are read from the first byte, and these data are input to the comparing means. The comparison means outputs an error signal when a predetermined logical value is found in each of the data.

[0010] Here, when an error signal is output,
The transfer phase is switched to the status phase, a status indicating an error is transferred to the initiator, and then the transfer phase is switched to the message phase and the message is transferred. Also, the occurrence of an error signal is reported to the central processing unit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the illustrated embodiments.

FIG. 1 is a block diagram of a system including an embodiment of the command check device of the present invention. In FIG. 1, target 10 is connected to initiator 30 via SCSI 20. In FIG. The target 10 includes a CPU 11 with a built-in program and a SCSI protocol controller 12. The CPU 11 has
A SCSI protocol controller 12 is connected. This SCSI protocol controller 12 includes SCSI
I20 is connected. The SCSI protocol controller 12 includes a buffer 13, a status/message transfer circuit 14, a memory 15, and an address switching circuit 1.
6, address generation circuit 17, and clock generation circuit 18
and AND circuits 19 for 1 byte (8 pieces).

The operation of the embodiment configured as described above will be explained. The CPU 11 operates according to the program, sets the address switching circuit 16 to the CPU 11 side, and sets the address switching circuit 16 to the CPU 11 side.
A bit pattern of a reserved area for each command is written in the memory 15 in advance according to the addresses starting from 1. When the SCSI protocol controller 12 receives a command from the initiator 30 and stores it in the buffer 13, the first byte of the command stored in the buffer 13 is supplied to the address generation circuit 17. The address generation circuit 7 first generates and outputs an address based on the first byte. The address switching circuit 16 has already been switched to the address generation circuit 17 side, and the address generation circuit 17 has already been switched to the address generation circuit 17 side.
Outputs the address from. At this time, one byte worth of data is each output from the buffer 13 and the memory 15 to the AND circuit 19. These two pieces of data are ANDed in the AND circuit 19, and if even one bit of the data is “1”, an output signal “1” is output, which is sent to the CPU 11 and the status/message transfer circuit 14 as an error signal. is output to. Note that the clock output from the clock generation circuit 18 supplies timing for address increment to the buffer 13 and the address generation circuit 17 in order to check each byte of the received command.

When an error occurs, the status/message transfer circuit 14 switches the phase to the status phase and transfers the status indicating the error to the initiator 3.
0, then switch the transfer phase to the message phase and transfer the message.

According to the above embodiment, the data from the buffer 13 and the data from the memory 15 are ANDed by the AND circuit 19, and if even one bit of them is "1", it is determined as an error, and the command is checked. This reduces processing time and increases command throughput. Further, since there is no need to incorporate a command check routine into the program built into the CPU 11, the program development period can be shortened, and the program capacity can also be reduced. As a result, the load on the CPU is reduced, so the CPU can be allocated to other processing.

[0016]

[Effects of the Invention] As is clear from the above embodiments, according to the present invention, command checking is performed by a circuit, so that
This has the advantage of shortening processing time and increasing command throughput.

Furthermore, according to the present invention, there is no need to incorporate a command check routine into a program.
The development period can be shortened and the program capacity can be reduced.

Furthermore, according to the present invention, as a result, the CPU
Since the load on the CPU is reduced, the CPU can be allocated to other processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a command check device according to an embodiment of the present invention.

[Fig. 2] Fig. 2 is a block diagram showing a conventional device.

[Explanation of symbols]

10 target 11 CPU 12 SCSI protocol controller 13 buffer 14 status/message transfer circuit 15 memory 16 address switching circuit 17 address generation circuit 18 clock generation circuit 19 AND circuit 20 SCSI 30 initiator

Claims (1)

[Claims] Claim 1: A device comprising a target including a protocol controller that performs protocol control and a central processing unit that performs predetermined processing, and an initiator connected to this target via an interface, in accordance with instructions from the central processing unit. It is equipped with a memory into which a bit pattern of a reserved area for each command can be written in advance, a buffer for storing the command from the initiator, and a comparison means for comparing the contents of this buffer with the contents of the memory. A command check device that outputs a status indicating an error when a bit in a reserved area has a predetermined logical value.