JPH04284026A - A/d converter for multiple channels - Google Patents

Abstract

PURPOSE:To set a conversion rate different for each channel by using a common A/D conversion circuit by thinning timing to write A/D converted data in a memory. CONSTITUTION:A scan step number counter 5 is provided to set the number of times for A/D conversion in respect to one time of a sample pulse input, a scan information register 6 is provided to hold rate information corresponding to the number of times for conversion, and a thinning control circuit 18 is provided to divide the frequency of the sample pulse at a frequency dividing ratio corresponding to the rate information while being applied the rate information and to generate a timing signal for writing A/D converted signals in a data memory 17. Namely, the conversion rate is set for each channel, and the thinning control circuit 18 fetches the A/D converted data in the data memory 17 at the timing thinning the sample pulse according to the set conversion rate.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a multi-channel A/D converter that selectively converts a plurality of analog inputs from multiple channels into analog-to-digital conversion (hereinafter referred to as A/D conversion).
This paper relates to improvements in converters.

0002

2. Description of the Related Art Conventionally, a multi-channel A/D converter has a configuration shown in FIG. 7, for example. In the figure, 1 is a multiplexer that selects any one of multiple analog inputs provided from multiple channels CH1 to CHn, 2 is an amplifier that amplifies the analog input selected by multiplexer 1 with a predetermined gain, and 3 is an amplifier 2. This is an A/D conversion circuit that converts analog input amplified by A/D. 4 is a control circuit that scans the multiplexer every time a sample pulse is input, and converts the analog input input from each channel CH1 to CHn to the A/D conversion circuit 3.
Make D conversion. Further, the control circuit 4 sets the gain of the amplifier 2 for each channel.

[0003] An A/D converter uses such a multiplexer to A/D convert analog inputs provided from multiple channels.
In a D converter (hereinafter referred to as a multiplex type A/D converter), when a sample pulse is input once, the analog input of each channel is A/D converted once. Therefore, the conversion rate of each channel becomes common, and if you want to change the conversion rate, you need to prepare a circuit like the one shown in Figure 7 for each conversion rate. It ends up being extremely expensive.

0004

[Problems to be Solved by the Invention] The present invention has been made to solve these problems, and although it is a multiplex type A/D converter, it is capable of different conversion rates depending on the channel. The purpose of this invention is to realize a multi-channel A/D converter that can be set to

[0005]

[Means for Solving the Problems] The present invention is a multi-channel A/D converter configured as follows. (1) A multi-channel A/D converter selects multiple analog inputs from multiple channels using a multiplexer and converts the selected analog inputs into A/D. If the set value is N, the scan step counts from 0 to N when a sample pulse is input once. A number counter, conversion number information indicating the number of A/D conversions, rate information specifying the conversion rate, and channel number information specifying the channel number for A/D conversion correspond to each other. Each time the scan step number counter counts, the rate information and channel number information corresponding to the conversion number information that matches this count are read out, and the read channel number information is stored as is applied to the multiplexer to select a channel, and rate information read from the scan information register is provided, and the sample pulse is divided by a frequency division ratio according to this rate information. and a thinning control circuit that generates a timing signal for writing the A/D converted signal into the data memory. (2) It has an amplifier that amplifies the analog input selected by the multiplexer, and the scan information register includes range information that specifies the gain of the amplifier according to the range of the signal to be selected. - This range information is stored in correspondence with rate information and channel number information, and this range information is read out along with rate information and channel number information, and the gain of the amplifier is set using the read range information. Characteristic A described in (1)
/D converter.

[0006]

[Operation] In the present invention, the conversion rate is set for each channel.
The decimation control circuit takes in the A/D converted data into the data memory at the timing at which the sample pulses are decimated according to the set conversion rate. Further, a range is set for each channel, and A/D converted data is amplified according to the set range.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the drawings. Figure 1
1 is a configuration diagram of an embodiment of the present invention. Components in FIG. 1 that are the same as those in FIG. 7 are given the same reference numerals. In FIG. 1, 5 is a scan step number counter, and the number of channels to be scanned for one sample pulse input is set. This counter 5 receives a sample pulse and performs a counting operation by a preset value for each sample pulse input. For example, if the set value is N, the counter 5 will be 0, 1 for one sample pulse input.
, 2... Counts up to N. Reference numeral 6 denotes a scan information register, which is composed of, for example, a group of 9 bits×32 registers. FIG. 2 shows the format of the information stored in this register group.

In FIG. 2, 0 to 31 indicate the number of A/D
This is conversion number information indicating whether conversion is being performed. In the example of FIG. 2, up to 32 conversion count information are provided to match the number of channels connected to the multiplexer 1. GR0, GR1
is conversion rate information that specifies the conversion rate. In the example of FIG. 2, four types of conversion rates are specified using 2-bit information. RA0 and RA1 are range information specifying the amplification factor of the amplifier 2. This range information specifies in what range the analog input from the channel selected by the multiplexer is applied to the A/D conversion circuit. CA0 to CA4 are channel number information that designates channel numbers to be selected by the multiplexer. The contents of the scan information register 6 in such a format are read out using the count of the counter 5 given via the SRA bus 7 as an address, and the information corresponding to the number of conversions equal to this count. Returning to Figure 1 again, 8,
Reference numerals 9 and 10 are a CA bus, an RA bus, and a GR bus, to which the channel number, range information, and conversion rate information read from the scan information register 6 are transferred, respectively. CA
Based on the channel information transferred via bus 8, multiplexer 1 selects a channel number for A/D conversion from among 32 channels. The gain of the amplifier 2 is set based on the range information transferred via the RA bus 9. 11
is the A/D data converted from A/D by the A/D converter 3.
The A/D data bus 12 is connected to the A/D data bus 11 and the FIFO (First In First O
ut) A buffer for adjusting the transfer speed difference of the data bus 13; 14 is a FIFO memory in which data transferred by the FIFO data bus 13 is temporarily stored; 15 is F
A buffer 17 adjusts the transfer speed difference between the IFO data bus 13 and the data bus 16, and a data memory 17 stores data transferred by the data bus 16.

Reference numeral 18 thins out the sample pulses according to the conversion rate information transferred by the GR bus 10, and
This is a thinning control circuit that generates a signal that provides the timing to take data into the data memory 17. FIG. 3 is a diagram showing a specific example of the configuration of the thinning control circuit 18. As shown in this figure, the thinning control circuit 18 has four scan groups divided according to the sample clock thinning rate.
Frequency division counters 181 to 184 are provided for each group. Each of the counters 181 to 184 changes its count each time a sample clock is input, and when the counter counts up, it asserts the write request signals FW0' to FW3'. Note that signals marked with a bar in the drawings are indicated with a ' in the specification. Only data that has been A/D converted during the period in which this request signal is asserted is written into the FIFO memory 14. The frequency division value of the frequency division counter that determines the thinning rate of each scan group is set in advance, and the conversion rate information GR,
Which of the four counters is to be operated is determined depending on the contents of GR1.

Returning to FIG. 1, 19 is a write request signal F.
When W0' to FW3' are asserted, the FIFO controller section outputs a write address FIFO ADR to the FIFO memory 14 via the FIFO address bus 20. In the FIFI controller section 19, 191-194 are four write request signals FW0'-
This is a FIFO controller provided for each FW 3'. Of these four FIFO controllers 191-194, only the one to which the asserted write request signal is applied outputs the write address FIFO ADR. When the A/D converter 3 outputs the conversion end signal EOC',
The game in front of FIFO controllers 191 to 194
The gate is closed and the request signals FW0'-FW3' are no longer applied to the FIFO controllers 191-194. When write address FIFO ADR is output, FIFO
The A/D data written to the memory 14 is
data bus 11→buffer 12→FIFO data bus 13, and then written to the FIFO memory 14. FIFO
When data is written to the memory 14, the FIFO controllers 191-194 send transfer request signals REQ0-REQ.
Outputs 3. 21 is direct memory access
Controller (hereinafter referred to as DMAC), FIF
A/D data stored in O memory 14 is transferred to data memory 17 by DMA operation. When forwarding, please DM
AC 21 provides a write address to data memory 17 via address bus 22. In DMA transfer, transfer data is transferred to data memory 1 via FIFO memory 14 → FIFO data bus 13 → buffer 15 → data bus 16.
7 is written. When reading data from the FIFO memory 14, the FIFO controllers 191 to 19
4 generates a read address from the FIFO memory. The FIFO controllers 191 to 194 have two counters, use these counters depending on when reading and writing data from the FIFO memory 14, and generate read addresses and write addresses based on the count values. It is.

The operation of such an A/D converter will be explained. For example, if the contents shown in FIG. 4 are stored in the scan information register 6 and the scan step number counter 5 is set to "3", each time a sample pulse is input, the fourth , that is, numbers 0 to 3 are sequentially read out. In Figure 4, GR
, RA, and CA are channel number information, range information, and conversion rate information, respectively. In this case, the information transferred on each bus is as shown in FIG. For example, the content to be scanned third in FIG. 4 is that the scan rate group is 1, the amplifier range is 3, and the channel number to be scanned is 5. Such content corresponds to the part shown by arrow A in FIG. On the other hand, the frequency division counters 181 to 184 of each scan group shown in FIG. One of them performs a counting operation. As an example, frequency division counters 181 to 184
FIG. 6 shows the timing when operating at frequency division ratios of 1/2, 1/3, 1/4, and 1/5, respectively. However, it is assumed that the contents stored in the scan information register and the value set in the scan step number counter are the same as the examples shown in FIGS. 4 and 5. As shown in the time chart of FIG. 6, when a sample pulse is input, the analog input is scanned in the order of channel numbers 3, 2, 5, and 6. The data obtained by A/D converting the analog inputs input from channels No. 3 and No. 2 is processed at a rate of once every two sample pulses, that is, according to the frequency division clock of the frequency division counter 181 in the thinning control circuit 18. Data is collected at a frequency division ratio of 1/2. Analog input from channel 5 is connected to A/
D-converted data is collected at a frequency division ratio of 1/3, and data obtained by A/D conversion of the analog input input from channel No. 6 is collected at a frequency division ratio of 1/4. The data thus collected is once stored in the FIFO memory 14 and then written to the data memory 17. The conversion rate is controlled by thinning out the timing at which A/D converted data is written to the memory. For example, if the sample pulse frequency is 200kHz, 3
The conversion rate of channel inputs No. and No. 2 is 100kHz,
The conversion rate of the 5th channel input is 66.7kHz, 6
The conversion rate of the channel input will be 50kHz.

0012

[Effect of the invention] In the conventional multiplex type multi-channel A/D converter, the conversion rate of each channel is fixed, so if you want to set different conversion rates for each channel, you can change the conversion rate. It is necessary to provide an A/D conversion circuit for each rate, which increases cost. In contrast, in the present invention, the channels are divided into groups, and the A/D converted data is written to the memory at thinned out timings using a divided clock with a different frequency division ratio for each group. This changes the conversion rate. This allows the common A
/D conversion circuit to convert different conversion rates depending on the channel.
Can be set to In this way, the circuit cost per channel can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing the format of data stored in the scan step number counter in FIG. 1;

FIG. 3 is a diagram showing a specific configuration example of the thinning control circuit of FIG. 1;

FIG. 4 is an explanatory diagram of the operation of the A/D converter in FIG. 1;

FIG. 5 is an explanatory diagram of the operation of the A/D converter in FIG. 1;

FIG. 6 is an explanatory diagram of the operation of the A/D converter in FIG. 1;

FIG. 7 is a configuration diagram of a conventional example of an A/D converter.

[Explanation of symbols]

1 Multiplexer 2 Amplifier 3 A/D conversion circuit 5 Scan step number counter 6 Scan information register 17 Data memory 18 Thinning control circuit

Claims (2)

[Claims] Claim 1: A multi-channel A/D converter that selects a plurality of analog inputs from multiple channels using a multiplexer and converts the selected analog inputs into A/D.
If the data memory into which the /D-converted digital signal is written and the number of times A/D conversion is performed for one sample pulse input are set, and the set value is N,
A scan step number counter that counts from 0 to N when a sample pulse is input once, and a scan step number counter that counts from 0 to N when a sample pulse is input once.
Conversion number information indicating whether A/D conversion is performed, rate information specifying a conversion rate, and channel number information specifying a channel number for performing A/D conversion are stored in correspondence with each other. Every time the scan step number counter counts, the rate information and channel number information corresponding to the conversion number information that matches this count are read out, and the read channel number information is given to the multiplexer to select the channel. A scan information register to be selected and rate information read from this scan information register are given, and the sample pulse is frequency-divided at a frequency division ratio according to this rate information, and A/D converted signal is generated. A multi-channel A/D converter comprising: a thinning control circuit that generates a timing signal for writing the data into the data memory. 2. An amplifier that amplifies the analog input selected by the multiplexer, and the scan information register includes range information that specifies the gain of the amplifier according to the range of the signal to be selected, and the conversion number information. , rate information, and channel number information, and this range information is read out along with the rate information and channel number information, and the gain of the amplifier is set based on the read range information. The A/D converter according to claim 1, characterized in that: