JPH0428265A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To hold down the occurrence of interface level so as to obtain a semiconductor device of high reliability by a method wherein the thickness of a gate electrode is twice or less as large as that of an gate insulating film and larger than that of a monomolecular layer. CONSTITUTION:An N<+> source region 1 and an N<+> drain region 2 are provided sandwiching a P-type channel region provided to the surface of a P-type silicon substrate 8 between them. A gate oxide film 3 is deposited on a P-type channel region, a gate electrode 4 of polycrystalline silicone whose thickness is twice or less as large as that of the gate insulating film 3 and larger than that of a monomolecular layer is formed thereon. The upper limit of the thickness of an impurity doped polycrystalline silicon gate is set twice or less as large as that of an oxide film, and the lower limit is set larger than that of a monomolecular layer which is able to function as an gate electrode, practically, it is preferable that the thickness of the silicon gate is equal to those of 5-10 monomolecular layers. By this setup, electrons are prevented from being trapped in a gate insulating film and an interface level is also prevented from occurring at the injection of electrons into the insulating film.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to MISFET (Met) used in electronic equipment.
al-Insulator-5emiconducto
r Field-EffectTrans is to
r) type semiconductor device and its manufacturing method.

(Summary of the Invention) The present invention prevents the generation of electron traps in the insulating film and prevents the formation of electron traps in the insulating film by making the thickness of the gate electrode in a semiconductor device less than twice the thickness of the gate insulating film and more than a monomolecular layer. This suppresses the generation of interface states that occur when electrons are injected into the surface.

(Prior Art) Conventionally, the film thickness ratio of the gate insulating film of a semiconductor device and the gate electrode made of a polycrystalline silicon gate, etc., is usually about 1:6 to 1:8 (1:8) if the semiconductor device is an MO3 type transistor. (Figure 2), and if the semiconductor device was a floating gate memory transistor, the ratio was more than 1:10 (
Figure 3). In FIGS. 2 and 3, 1 is an n source region, 2 is an n drain region, 3 is a gate insulating film, and 8 is a gate insulating film.
4 is a P-type silicon substrate, 4 is a gate electrode, 5 is a floating gate electrode, and 6 is a control gate electrode.

The voltage shift of the C-V curve can be used to determine the relationship between the ratio of the number of electrons trapped in the insulating film, oxide film, and interface states in Figures 5 and 6; Point C in figure 6
As shown in Figure 3, 3000 insulating film for 100 or 200 people.
Approximately 0 gate electrodes are formed.

(Problem to be solved by the invention) As in the past, when the gate electrode film made of polycrystalline silicon gate etc. is thicker than the gate insulating film thickness, there are many electron traps in the insulating film (and the insulating film Many interface states were generated between the insulating film and the Si substrate due to electron injection into the silicon substrate, causing changes in the semiconductor device over time.Thus, if the semiconductor device is a transistor (MOS), it causes a change in the threshold value of the transistor. was. Furthermore, if the semiconductor device is a floating gate type memory transistor, electrons are trapped in the gate insulating film and in the interface level, causing a reduction in the number of times the memory can be rewritten.

(Means for Solving the Problems) In the present invention, the thickness of a gate electrode such as a polycrystalline silicon gate of a semiconductor device is made to be less than twice the thickness of a gate insulating film and more than a monomolecular layer.

(Function) A semiconductor device formed as in the present invention has fewer electron traps in the gate insulating film and fewer interface states generated by electron injection into the gate insulating film, so that changes over time of the semiconductor device are reduced. be able to.

(Example) Examples of the semiconductor device and its manufacturing method of the present invention will be described below based on the drawings. In the embodiment, an MO3 type semiconductor device using a silicon oxide film as the gate insulating film will be described, but it goes without saying that the invention is not limited to the silicon oxide film. Furthermore, although a polycrystalline silicon gate will be described as the gate electrode, it may be made of silicide, polycide, or the like.

(Example 1) FIG. 1 is a structural cross-sectional view of a Si N-channel MO8 type transistor according to the present invention. An n" source region 1 is formed on both sides of the P-type channel region on the surface of the P-type silicon substrate 8.
and an n+ drain region 2, a gate oxide film 3 is formed on the P-type channel region, and a polycrystalline film having a film thickness of at most twice the thickness of the gate oxide film and at least a monomolecular layer is formed thereon. A gate electrode 4 made of silicon is formed. The voltage shift of the CV curve in Figure 5 can be used to determine the relationship between the gate electrode film thickness and the ratio of the number of electrons trapped in the insulating film and in the interface state when using a gate oxide film of 100 people. . Here, curve a represents the characteristics of the semiconductor device of the present invention manufactured by dry oxidation, and curve a represents the characteristics of the semiconductor device of the present invention manufactured by oxidation mixed with Cl (chloro). represents.

From curve a, the upper limit of the thickness of the impurity-doped polycrystalline silicon film should be less than twice the oxide film thickness, and the lower limit should be at least 5 times the monomolecular layer that functions as a gate electrode.
~10 layers are preferred. It can be seen that when the value is within this range, electron traps are significantly reduced. Although an oxide film made of only oxygen or diluted oxygen is effective, it is understood from the curve that electron traps are further significantly reduced by mixing Cl (chloro) into the oxide film. The range of film thickness is similar to curve a.

- Methods of mixing Cl (chloro) into the oxide film include HCl oxidation, TCA (lichloroethane), TCE
() Lichlorethylene)! Oxidation method mixed in the base, C
There is ion implantation of 1,000 yen, etc., but here we will explain the general oxidation in which TCA is mixed into oxygen (TCA oxidation). When using TCA oxidation, 950°C-1050
It is effective to do this within the range of 'c. Also, C- in Figure 6
The voltage shift of the V curve can be used to determine the relationship between the gate electrode film thickness and the ratio of the number of electrons trapped in the insulating film and in the interface state when a 200-layer gate oxide film is used. Here, as in Fig. 5, the curve a is dry (Dry: Dr
y) represents the characteristics of the semiconductor device of the present invention manufactured by oxidation, and the curve represents the characteristics of the semiconductor device of the present invention manufactured by oxidation mixed with Cl (chloro),
In the same range as shown in FIG. 5, the characteristics are improved compared to the prior art.

(Example 2) FIG. 4 is a structural cross-sectional view of a floating gate type memory transistor according to the present invention. P-type silicon substrate 8
sandwiching the P-type channel region of n'' source region 1 and n
“ A floating gate made of polycrystalline silicon in which a drain region 2 is provided, a gate oxide film 3 is provided on the P-type channel region, and the film thickness is less than twice the gate oxide film thickness and more than a monomolecular layer. It has a structure in which an electrode 5 is provided, and a control gate electrode 6 is further provided on the electrode 5 with an insulating film 7 interposed therebetween.

(Embodiment 3) A cross-sectional view of the manufacturing process of a Si N-channel MO8 type transistor according to the present invention will be explained. FIG. 7(a) shows the gate oxide film 3 formed on the P-type channel region of the P-type silicon substrate 8. As shown in FIG. There are methods for forming the gate oxide film by thermal oxidation and CVD, but thermal oxidation was used here. FIG. 7(b) shows the formation of an impurity-doped polycrystalline silicon film 9 having a thickness less than twice the thickness of the gate oxide film and more than a monomolecular layer. A method for forming a thin gate electrode doped with impurities, which is less than twice the thickness of the gate oxide film and more than a monomolecular layer, is to form a first electrode by CVD or low pressure CVD, and then use POCli, etc. There are methods such as doping with impurities, but in terms of film thickness control, MLE
(Molecular Layer! Epitaxy
) is an excellent method to dope impurities after forming a thin gate electrode. Methods for forming a gate electrode with a thin film thickness while doping impurities include the CVD method in which a gas such as PH3 is mixed and the low pressure CVD method, but in terms of film thickness control, MLD (Molecular
The Layer Doping method is particularly excellent. In FIG. 7(C), an n-type impurity such as P or A3 is ion-implanted into the n source region 1 through the gate oxide film 3 using the resist or the resist and the gate electrode 4 as a mask.
and n゛ After forming the drain region 2, the resist is removed.

(Embodiment 4) Next, sectional views of another manufacturing process of a Si N-channel MO3 type transistor according to the present invention will be explained. FIG. 8(a) shows P
A gate oxide film 3 is shown formed on a P-type channel region of a type silicon substrate 8. FIG. 8(b) shows a state in which the polycrystalline silicon film 9 is doped with n-type impurities using a gas such as POCL after being formed. Figure 8 (C)
2 shows the polycrystalline silicon film 9 made thinner by etching to a thickness less than twice that of the gate insulating film and more than a monomolecular layer. FIG. 8(d) shows after forming an n source region 1 and an n+ drain region 2 by ion implantation of n-type impurities such as P or As through the gate oxide film 3 using the resist or the gate electrode 4 as a mask. , shows the resist removed.

(Example 5) Another sequential cross-sectional view of the manufacturing process of a Si N-channel MO3 type transistor according to the present invention will be explained. FIG. 9(a) shows P
A gate oxide film 3 is shown formed on a P-type channel region of a type silicon substrate 8. FIG. 9(b) shows the formation of an impurity-doped polycrystalline silicon film 9 having a thickness less than twice the thickness of the gate oxide film and more than a monomolecular layer. In this case, the polycrystalline silicon film 9 may be doped with impurities after it is formed, or the polycrystalline silicon may be formed while being doped with impurities. FIG. 9(C) shows that an insulating film 7 made of 5i02 or the like is formed by CVD or the like on the gate electrode 4-J: formed by photolithography, and then the gate electrode 4-J: is formed using the gate electrode 4 as a mask. By ion-implanting n-type impurities such as P and As through 7, an n' source region 1 and an n' drain region 2 are formed.
The figure shows the formation of the .

(Embodiment 6) An example of the manufacturing process of a floating gate type memory transistor according to the present invention will be described. FIG. 10(a) shows a gate oxide film 3 formed on a P-type channel region of a P-type silicon substrate 8 by thermal oxidation. FIG. 10(b) shows the formation of an impurity-doped polycrystalline silicon film 9 that will become a floating gate electrode and has a thickness less than twice that of the gate oxide film and more than a monomolecular layer. A method for forming a thin gate electrode doped with impurities of twice the thickness of the gate oxide film and more than a monomolecular layer includes forming the gate electrode by CVD or low pressure CVD, and then using poct, etc. There is a method of doping impurities with M L E (
Molecular Layer! pitaxy
) is an excellent method to dope impurities after forming a thin gate electrode. In addition, methods for forming a thin gate electrode while doping impurities include the CVD method in which a gas such as PH is mixed, the low pressure CVD method, etc.
In terms of film thickness control, MLD (Molecular
The Layer Doping method is particularly excellent. 1st
0 (C), an insulating film 7 is formed, and a control gate troll gate electrode 6 and a floating gate electrode 5 are formed on it.
This figure shows that an n' source region and an n' drain region 2 are formed by ion implantation through a gate oxide film 3 using as a mask.

(Embodiment 7) Another example of the manufacturing process of a floating gate type memory transistor according to the present invention will be described. FIG. 11(a) shows P
A gate oxide film 3 is shown formed on a P-type channel region of a type silicon substrate 8. FIG. 1I(b) shows that a polycrystalline silicon film 9 doped with impurities using a gas such as POCl2 is formed on the gate oxide film. FIG. 11C shows the polycrystalline silicon film 9 made to have a thickness less than twice that of the gate insulating film and more than a monomolecular layer by etching. FIG. 11(d) shows the insulating film 7.
After forming a control gate electrode 6 thereon, P and AS are formed through the gate oxide film 3 using the control gate electrode 6 and floating gate electrode 5 as masks.
This figure shows that an n1 source region 1 and an nl drain region 2 are formed by ion implantation of n-type impurities such as.

(Effects of the Invention) As described above, according to the present invention, a highly reliable semiconductor device can be manufactured by suppressing the generation of electron traps in the gate insulating film and the generation of interface states that occur when electrons are injected into the insulating film. can do. Although the case where the gate insulating film is relatively thin has been described here, the present invention can also be applied to a case where the gate insulating film is thick.

Furthermore, although only an N-channel semiconductor device has been described in the embodiment, a P-channel semiconductor device may also be used.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the structure of a Si N-channel MOS transistor, Figure 2 is a cross-sectional view of a conventional MOS transistor, Figure 3 is a cross-sectional view of a conventional floating gate memory transistor, and Figure 4 is a cross-sectional view of a conventional floating gate memory transistor. FIG. 5 is a structural cross-sectional view of the floating gate type memory transistor of the present invention, and the gate electrode film thickness and t, -V when the gate insulating film is 100 Ω
Figure 6 shows the relationship between the voltage shift of the curve and the voltage shift of the C-V curve. a)
8(C) are cross-sectional views in the order of manufacturing steps of the Si N-channel MOS transistor of the present invention, and FIGS. 8(a) to 8(d) are cross-sectional views in the order of manufacturing steps of the Si N-channel MOS transistor of the present invention. 9(a) to 9(C) are sectional views in order of other manufacturing steps of the Si N-channel MOS transistor of the present invention, and FIGS. 10(a) to 10(C) are floating gate type memories of the present invention. 11(a) to 11(d) show cross-sectional views in the order of manufacturing steps of the I transistor, and FIGS. 11(a) to 11(d) show sectional views in the order of the manufacturing steps of another floating gate type memory transistor of the present invention. 1... Source region 2... Drain region 3... Gate insulating film 4... Gate electrode 5... Floating gate electrode 6... Control gate)? ttfi7...Insulating film 8,... P-type silicon substrate 980. Polycrystalline silicon film Applicant Seiko Electronics Co., Ltd. Agent Patent attorney Keisuke Hayashi

Claims (4)

[Claims] (1) A first conductivity type channel region, a second conductivity type source and drain region spaced apart from each other with the region in between, a gate insulating film provided on the channel region, and a gate electrode provided on the insulating film. 1. A semiconductor device comprising: a gate electrode having a thickness not more than twice the thickness of a gate insulating film and a monomolecular layer or more; (2) forming a gate insulating film on the surface of a semiconductor region of a first conductivity type; and forming a gate electrode on the gate insulating film with a thickness of at most twice the thickness of the gate insulating film and at least a monomolecular layer; 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a source region and a drain region of a second conductivity type on the semiconductor surface on both sides of the gate electrode. (3) The semiconductor device according to item 1, wherein the gate insulating film contains Cl (chloro). (4) The method for manufacturing a semiconductor device according to item 2, wherein the gate insulating film contains Cl (chloro).