JP3191416B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, as the integration and speed of LSIs have increased, the size of MOS transistors has been reduced, and the gate length has reached half a micron. In a transistor in such a region, the short channel effect becomes a more serious problem. The short channel effect is
This occurs because the distance between the source and drain diffusion layers is reduced, and the depletion layers extending from the two diffusion layers are more likely to come into contact with each other. As a method for alleviating this problem, a reduction in the thickness of a gate oxide film is mentioned. In the half-micron region, an oxide thin film of about 10 nm is used.

With further miniaturization, the oxide film is reduced to a thickness of 8 nm or less, and a P-channel transistor, instead of a conventional buried channel type, uses a surface channel type transistor having a strong short channel effect. become.

However, in a Pch surface channel transistor, a P-type gate electrode must be formed. Therefore, different types of N-type and P-type gate electrodes are mixed in one LSI. Conventionally, the impurity doping of the gate electrode is usually formed by POCl ₃ diffusion, but this method cannot simultaneously form different conductivity type gate electrodes. In order to form a gate electrode of a different conductivity type, impurity doping by ion implantation becomes indispensable.

[0005] Ion implantation is performed by ionizing gaseous impurity molecules to form positively charged ions, accelerating the ions, and colliding the ions with a wafer. Therefore, the wafer surface is charged in the positive direction by the implanted ions.

FIG. 3 shows a state of charging at the time of ion implantation of an NchMOS capacitor. The P-type semiconductor substrate 1 is grounded, and the gate electrode 10 is charged in the positive direction. This positive charge loses its escape due to the oxide insulating film 3 between the semiconductor substrate and the gate electrode, and remains in the gate electrode. Therefore, an electric field is applied to the gate oxide film during ion implantation. Due to this electric field, the resistance of the gate oxide film is deteriorated and eventually destroyed.

As a means for preventing the oxide film from being destroyed due to charge-up, a method generally used is to supply electrons to the wafer surface and electrically neutralize it with positive charges. However, electrons are unlikely to enter the positive ion beam,
In addition, the state of charging is not uniform within the wafer and varies greatly depending on the implantation conditions, so that it is impossible to completely neutralize the charge.

[0008] Therefore, there has been proposed a method of preventing a breakdown of an oxide film by forming a passage for current flow from a gate electrode to a substrate.
FIG. 4 shows a method of forming an N-type gate electrode of a MOS transistor by ion implantation in a conventional technique disclosed in Japanese Patent Application Laid-Open No. 02-192723. By the element isolation region 2, the transistor region A and the contact region B
In the contact region B, the gate oxide film 3 is removed, and the upper gate electrode metal polycrystalline silicon 7 and the semiconductor substrate 1 are in direct contact.

The N-channel MOS constructed as described above
In the type transistor, since the positive charges in the gate electrode flow into the substrate in the contact region B, the gate electrode is not charged, and the breakdown of the gate oxide film can be prevented.

[0010]

However, in the above-described structure, the distance between the transistor region A and the contact region B is long, the resistance of the current path of the positive charge becomes high, and the current hardly flows. Further, when patterning the gate electrode, the etching selectivity between the polycrystalline silicon and the silicon substrate is small, so that there is a danger that the silicon substrate surface in the contact region may be dug down.

The present invention has been made in view of the above problems, and provides a method of manufacturing a semiconductor device having excellent resistance to gate insulating film destruction due to charge-up by ion implantation without digging a silicon substrate when forming a gate electrode.

[0012]

In order to solve the above-mentioned problems, an opening is formed by removing a part of a gate insulating film on a source / drain diffusion layer of a MOS transistor, and an opening is formed on a bottom surface of the semiconductor substrate. Preferably, an insulating film thinner than the gate insulating film is formed.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a first insulating film having a thickness of 10 nm or less on a semiconductor substrate;
Removing a part of the first insulating film on the source and drain regions of the transistor to form an opening reaching the semiconductor substrate; and forming a thinner than the first insulating film on the semiconductor substrate surface at the bottom of the opening. Forming a second insulating film;
Depositing a gate electrode material on the first and second insulating films and then implanting impurities into the gate electrode material using an ion implantation method, and forming a gate electrode using a photolithography method It is provided with.

[0014]

According to the present invention, the electric charge charged on the gate electrode material in the step of injecting impurities into the gate electrode material by using the ion implantation method is thinner than the first insulating film. Flows into the substrate through the opening in which the MOS transistor is formed, so that a MOS transistor with less damage to the gate insulating film can be formed. Further, since the second insulating film functions as a stopper for etching the gate electrode material, the semiconductor substrate is not dug.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing an N-type gate electrode of a MOS transistor according to one embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing a manufacturing method of an N-type gate electrode of a MOS transistor according to a first embodiment of the present invention.

In FIG. 1A, on a P-type silicon substrate 1,
After providing the element isolation region 2 using the LOCOS technology, 9
Thermal oxidation is performed in a pyro atmosphere at 00 ° C. to form a 9-nm gate oxide film 3 serving as a first insulating film. Next, patterning is performed using the photoresist 4, and the oxide film on the portions where the source and drain regions are to be formed is removed using hydrofluoric acid to form openings.

In FIG. 1B, thermal oxidation is performed in a dry atmosphere at 900 ° C. to form a second insulating film 5 in the opening.
A thermal oxide film 5 of nm is formed. At this time, an oxide film is also formed on the gate oxide film 3 and the element isolation region 2, and the thickness is set to about 1 nm.

In FIG. 1 (c), after polycrystalline silicon 7 is deposited on a semiconductor device by using a well-known vapor deposition method, arsenic ions are implanted under the conditions of a dose of 6.0E15 cm-2 and an acceleration energy of 40 KeV. I do.

In FIG. 1D, patterning is performed using a photoresist 9, and the polycrystalline silicon is etched by a dry etching method using the gate oxide film 3 and the thermal oxide film 5 as stoppers. Form electrodes and complete. Thereafter, a source transistor, a drain region, an interlayer insulating film, a source electrode, and a drain electrode are formed by using a known method to complete a MOS transistor.

In the method for manufacturing an N-type gate electrode of a MOS transistor configured as described above, a current easily flows in a thin portion as shown by a current path 8 in FIG. In addition, since the distance from the gate electrode forming portion is short, the resistance of the current path is small. Therefore, the electric charge charged on the gate electrode formation portion flows to the substrate through the current path 8, and the gate oxide film is hardly damaged.

In forming the gate, the thermal oxide film 5 functions as a stopper for etching the polycrystalline silicon, so that the silicon substrate 1 is not dug down.

(Embodiment 2) FIG. 2 is a cross-sectional view showing a manufacturing method of an N-type gate electrode of a MOS transistor according to a second embodiment of the present invention. This embodiment is characterized in that a nitride film 6 is used in place of the thermal oxide film 5 of the first embodiment.

In FIG. 2A, on a P-type silicon substrate 1,
After providing the element isolation region 2 using the LOCOS technology, 9
Thermal oxidation is performed in a pyro atmosphere at 00 ° C. to form a 9-nm gate oxide film 3 serving as a first insulating film. Next, patterning is performed using the photoresist 4, and an oxide film on the source and drain formation portions is removed using hydrofluoric acid to form an opening.

In FIG. 2B, in a nitrogen atmosphere at 950 ° C., the surface of the silicon substrate 1 at the opening and the gate oxide film 3 are formed.
Nitriding on the element isolation region 2 is performed. At this time, the thickness of the nitride film 6 on the opening silicon substrate serving as the second insulating film is set to about 2 nm. In the main nitriding step, RTA in a nitrogen atmosphere at 1000 ° C. may be used.

In FIG. 2C, arsenic ions are implanted under the conditions of a dose of 6.0E15 cm @ -2 and an acceleration energy of 40 KeV after polycrystalline silicon 7 is deposited on the semiconductor device by using a well-known vapor deposition method. I do.

In FIG. 2D, patterning is performed using a photoresist 9, and the polycrystalline silicon is etched by a dry etching method using the gate oxide film 3 and the nitride film 6 as stoppers to form a gate electrode. To complete.

In the method of manufacturing the N-type gate electrode of the MOS transistor configured as described above, as shown by the current path 8 in FIG. In addition, since the distance from the gate electrode forming portion is short, the resistance of the current path is small. Therefore, the electric charge charged on the gate electrode formation portion flows to the substrate through the current path 8, and the gate oxide film is hardly damaged.

In forming the gate, the nitride film 6 functions as a stopper for the polycrystalline silicon etching, so that the silicon substrate 1 is not dug down.

Further, since the upper portion of the gate oxide film is nitrided, the dielectric constant of the gate oxide film increases, the short channel effect is improved, and the driving force of the transistor increases.

In the first and second embodiments, the method of manufacturing the N-type gate electrode of the MOS transistor has been described. However, it goes without saying that these methods can be applied to the P-type gate electrode. Further, in the P-type gate electrode, the nitride film on the gate oxide film suppresses the diffusion of boron ions in the gate electrode. Therefore, there is also an effect of preventing seepage of boron ions into the substrate and suppressing fluctuation of the threshold voltage.

In the first and second embodiments, an oxide film is used as the first insulating film, but any material used for the gate insulating film such as tantalum oxide may be used.

[0033]

As described above, according to the present invention, the electric charge charged on the gate electrode material in the step of implanting impurities into the gate electrode material by using the ion implantation method is smaller than that of the first insulating film. Since it flows to the substrate through the opening in which the insulating film is formed, damage to the gate oxide film due to charge-up during ion implantation can be suppressed, and a MOS transistor having a gate oxide film of 10 nm or less can be formed.

[Brief description of the drawings]

FIG. 1 is a structural sectional view showing a manufacturing process of an N-type gate electrode of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a structural sectional view showing a manufacturing process of an N-type gate electrode of a MOS transistor according to a second embodiment of the present invention.

FIG. 3 is a schematic diagram showing a state of charging at the time of ion implantation of an NchMOS capacitor;

FIG. 4 is a structural sectional view showing a manufacturing process of an N-type gate electrode of a MOS transistor using a conventional method

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Element isolation region 3 Gate oxide film 4,9 Resist 5 Thermal oxide film 6 Nitride film 7 Polycrystalline silicon 8 Current path 10 Gate electrode

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroaki Nakaoka 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2-109370 (JP, A) JP-A-3-3 142937 (JP, A) JP-A-2-295113 (JP, A) JP-A-4-56276 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21 / 265 H01L 21/28 301 H01L 21/336 H01L 29/43

Claims (2)

(57) [Claims] 2. A semiconductor device comprising: a first substrate having a thickness of 10 nm or less on a semiconductor substrate;
Forming a part of the first insulating film on the source and drain regions of the MOS transistor by using a photolithography method.
Removing the opening to reach the semiconductor substrate, forming a second insulating film thinner than the first insulating film on the semiconductor substrate surface at the bottom of the opening; After depositing a gate electrode material on the insulating film, a step of injecting impurities into the gate electrode material using an ion implantation method, and a step of forming a gate electrode using a photolithography method are provided. A method for manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1 ,
Oite, the second using a nitride film as the insulating film, the first insulating film and a method of manufacturing a semiconductor device characterized by forming the nitride film on a semiconductor substrate surface of the opening bottom.