JPH0428257A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0428257A JPH0428257A JP2133020A JP13302090A JPH0428257A JP H0428257 A JPH0428257 A JP H0428257A JP 2133020 A JP2133020 A JP 2133020A JP 13302090 A JP13302090 A JP 13302090A JP H0428257 A JPH0428257 A JP H0428257A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- coolant
- groove
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 239000000758 substrate Substances 0.000 claims description 43
- 239000003507 refrigerant Substances 0.000 claims description 15
- 238000001816 cooling Methods 0.000 abstract description 14
- 239000002826 coolant Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- LUMVCLJFHCTMCV-UHFFFAOYSA-M potassium;hydroxide;hydrate Chemical compound O.[OH-].[K+] LUMVCLJFHCTMCV-UHFFFAOYSA-M 0.000 abstract 1
- 239000000463 material Substances 0.000 description 19
- 239000011521 glass Substances 0.000 description 14
- 239000002131 composite material Substances 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- HUAUNKAZQWMVFY-UHFFFAOYSA-M sodium;oxocalcium;hydroxide Chemical compound [OH-].[Na+].[Ca]=O HUAUNKAZQWMVFY-UHFFFAOYSA-M 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ＥＣＬ、ゲートアレイ、ＬＳＩメモリ等の
半導体素子が基板に実装された半導体装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor element such as an ECL, a gate array, or an LSI memory is mounted on a substrate.
第４図は従来の半導体装置を示す側面図であり、図にお
いて、（１）はシリコン（Ｓｉｌ製の半導体素子で、そ
の主面（２）には図示しない回路が形成されている。FIG. 4 is a side view showing a conventional semiconductor device. In the figure, (1) is a semiconductor element made of silicon (Sil), and a circuit (not shown) is formed on its main surface (2).
（３）は熱伝導率の大きい材料で作られた基板で、アル
ミナ（Ａ１２０３）や炭化ケイ素（ＳｉＣ） 、窒化ア
ルミニウム（ＡＩＮ）が用いられている。半導体素子（
１）の裏面（４）が基板（３）に対向するようにして、
半導体素子（１）が基板（３）に実装されている。この
実装は、基板（３）の表面に金（Ａｕ）等をメタライズ
して金（Ａｕ） −シリコン＜Ｓｉ）合金接合法により
行なうか、あるいは、厚膜ペースト等で接着して行なっ
ている。（５１は熱伝導率が大きく、加工性の良い金属
で作られた冷却フィンで、アユミニラム（Ａ１）や銅（
Ｃｕ）などが用いられ、断面がくし形の形状に加工され
て表面積が大きくなっている。(3) is a substrate made of a material with high thermal conductivity, such as alumina (A1203), silicon carbide (SiC), or aluminum nitride (AIN). Semiconductor element (
1) so that the back side (4) faces the substrate (3),
A semiconductor element (1) is mounted on a substrate (3). This mounting is carried out by metallizing gold (Au) or the like on the surface of the substrate (3) and using a gold (Au)-silicon<Si) alloy bonding method, or by bonding with a thick film paste or the like. (51 is a cooling fin made of a metal with high thermal conductivity and good workability, such as Ayuminilam (A1) or copper (
Cu) is used, and the cross section is processed into a comb shape to increase the surface area.
次に動作について説明する。半導体素子（１）を動作さ
せると発熱し、その熱は基板（３）を通して冷却用フィ
ン（５）に伝わる。冷却用フィン（５］には図示しない
ファンにより風が送られ、ここから外部へ放熱が行なわ
れる。Next, the operation will be explained. When the semiconductor element (1) is operated, it generates heat, and the heat is transmitted to the cooling fins (5) through the substrate (3). Air is sent to the cooling fins (5) by a fan (not shown), from which heat is radiated to the outside.
上記のように、半導体素子（１）で発生した熱はそこか
ら直接放散されるのではなく、基板（３）を経由して冷
却用フィン（５）から放散されるので、冷却効率が悪く
、急速な発熱や多大な発熱があった場合は十分冷却でき
ない。また、基板（３）の材料選定は熱伝導率の大きい
ことを優先的に考慮しなければならないので、使用材料
が限定されて、半導体素子（１）との間で熱膨張係数の
ミスマツチが生じる。As mentioned above, the heat generated in the semiconductor element (1) is not directly dissipated from there, but is dissipated from the cooling fins (5) via the substrate (3), resulting in poor cooling efficiency. If there is rapid heat generation or large amount of heat generation, sufficient cooling cannot be achieved. In addition, when selecting a material for the substrate (3), priority must be given to high thermal conductivity, which limits the materials that can be used and causes a mismatch in thermal expansion coefficient with the semiconductor element (1). .
そのため、半導体素子（１）のはがれや破損などの不具
合が発生する恐れがあり、特に大形Ｌ Ｓ Ｉのマルチ
チップ搭載には問題があった。Therefore, there is a risk that problems such as peeling and damage of the semiconductor element (1) may occur, which is particularly problematic when mounting multi-chips on large LSIs.
この熱膨張係数のミスマツチを防止するために、基板と
して、半導体素子と同種材料のシリコンを用い、基板内
に冷媒通路を形成し、ここに流す冷媒により半導体素子
を冷却する方法がある。しかし、この方法でも、半導体
素子の冷却は基板を通して間接的に行なうので、やはり
冷却効率が悪い。In order to prevent this mismatch in thermal expansion coefficients, there is a method in which silicon, which is the same material as the semiconductor element, is used as the substrate, a coolant passage is formed in the substrate, and the semiconductor element is cooled by the coolant flowing therethrough. However, even with this method, the semiconductor element is cooled indirectly through the substrate, so the cooling efficiency is still poor.
〔発明が解決しようとする課題〕
従来の半導体装置は以上のように構成されているので、
半導体素子が間接的に冷却され、従って、冷却効率が悪
く、半導体素子の温度上昇のために素子動作速度の低下
、誤動作、長時間動作不可などの問題点があった。更に
、Ａｌ２Ｏ３などの基板の場合は半導体素子との間の熱
膨張係数のミスマツチが生じ、そのため大形ＬＳＩ素子
などの実装が困難であった。[Problem to be solved by the invention] Since the conventional semiconductor device is configured as described above,
The semiconductor device is indirectly cooled, and therefore the cooling efficiency is poor, and the temperature of the semiconductor device increases, resulting in problems such as a decrease in device operating speed, malfunction, and inability to operate for a long time. Furthermore, in the case of a substrate made of Al2O3 or the like, a mismatch in thermal expansion coefficient occurs between the substrate and the semiconductor element, making it difficult to mount large-sized LSI elements and the like.
この発明は上記のような問題点を解消するためになされ
たもので、冷却効率が良く、がっ、半導体素子と基板間
の熱膨張係数のミスマツチによる不具合を防止できる半
導体装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor device that has good cooling efficiency and can prevent problems caused by mismatching of the coefficient of thermal expansion between the semiconductor element and the substrate. shall be.
この発明に係る半導体装置は、半導体素子の裏面に溝を
形成してそこに冷媒が流通できるようにしたものである
。In the semiconductor device according to the present invention, a groove is formed on the back surface of a semiconductor element so that a coolant can flow therein.
この発明における半導体装置は、半導体素子の裏面に形
成された溝に冷媒を流通させることにより半導体素子を
直接的に冷却する。また、基板としては熱伝導率を考慮
する必要がないので、その面から材料選定が限定されず
、半導体素子と同じないしは近似した熱膨張係数を有す
る材料を選定することができる。The semiconductor device according to the present invention directly cools the semiconductor element by flowing a coolant through a groove formed on the back surface of the semiconductor element. Furthermore, since there is no need to consider thermal conductivity for the substrate, material selection is not limited from this point of view, and a material having a coefficient of thermal expansion that is the same as or similar to that of the semiconductor element can be selected.
（づ）
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例による半導体装置の断面図であ
り、図において、（′７１はシリコン製の半導体素子で
、その主面（８）には図示しない回路が形成されている
。第２図は半導体素子（刀の平面図であり、第１図にお
いて下方から見た図を示し、（９）は裏面００）にジグ
ザグ状に形成された渦である。(d) Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. The figure is a plan view of a semiconductor element (sword), showing the view from below in FIG. 1, and (9) is a vortex formed in a zigzag shape on the back surface 00.
（１１）は半導体装置（１）が実装された複合基板、（
Ｉ２）、（１３）はそれぞれ単結晶シリコンで作られた
第１および第２の基板、（１４）、（１５）はソーダラ
イム系の第１および第２の薄膜ガラス層て、第１および
第２の基板（１２）、（１３）は第１の薄膜ガラス層（
１４）を介して互いに一体的に接合され、これらにより
複合基板（１１）を構成している。半導体素子（７）は
その裏面００）を第１の基板（１２）に対向させて、第
２の薄膜ガラス層（１５）を介して第１の基板（１２）
に接合されることにより、複合基板（１１）に実装され
、シリコン基板−Ｆへの素子実装（ｃｈｉｐｓ ｏｎ
５ｉｌｉｃｏｎ） 構造になっている。（１６）、（１
７）は第１の基板（１２）に形成された貫通孔と連絡路
で、半導体素子（７）の溝（９）の両端部（１９）と対
向する部分に貫通孔（Ｉ６）が設けられると共に、貫通
孔（１６）と連通するように連絡路（１７）が設けられ
ている。（２０）、（２１）は第２の基板（１３）に形
成された冷媒導入口と冷媒排出口で、それぞれ連絡路（
１７）と連通ずるように設けられ、以上により、冷媒導
入口（２０）から半導体素子ｆ７］の溝（９）を通って
冷媒排出口（２１）に至る一連の冷媒用通路が形成され
ている。(11) is a composite substrate on which the semiconductor device (1) is mounted, (
I2) and (13) are first and second substrates made of single crystal silicon, respectively; (14) and (15) are soda lime-based first and second thin glass layers; The second substrates (12) and (13) have a first thin glass layer (
14), and these constitute a composite substrate (11). The semiconductor element (7) is placed on the first substrate (12) via the second thin glass layer (15) with its back surface (00) facing the first substrate (12).
chips on the silicon substrate (F), and is mounted on the composite substrate (11).
5ilicon) structure. (16), (1
7) is a communication path with a through hole formed in the first substrate (12), and the through hole (I6) is provided in a portion facing both ends (19) of the groove (9) of the semiconductor element (7). At the same time, a communication path (17) is provided to communicate with the through hole (16). (20) and (21) are a refrigerant inlet and a refrigerant outlet formed in the second substrate (13), respectively, and communication paths (
17), and as a result, a series of refrigerant passages are formed from the refrigerant inlet (20) to the refrigerant outlet (21) through the groove (9) of the semiconductor element f7]. .
次に製造方法について説明する。半導体素子（力の裏面
００）に、リソグラフィ技術により製作された窒化シリ
コン（Ｓｉ ３Ｎａ ）や二酸化シリコン（Ｓｉ（ｈ）
のマスクく図示せず）を用い、フッ酸（ＨＦ）、水酸化
カリウム（ＫＯＨ）等のエツチング液でウェットエツヂ
フグ法により、溝（９）を形成する。冷却を良くするに
は溝（９）の表面積が大きいのが好ましいので、高アス
ペクト比の微細なパターンの溝（９）を形成するために
、Ｃ］、 ＯＯ）方位を有する半導体素子（７）をＫＯ
）（水溶液により異方性エツチングを行うのがよい。Next, the manufacturing method will be explained. Silicon nitride (Si3Na) and silicon dioxide (Si(h)) manufactured by lithography technology are used for semiconductor devices (back side 00).
The grooves (9) are formed using a wet etching method using an etching solution such as hydrofluoric acid (HF) or potassium hydroxide (KOH) using a mask (not shown). In order to improve cooling, it is preferable that the surface area of the groove (9) is large, so in order to form the groove (9) in a fine pattern with a high aspect ratio, the semiconductor element (7) having the C], OO) orientation is used. KO
) (Anisotropic etching is preferably performed using an aqueous solution.
第１の基板（１２）には、半導体素子（７）が実装され
る側とは反対側の面に、上記と同様のエツチングを行な
って連絡路（１７）形成のなめに溝状に加工し、また、
半導体素子（７１実装側の面から同様のエツチングによ
り貫通孔（１６）を形成する。第２の基板（１３）には
同様のエツチングにより、冷媒導入口および排出口（２
０）、（２１）を形成する。On the side of the first substrate (12) opposite to the side on which the semiconductor element (7) is mounted, etching is performed in the same manner as described above to form a diagonal groove to form a communication path (17). ,Also,
A through hole (16) is formed by similar etching from the surface on which the semiconductor element (71 is mounted).A refrigerant inlet and an outlet (2) are formed in the second substrate (13) by similar etching.
0), (21) are formed.
次に、第１および第２の基板（１２）、（１３）を陽極
接合法により互いに接合する。陽極接合法は、デイ−（
Ｄ） ピー（Ｐ）、ボメランッにより発明され、特公
昭５３−２８７４７２号公報に示されている。第３図は
陽極接合法の説明図であり、（２３）、（２４）は互い
に接合される第１および第２の材料で、第１の材料（２
３）は導体、あるいはシリコン等の半導体であるが、接
合時の温度では導体としてふるまう。第２の材料（２４
）はガラス等の絶縁物、（２５）は直流電源である。上
記のような両材料（２３）、（２４）を、第２の材料（
２４）がイオンマイグレーションする温度に加熱し、第
１の材料（２３）側を正、第２の材料（２４）側を負に
して直流電圧を印加することにより、両者の接合を行な
うものである。Next, the first and second substrates (12) and (13) are bonded to each other by an anodic bonding method. The anodic bonding method is
D) Invented by P. Bomeran and disclosed in Japanese Patent Publication No. 53-287472. FIG. 3 is an explanatory diagram of the anodic bonding method, in which (23) and (24) are the first and second materials to be bonded to each other, and the first material (2
3) is a conductor or a semiconductor such as silicon, but it behaves as a conductor at the temperature during bonding. Second material (24
) is an insulator such as glass, and (25) is a DC power source. Both materials (23) and (24) as described above are combined with the second material (
24) is heated to a temperature at which ion migration occurs, and the first material (23) side is positive and the second material (24) side is negative, and a DC voltage is applied to bond the two. .
実際の接合プロセスは以下に示す通りである。The actual bonding process is as shown below.
第１または第２の基板（１２）、（１３）の表面上に、
ＲＦマグネトロンスパッタ法等で厚さ１〜１０ミクロン
の第１の薄膜ガラス層（１４）を形成する。次に、両基
板（２３）、（２４）を約２００℃に加熱し、第１の薄
膜ガラス層（１４）を内側にして両者を重ね合せ、第１
の薄膜ガラス層（１４）が形成された側の基板を負、他
方を正にして両者間に直流電圧を印加し、接合を行なう
。第１の基板（１２）の溝状にエツチングされた部分と
第２の基板（１３）とにより、冷媒が通る連絡路（１７
）が形成される。上記接合は第１の薄膜ガラス層（１４
）の厚さが５ミクロン、加熱温度２００℃、印加直流電
圧２０Ｖの条件で行った場合に接合状態が最も良好とな
った。On the surface of the first or second substrate (12), (13),
A first thin glass layer (14) having a thickness of 1 to 10 microns is formed by RF magnetron sputtering or the like. Next, both substrates (23) and (24) are heated to about 200°C, and they are stacked on top of each other with the first thin glass layer (14) inside.
The substrate on which the thin film glass layer (14) is formed is made negative, and the other substrate is made positive, and a DC voltage is applied between them to perform bonding. The groove-shaped etched portion of the first substrate (12) and the second substrate (13) form a communication path (17) through which the refrigerant passes.
) is formed. The above bonding is performed using the first thin glass layer (14
) The bonding condition was the best when the thickness was 5 microns, the heating temperature was 200° C., and the applied DC voltage was 20 V.
このようにして第１および第２の基板（１２）、（１３
）を接合して複合基板（１１）を形成し、その上に半導
体素子（力を実装する。まず、第１の基板（１２）側表
面または半導体素子（７）の裏面に第２の薄膜ガラス層
（１５）を、第１の薄膜ガラス層（１４）の場合と同様
にして形成する。その後、上記と同様の陽極接合法によ
り両者の接合を行なう。In this way, the first and second substrates (12), (13
) are bonded to form a composite substrate (11), and a semiconductor element (forced) is mounted on it. The layer (15) is formed in the same manner as the first thin glass layer (14).Then, both are bonded by the same anodic bonding method as described above.
次に動作について説明する。半導体装置の運転時には冷
媒（図示せず）を流して冷却する。冷媒としては、半導
体素子（７１や複合基板（１１）の材料であるシリコン
とガラスを腐食しないフレオン類、あるいは、素子を低
温で動作させる場合は液体窒素を用いる。冷媒導入口お
よび排出口（２０）、（２１）には図示しないパイプが
接続されていて、例えばポンプなどにより、冷媒導入口
（２０）から冷媒を流し込む。冷媒は第１図の矢印で示
すように流れ、半導体素子（′７１の裏面αＯ）の溝（
９）を通って直接、半導体素子（力を冷却する。溝（９
）は大面積にわたって冷媒と接触する形状になっている
ので効率よく冷却が行なわれる。半導体素子（７１から
熱を奪った冷媒は、冷媒排出口（２１）からパイプを通
って排出される。Next, the operation will be explained. During operation of the semiconductor device, a refrigerant (not shown) is flowed to cool the semiconductor device. As the coolant, use Freon, which does not corrode the silicon and glass that are the materials of the semiconductor element (71) and the composite substrate (11), or liquid nitrogen when the element is operated at low temperatures. ) and (21) are connected to pipes (not shown), and a refrigerant is poured into the refrigerant inlet (20) using a pump, for example.The refrigerant flows as shown by the arrow in FIG. The groove on the back side αO) (
cooling the semiconductor element (power) directly through the groove (9).
) has a shape that makes contact with the refrigerant over a large area, so cooling is performed efficiently. The refrigerant that has taken heat from the semiconductor element (71) is discharged from the refrigerant outlet (21) through the pipe.
なお、上記実施例では陽極接合法による接合において、
互いに接合されるものの一方のみに薄膜ガラス層を形成
したが、多方に成膜して接合を行ってもよく、その場合
は印加直流電圧の極性はいずれでもよい。薄膜ガラス層
の厚さが２ミクロン、加熱温度２００℃、印加電圧２０
Ｖの条件で行った場合が、接合状態が最も良好である。In addition, in the above embodiment, in the bonding by the anodic bonding method,
Although the thin glass layer was formed only on one side of the parts to be bonded to each other, the thin glass layer may be formed on multiple sides and bonded, and in that case, the polarity of the applied DC voltage may be either. The thickness of the thin glass layer is 2 microns, the heating temperature is 200°C, and the applied voltage is 20°C.
The bonding condition is the best when the bonding is performed under the condition of V.
また、薄膜ガラス層の材質としてソーダライム系のもの
を用いたが、ホウケイ酸ガラス系でもよく、更に、溝（
９）のパターン形状をジグザグ状で全体として四角形に
したが、円形やらせん形のパターンにしてもよい。In addition, although soda lime-based material was used as the material for the thin glass layer, borosilicate glass-based material may also be used.
Although the pattern shape in 9) is zigzag and has a rectangular shape as a whole, it may also be a circular or spiral pattern.
以上のように、この発明によれば、半導体素子の裏面に
溝を形成して冷媒が流通できるように構成したので、冷
媒により半導体素子が直接的に冷却され、従って、冷却
効果が良く、また、基板の材料選定において熱伝導率の
面から限定されず、例えば半導体素子と同種の材料を用
いることができ、半導体素子と基板の間の熱膨張係数の
ミスマツチによる不具合を防止できる。As described above, according to the present invention, grooves are formed on the back surface of the semiconductor element so that the coolant can flow therethrough, so the semiconductor element is directly cooled by the coolant, and therefore the cooling effect is good. The selection of the material for the substrate is not limited in terms of thermal conductivity; for example, the same type of material as the semiconductor element can be used, and problems due to mismatch in thermal expansion coefficients between the semiconductor element and the substrate can be prevented.
第１図はこの発明の一実施例による半導体装置の断面図
、第２図は第１図に示された半導体装置の半導体素子の
平面図、第３図は陽極接合法の説明図、第４図は従来の
半導体装置の側面図である。
図において、（７）は半導体素子、（８）は主面、（９
）は溝、００）は裏面、（１１）は複合基板である。
なお、各図中同一符号は同一または相当部分を示す。
代理人 弁理士 大 岩 増 雄
手続補正書（自発）
１事件の表示
２発明の名称
平成２年特許願第１．３３０２０号
半導体装置
３補正をする者
事件との関係
住 所
名 称（６０１）
４代理人
住
所FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor element of the semiconductor device shown in FIG. 1, FIG. 3 is an explanatory diagram of an anodic bonding method, and FIG. The figure is a side view of a conventional semiconductor device. In the figure, (7) is the semiconductor element, (8) is the main surface, and (9) is the semiconductor element.
) is the groove, 00) is the back surface, and (11) is the composite substrate. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Patent Attorney Masuo Oiwa Procedural amendment (voluntary) 1. Indication of the case 2. Name of the invention 1990 Patent Application No. 1.33020 Semiconductor device 3. Person making the amendment Address related to the case Name (601) 4 Agent address
Claims (1)
、上記半導体素子の裏面を上記基板に対向させて、上記
半導体素子を上記基板に実装したものにおいて、半導体
素子の裏面に溝を形成して冷媒が流通できるようにした
ことを特徴とする半導体装置。The semiconductor element is composed of a substrate and a semiconductor element having a circuit formed on its main surface, and the semiconductor element is mounted on the substrate with the back surface of the semiconductor element facing the substrate, wherein a groove is formed on the back surface of the semiconductor element. A semiconductor device characterized in that a refrigerant is allowed to flow through the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133020A JPH0428257A (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133020A JPH0428257A (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0428257A true JPH0428257A (en) | 1992-01-30 |
Family
ID=15094919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2133020A Pending JPH0428257A (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0428257A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5692558A (en) * | 1996-07-22 | 1997-12-02 | Northrop Grumman Corporation | Microchannel cooling using aviation fuels for airborne electronics |
| US5777384A (en) * | 1996-10-11 | 1998-07-07 | Motorola, Inc. | Tunable semiconductor device |
-
1990
- 1990-05-23 JP JP2133020A patent/JPH0428257A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5692558A (en) * | 1996-07-22 | 1997-12-02 | Northrop Grumman Corporation | Microchannel cooling using aviation fuels for airborne electronics |
| US5777384A (en) * | 1996-10-11 | 1998-07-07 | Motorola, Inc. | Tunable semiconductor device |
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