CN117766490A - Heat dissipation packaging structure of integrated copper manifold micro-channel and preparation method - Google Patents
Heat dissipation packaging structure of integrated copper manifold micro-channel and preparation method Download PDFInfo
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Abstract
The invention discloses a heat dissipation packaging structure of an integrated copper manifold micro-channel and a preparation method thereof, wherein the packaging structure comprises a chip and a packaging cover plate; the packaging cover plate is configured as an inlet and outlet passage for liquid cooling medium and is connected with the chip to realize packaging; copper manifold micro-channels are embedded in the back surface of the chip or the lower bottom surface of the packaging cover plate. The inner surface of the manifold microchannel assembly is plated with metal copper, so that heat generated by the chip can be efficiently transferred to a cooling medium, the heat dissipation contact area is increased, the heat transfer resistance is reduced, the chip can be directly and rapidly dissipated, the pressure generated by the flowing of the liquid cooling medium is relieved, the mechanical stress on the chip is reduced, and the reliability and the stability of the chip in long-time work are improved by utilizing the characteristics of unequal widths and unequal lengths of the first microchannel and the second microchannel. The invention also utilizes the bonding layer between the packaging cover plate and the chip to form an integrated heat dissipation packaging structure, thereby maximally reducing the packaging volume and being beneficial to miniaturization and light weight of electronic equipment.
Description
Technical Field
The invention belongs to the technical field of semiconductor chip packaging, and particularly relates to a heat dissipation packaging structure of an integrated copper manifold microchannel and a preparation method thereof.
Background
Chip heat dissipation refers to a technique of effectively guiding heat generated by an electronic chip during operation to an external environment to maintain normal operation of the chip and to extend the life of the chip. With the rapid development of technologies such as 5G communication, automatic driving, artificial intelligence and the like, the data generation processing and communication rate of intelligent equipment are continuously improved, the performance requirements on a chip are higher and higher, and in order to keep the development speed, the computing power of a data center is doubled basically after 3.5 months, for example, the OpenAI company in the united states. The continued advancement in integrated circuit technology has led to more integration and miniaturization of electronic chips, resulting in higher and higher power densities of the chips. At present, the improvement of the performance and the power density of the chip causes a large amount of heat to be generated during operation, the operation speed of the chip is influenced by the heat, the operation frequency of the chip is reduced, and irreversible damage is caused under severe conditions. To avoid this, microsoft corporation of america, for example, places its data center on the seafloor and google on the nordic finland where the climate is severe. Heat dissipation management is one of the major challenges for future electronic chips.
Currently, the mainstream chip heat dissipation technology includes air cooling, liquid cooling and refrigeration technology. The air cooling technology is to utilize a fan or a radiating fin and other devices to radiate heat of the chip into the air in a convection and radiation mode. The technology is simple, low in cost and high in reliability, but with the improvement of the integration level and the power consumption of the chip, the air cooling technology is difficult to meet the heat dissipation requirement, and the problems of noise, electromagnetic interference and the like can be generated. The refrigeration technology utilizes refrigerant or thermoelectric material to realize active cooling of the chip through compression or current. The technology can lead the temperature of the chip to be lower than the ambient temperature, and improve the performance and the reliability of the chip, but the technology also needs to consume extra energy, increase the weight and the volume of the system, and solve the problems of environmental influence of the refrigerant and the like. The liquid cooling technology uses liquid as a cooling medium, and heat of a chip is transferred to the cooling medium through a pump or natural circulation. The technology has the advantages of high heat dissipation efficiency, uniform temperature, low noise and the like. Conventional liquid cooling techniques require one or two layers of thermal interface material (e.g., silicone grease, cover plate) between the chip and the coolant, and thermal flow resistance between the thermal interface material layer and the chip, cover plate, and cold plate can occur, which can make efficient heat transfer difficult. In addition, the volume required for this solution is too large, which reduces the power density and prevents integration, and the current demands for miniaturization and light weight are not matched.
Aiming at the liquid cooling technology, the common liquid cooling micro-channels at present are divided into a non-embedded type micro-channel and an embedded type micro-channel. The former requires heat transfer to the microchannel cold plate via an intermediate thermal interface material and then dissipated by liquid, which has the disadvantages of large size and thermal resistance. The latter is to manufacture the micro-channel directly behind the chip by etching, which is complex, costly and incompatible with existing equipment production and assembly processes. In addition, when the liquid passes through, larger pressure is generated, the power of the liquid pump is increased, and the local warping of the chip caused by destructive mechanical stress is generated, so that the reliability and the stability of the chip are not guaranteed.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a heat dissipation packaging structure of an integrated copper manifold microchannel and a preparation method thereof, wherein a plurality of manifold microchannels plated with metal copper are arranged on the back surface of a chip, so that a trigger heat source can be connected in a short distance and heat can be transferred efficiently, and a bonding layer is arranged below a packaging cover plate provided with a liquid inlet and a liquid outlet, so that the heat dissipation structure can be packaged completely, and the integrated heat dissipation packaging structure is formed.
In a first aspect of the present invention, the present invention provides a heat dissipation package structure integrating copper manifold micro-channels, comprising:
a chip;
the packaging cover plate is configured as an inlet and outlet channel of a liquid cooling medium and protects the chip;
a manifold microchannel assembly configured to dissipate heat from the chip;
the manifold microchannel assembly is arranged on the back surface of the chip and connected with the packaging cover plate, or is arranged on the lower bottom surface of the packaging cover plate and connected with the chip;
further, liquid inlets and outlets for liquid cooling medium are formed in two sides of the packaging cover plate; the liquid inlet and outlet penetrates through the packaging cover plate;
further, the chip and the packaging cover plate are connected by bonding,
further, the manifold microchannel assembly comprises first microchannel units and second microchannel units which are alternately distributed along the width direction of the chip, wherein the first microchannel units comprise n1 first microchannels, n1 is more than or equal to 1, the second microchannel units comprise n2 second microchannels, n2 is more than or equal to 1, and the adjacent microchannels have a distance d, d is more than 0;
further, the shape of the first micro-channel is a conical strip structure at two ends; the shape of the second micro-channel is a cuboid strip structure;
further, the length direction axis of the first micro-channel is perpendicular to the length direction axis of the liquid inlet and outlet; the length direction axis of the second micro-channel is perpendicular to the length direction axis of the liquid inlet and outlet;
further, the length of the liquid inlet and outlet is greater than the width of the manifold microchannel assembly;
further, if the manifold microchannel assembly is arranged on the back surface of the chip, the two side end parts of the manifold microchannel assembly are positioned right below the liquid inlet and outlet; if the manifold microchannel assembly is arranged on the lower bottom surface of the packaging cover plate, the two side end parts of the manifold microchannel assembly are positioned in the liquid inlet and outlet;
further, the width of the liquid inlet and outlet is 5-10 times of the distance d between the adjacent micro-channels.
Further, the length of the first micro-channel is greater than the length of the second micro-channel, and the width W1 of the first micro-channel is greater than the width W2 of the second micro-channel, w1= [2×w2,5×w2];
further, a copper metal coating layer is arranged on the inner surface of a manifold microchannel of the manifold microchannel assembly, and the copper metal coating layer comprises a barrier layer, a metal adhesion layer, a copper seed crystal layer and a copper bonding layer;
in a second aspect of the present invention, the present invention provides a method for forming a heat dissipation package structure integrated with a copper manifold microchannel, comprising:
s1, preparing a packaging cover plate, and etching liquid inlet and outlet holes penetrating through the packaging cover plate on two sides of the packaging cover plate;
preferably, according to the given size of the chip, defining the size of a single packaging cover plate on the wafer, obtaining the single packaging cover plate in a cutting mode, defining the pattern of a liquid cooling medium inlet and a liquid cooling medium outlet through a photoetching process, etching a liquid inlet and a liquid outlet of the packaging cover plate through an etching process, and carrying out chemical mechanical polishing/grinding on the back surface of the packaging cover plate to obtain the liquid inlet and the liquid outlet penetrating through the packaging cover plate;
preferably, according to the given size of the chip, defining the size of the packaging cover plate on the wafer, defining the pattern of the liquid cooling medium inlet and outlet on the packaging cover plate on the wafer through a photoetching process, etching the liquid inlet and outlet of the packaging cover plate through an etching process, and carrying out chemical mechanical polishing/grinding on the back of the wafer to obtain the liquid inlet and outlet penetrating through the packaging cover plate;
preferably, according to the given size of the chip, defining the size of a single packaging cover plate on a wafer, obtaining the single packaging cover plate in a cutting mode, defining a pattern of liquid cooling medium inlets and outlets parallel to two ends and a manifold microchannel pattern perpendicular to the liquid inlet and outlet through a photoetching process, etching the liquid inlet and outlet and the manifold microchannel of the packaging cover plate through an etching process, and carrying out chemical mechanical polishing/grinding on the back surface of the packaging cover plate to obtain the liquid inlet and outlet penetrating through the packaging cover plate;
preferably, according to the given size of the chip, defining the size of the packaging cover plate on the wafer, defining the patterns of the liquid cooling medium inlet and outlet and manifold micro-channel patterns perpendicular to the liquid inlet and outlet on the packaging cover plate on the wafer through a photoetching process, etching the liquid inlet and outlet and manifold micro-channel of the packaging cover plate through an etching process, and carrying out chemical mechanical polishing/polishing on the back of the wafer to obtain the liquid inlet and outlet penetrating through the packaging cover plate;
step S2, etching the manifold microchannel assembly on the back surface of the chip or the lower bottom surface of the packaging cover plate; the inner surface of a manifold microchannel of the manifold microchannel assembly is provided with a copper metal coating layer;
preferably, a silicon dioxide barrier layer with high mass density is grown on the lower bottom surface of the packaging cover plate etched with the manifold microchannel assembly through a dry oxidation process, then a metal adhesion layer is deposited through a deposition process, then a copper metal is deposited as a copper seed layer through a deposition process, and finally copper metal is plated as a copper bonding layer through an electroplating process.
More preferably, a pattern of the manifold micro-channel is defined on the back of the chip through a photoetching process, and then an etching process is adopted to etch a certain thickness on the back of the chip to form the manifold micro-channel under the condition that the depth of the transistor is determined and the electrical property of the chip is not affected;
and growing a silicon dioxide barrier layer with high mass density on the back surface of the chip with the manifold microchannel assembly through a dry oxidation process (low temperature), depositing a silicon nitride barrier layer through a chemical vapor deposition process, depositing a metal adhesion layer through a plasma enhanced chemical vapor deposition process, depositing a copper metal serving as a copper seed layer through a plasma enhanced chemical vapor deposition process, and plating a copper bonding layer through an electroplating process.
S3, preparing an integrated copper manifold microchannel heat dissipation packaging structure;
preferably, the copper bonding layer of the package cover plate is polished by a chemical mechanical polishing process; processing the copper bonding layer of the chip through an inert gas plasma processing technology; carrying out acid washing treatment on the lower bottom surface of the packaging cover plate and the back surface of the chip, and then cleaning and drying; and (3) processing for a certain time under a certain temperature and pressure in an inert gas atmosphere through a hot pressing process, so as to finish the bonding of the single chip or wafer level packaging cover plate and the chip.
Compared with the prior art, the invention has at least the following beneficial effects:
(1) According to the integrated copper manifold microchannel heat dissipation packaging structure and the preparation method, in the integrated copper manifold microchannel heat dissipation packaging structure, the manifold microchannel components with the surfaces plated with metal copper are embedded in the chip and the packaging cover plate, so that heat generated by the chip can be efficiently transferred to a cooling medium, the manifold microchannel components are composed of the first and second microchannels with different shapes, the heat dissipation contact area is increased by utilizing the characteristics of unequal widths and unequal lengths of the first and second microchannels, the heat transfer resistance is reduced, and the chip can be directly and rapidly dissipated;
(2) The manifold microchannel assembly is formed by the first and second microchannels with different shapes, and the pressure generated by the flowing of the liquid cooling medium is relieved, the mechanical stress on the chip is reduced, and the reliability and stability of long-time work of the chip are improved by utilizing the characteristics of unequal widths and unequal lengths of the first and second microchannels;
(3) The bonding layer between the packaging cover plate and the chip is utilized, the packaging cover plate, the chip and the heat dissipation structure formed by the manifold microchannel component with the surface plated with metal copper can be completely packaged, an integrated heat dissipation packaging structure is formed, the packaging volume can be maximally reduced, the miniaturization and the light weight of electronic equipment are facilitated, and the process is compatible with the subsequent process of an integrated circuit, and the cost is low.
Drawings
To further clarify the advantages and features present in various embodiments of the present invention, a more particular description of various embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be denoted by the same or similar reference numerals.
FIG. 1 is a schematic diagram of a layered structure of an integrated copper manifold microchannel heat sink package according to one embodiment of the invention, wherein FIG. 1: 101 is a packaging cover plate, 102 is a liquid inlet and outlet, 103 is a chip, and 104 is a manifold microchannel;
FIG. 2 shows a top view of a package cover plate with inlet and outlet ports on both sides;
FIG. 3 shows a side view of a package cover;
FIG. 4 shows a cross-sectional view of the middle of the package cover;
fig. 5 shows the copper metal bonding layer at the bottom of the package cover, fig. 5: 201 is a silicon dioxide barrier layer, 202 is a metal adhesion layer, 203 is a seed layer of copper metal, 204 is a copper metal layer;
fig. 6 shows a top view of a copper manifold microchannel chip on the back, fig. 6: 301 is a first microchannel and 302 is a second microchannel;
FIG. 7 shows a side view of a chip;
FIG. 8 shows a cross-sectional view of the middle of a chip;
fig. 9 shows the metal layer on the back side copper manifold microchannel of the chip, fig. 9: 401. a silicon dioxide barrier layer 405, a silicon nitride barrier layer 402, a chromium metal adhesion layer 403, a copper seed layer 404, a copper bonding layer 405, a barrier layer;
fig. 10 is a schematic diagram of a layered structure of an integrated copper manifold microchannel heat sink package according to another embodiment, and fig. 10 shows: 501 is a packaging cover plate, 502 is a liquid inlet and outlet, 503 is a chip, and 504 is a manifold microchannel.
Detailed Description
It should be noted that the components in the figures may be exaggerated for illustrative purposes and are not necessarily to scale.
In the present invention, the embodiments are merely intended to illustrate the scheme of the present invention, and should not be construed as limiting.
In addition, embodiments of the present invention are performed in a particular sequence of process steps, but the sequence in which the process steps are performed is not limited to better distinguishing between various parts, and the steps may be adjusted according to the process for efficient production.
The invention is further elucidated below in connection with the detailed description and with reference to the drawings.
Example 1
FIG. 1 illustrates a schematic diagram of a layered structure of an integrated copper manifold microchannel heat sink package in accordance with one embodiment of the present invention. As shown in fig. 1, the heat dissipation package structure includes a package cover 101, liquid inlets and outlets 102 on two sides of the package cover, a chip 103, and a copper manifold microchannel assembly 104 on the back of the chip.
The packaging cover plate 101 is arranged on the chip 103 through a bonding process, the liquid inlet and outlet ports 102 on two sides of the packaging cover plate 101 are arranged at two ends of the copper manifold micro-channel, the cooling liquid flows into the liquid inlet and outlet ports 102, and heat generated during the operation of the chip 103 is taken away through the copper manifold micro-channel assembly 104.
The forming method of the integrated copper manifold micro-channel heat dissipation packaging structure comprises the following steps:
step 1, preparation of the package cover plate 101. Designing the size of a packaging cover plate according to the given chip size, and then obtaining a single packaging cover plate 101 through a wafer dicing process; the material of the packaging cover plate is not limited to silicon chips, and glass, copper plates, stainless steel plates and PCBs can be adopted.
Carrying out organic ultrasonic cleaning on the single-chip packaging cover plate 101 by using acetone, isopropanol and deionized water to remove impurities such as surface dust; then, inorganic cleaning is carried out by adopting a mixed solution of hydrochloric acid and hydrogen peroxide to remove surface oxides and possibly residual metal elements;
the distribution of manifold micro-channel components 104 is designed according to a given chip size, the positions and the sizes of the inlets and the outlets 102 are designed, the shapes of the inlets and the outlets 102 are defined on the single packaging cover plate 101 through a photoetching process, then the inlets and the outlets 102 are completely etched through the whole packaging cover plate 101 through an etching process, at the moment, the top view of the packaging cover plate 101 is shown in fig. 2, the side view is shown in fig. 3, and the middle cross section is shown in fig. 4;
a dry oxidation process is applied to the smooth surface of the packaging cover plate 101, and a layer of high-quality and compact silicon dioxide with the thickness of 100 nanometers is grown to serve as a barrier layer 201; then a layer of 20 nm chromium metal is deposited on the surface by high vacuum physical vapor deposition as a copper adhesion layer 202; then depositing a layer of 50 nm copper metal by high vacuum physical vapor deposition to be used as a seed crystal layer 203 of the subsequent electroplated copper, namely a conductive layer; finally, a 100 to 1000 nm thick layer of copper is electroplated as a subsequent copper bonding layer 204 by a copper electroplating apparatus. As shown in fig. 5, on the encapsulation cover 101 are in order a silicon dioxide barrier layer 201, a chromium metal adhesion layer 202, a copper metal seed layer 203, and a copper bonding layer 204.
Step 2, preparing the chip with the copper manifold micro-channel on the back surface.
Defining a designed manifold microchannel assembly 104 on the back surface of a chip 103 through a photoetching process, wherein the manifold microchannel assembly 104 is formed by alternately distributing a first microchannel 301 and three second microchannels 302 along the width direction of the chip, and the adjacent microchannels have a distance d;
the shape of the first micro-channel 301 is a conical strip structure at two ends; the shape of the second micro-channel 302 is a cuboid strip structure;
the longitudinal axis of the first micro channel 301 is perpendicular to the longitudinal axis of the liquid inlet/outlet 102; the longitudinal axis of the second micro channel 302 is perpendicular to the longitudinal axis of the liquid inlet/outlet 102;
the length of the liquid inlet and outlet 102 is greater than the width of the manifold microchannel assembly 104, and the end of the manifold microchannel assembly 104 is positioned in the liquid inlet and outlet 102 when the subsequent bonding is performed; the width of the inlet/outlet 102 is 5-10 times the spacing d between adjacent microchannels.
The length of the first micro-channel 301 is greater than the length of the second micro-channel 302, and the width W1 of the first micro-channel 301 is greater than the width W2 of the second micro-channel 302, w1= [2×w2,5×w2];
determining the etching depth of the manifold microchannel assembly 104 on the back side of the chip 103 according to the working position of the transistor of the chip 103, and etching 50% -60% of the depth on the premise of not obstructing the working of the transistor, namely the working of the chip and not affecting the performance and the reliability of the chip on the chip with the shape of the manifold microchannel assembly 104 defined by the etching process, wherein the top view of the chip 103 with the manifold microchannel assembly 104 on the back side is shown in fig. 6, the middle cross section is shown in fig. 7, and the side view is shown in fig. 8;
a layer of high quality and dense silicon dioxide 100 nm thick is grown as a barrier layer 401 on the back side of the chip 103 from which the manifold microchannel assembly 104 has been etched by a dry oxidation process; then a layer of 50 nm high-quality dense silicon nitride is deposited as a barrier layer 405 by a high vacuum chemical vapor deposition process; thus, the subsequent copper metal is strictly ensured not to diffuse into the chip in the operation of the chip 103, so that reliability and stability problems are caused;
depositing a 20 nm layer of chromium metal as a copper adhesion layer 402 by a high vacuum physical vapor deposition process; then depositing a layer of 50 nm copper metal by high vacuum physical vapor deposition to be used as a seed crystal layer 403 of the subsequent electroplated copper, namely a conductive layer; finally, a 100 to 1000 nm thick layer of copper is electroplated as a subsequent copper bonding layer 404 by a copper electroplating apparatus. As shown in fig. 9, the manifold microchannel surface is, in order, a silicon dioxide barrier layer 401, a silicon nitride barrier layer 405, a chromium metal adhesion layer 402, a copper seed layer 403, and a copper bonding layer 404.
Step 3, bonding of the package cover 101 and the chip 103 with the copper manifold microchannel assembly 104 on the back side, and formation of monolithically integrated copper manifold microchannel heat dissipating package structure.
The surface of the packaging cover plate 101 with the copper bonding layer 204 is properly polished through a chemical mechanical polishing process, so that the flatness of the surface is improved; argon plasma treatment is carried out on the back surface (namely, the surface with the copper bonding layer 404) of the micro-channel component 104 of the chip 103 with the copper manifold under a certain power; before bonding, putting the two materials into sulfuric acid for soaking for a certain time to completely remove impurities such as oxides on the surface, and finally flushing with deionized water and drying with nitrogen;
through the hot-press bonding process, in a nitrogen atmosphere and at 240 ℃, 80MPa pressure is applied for one hour, copper metal bonding is carried out, two ends of the manifold microchannel assembly 104 are respectively positioned right below the two liquid inlet and outlet ports 102, and finally the monolithically integrated copper manifold microchannel heat dissipation packaging structure is formed.
Example 2
FIG. 10 is a schematic diagram of a layered structure of an integrated copper manifold microchannel heat sink package in accordance with one embodiment of the present invention. As shown in fig. 10, the heat dissipation package structure includes a package cover 501, liquid inlet and outlet ports 502 at two sides of the package cover, copper manifold micro-channels 503 embedded in the package cover, and chips 504.
The package cover plate 501 is arranged on the chip 504 through a bonding process, the liquid inlet and outlet ports 502 at two sides of the package cover plate 501 are arranged at two ends of the copper manifold micro-channel 503, and the cooling liquid flows into the liquid inlet and outlet ports 502 and takes away heat generated by the chip 504 during operation through the copper manifold micro-channel 503.
The forming method of the integrated copper manifold micro-channel heat dissipation packaging structure comprises the following steps:
step 1, preparing a packaging cover plate 501 with cooling medium inlets and outlets on two sides and copper manifold micro-channels embedded therein. The material of the packaging cover plate is not limited to silicon chips, and glass, copper plates, stainless steel plates and PCBs can be adopted.
The size of the package cover 501 is defined by a given chip 504 size; the rectangular inlet/outlet 502 of the cooling medium inlet/outlet is designed in size and position, and alignment marks corresponding to the wafer of the chip 504 are designed.
The patterns of the liquid inlet and outlet 502 and the manifold microchannel assembly 103 on the packaging cover plate 501 are defined by adopting a photoetching process, and then a dry etching process is adopted to etch the wafer with the depth of about 50% to 60% according to the thickness of the wafer, so that the wafer of the packaging cover plate 501 with the liquid inlet and outlet 502 and the manifold microchannel 503 is obtained. The two ends of the manifold microchannel assembly 104 extend into the two fluid inlet and outlet ports 502, respectively.
The manifold microchannel assembly 103 is formed by alternately distributing a first microchannel and three second microchannels along the length direction of the liquid inlet and outlet 502, and the adjacent microchannels have a distance d;
the shape of the first micro-channel is a conical strip structure at two ends; the shape of the second micro-channel is a cuboid strip structure;
the longitudinal axis of the first micro-channel is perpendicular to the longitudinal axis of the liquid inlet and outlet 502; the length-direction axis of the second micro-channel is perpendicular to the length-direction axis of the liquid inlet and outlet 502;
the length of the liquid inlet and outlet is greater than the width of the manifold microchannel assembly 103, and the end part of the manifold microchannel assembly is positioned in the liquid inlet and outlet 502 when the manifold microchannel assembly is bonded later; the width of the inlet/outlet 502 is 5-10 times the spacing d between adjacent microchannels.
The length of the first micro-channel is greater than that of the second micro-channel, and the width W1 of the first micro-channel is greater than that of the second micro-channel W2, W1= [2×W2,5×W2];
the wafer is turned over to the back surface for chemical mechanical polishing, and the etched depth is deeper than the depth of the manifold micro-channels 503 due to the wider inlet/outlet 502, and the wafer is polished to a thickness of 20% to 30% until the back surface of the inlet/outlet 502 is penetrated, and the preparation of the inlet/outlet 502 is completed.
And thoroughly cleaning the wafer to remove impurities such as surface dust, oxides and possibly residual metal elements. A layer of high-quality and compact silicon dioxide with the thickness of 100 nanometers is grown on the front surface of the wafer with the packaging cover plate 501 by using a dry oxidation process to serve as a barrier layer; then depositing a layer of 20 nm chromium metal as a copper adhesion layer on the surface by high vacuum physical vapor deposition; then depositing a layer of 50 nm copper metal by high vacuum physical vapor deposition, and taking the copper metal as a seed crystal layer of the subsequent electroplated copper, namely a conductive layer; finally, a layer of copper, 100 to 1000 nanometers thick, is electroplated as a cladding layer and subsequent copper bonding layer on the surface of manifold microchannel 503 by an electroplating copper apparatus.
Step 2, preparation of chip 504.
The front side of the wafer with the die 504 is protected and flipped over to the back side, and mechanical thinning is performed to a thickness of about 50% based on the location of the transistor, on the premise that the operation of the underlying transistor, i.e., the operation of the die 504, is not hindered, and the performance and reliability of the die 504 are not affected, so as to reduce thermal resistance and enable heat to be conducted quickly and directly.
Carrying out dry oxidation on the wafer with the thinned back, and generating a layer of high-quality and compact silicon dioxide with the thickness of 100 nanometers on the back of the wafer to serve as a barrier layer; then depositing a layer of high-quality dense silicon nitride with the density of 50 nanometers as a barrier layer by a high-vacuum chemical vapor deposition process; thus, the subsequent copper metal is strictly ensured not to diffuse into the chip 504 during the operation of the chip 504, thereby causing reliability and stability problems;
depositing a layer of 20 nm chromium metal serving as a copper adhesion layer through a high vacuum physical vapor deposition process; then depositing a layer of 50 nm copper metal by high vacuum physical vapor deposition, and taking the copper metal as a seed crystal layer of the subsequent electroplated copper, namely a conductive layer; finally, electroplating a copper layer with the thickness of 500-2000 nanometers by copper electroplating equipment to serve as a subsequent copper bonding layer.
And 3, bonding the wafer of the packaging cover plate 501 with the liquid inlet and outlet ports 502 at two ends and the wafer of the chip 504 with the back thinned and embedded with the copper manifold micro-channel 503, namely forming the heat dissipation packaging structure of the integrated copper manifold micro-channel 503.
Carrying out argon plasma treatment on a packaging cover plate 501 wafer with liquid inlet and outlet ports 502 at two ends and a copper manifold microchannel 503 embedded in the wafer at a power of 30% -50%; before bonding, the copper bonding layers of the two wafers are soaked in sulfuric acid for 30 to 60 seconds to completely remove impurities such as oxides on the surfaces;
and (3) aligning the wafer of the packaging cover plate 501 and the wafer of the chip 504 according to the alignment mark arranged before, and then carrying out copper metal bonding by a hot-press bonding process under the atmosphere of nitrogen and in the environment of 240 ℃ under the condition of applying 80 megapascals for one hour.
After bonding, a wafer dicing saw is used to obtain a monolithic chip 504 with an integrated copper manifold microchannel 503 heat dissipation package structure.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the claims without affecting the spirit of the invention.
Claims (10)
1. A heat dissipation package structure integrating copper manifold microchannels, comprising:
a chip;
the packaging cover plate is configured as an inlet and outlet channel of a liquid cooling medium and protects the chip; liquid inlets and outlets for liquid cooling medium are formed in two sides of the packaging cover plate; the liquid inlet and outlet penetrates through the packaging cover plate;
wherein the manifold microchannel assembly is configured to dissipate heat from the chip; the inner surface of a manifold microchannel of the manifold microchannel assembly is provided with a copper metal coating layer;
the manifold microchannel assembly is arranged on the back surface of the chip and connected with the packaging cover plate, or is arranged on the lower bottom surface of the packaging cover plate and connected with the chip.
2. The heat spreader package of claim 1, wherein the die is bonded to the package cover.
3. The heat spreader package structure of claim 1, wherein the manifold microchannel assembly comprises first and second microchannel units alternately distributed along the width of the chip; the first micro-channel unit comprises n1 first micro-channels, wherein n1 is more than or equal to 1; the second micro-channel unit comprises n2 second micro-channels, and n2 is more than or equal to 1; adjacent microchannels have a spacing d, d > 0.
4. A heat dissipation package as recited in claim 3, wherein the first microchannel is shaped as a conical strip at both ends; the second micro-channel is in a cuboid strip structure.
5. The heat dissipation packaging structure integrated with a copper manifold microchannel according to claim 3 or 4, wherein the longitudinal axis of the first microchannel is perpendicular to the longitudinal axis of the liquid inlet and outlet; the length direction axis of the second micro-channel is perpendicular to the length direction axis of the liquid inlet and outlet.
6. A heat dissipation package structure integrating copper manifold microchannels according to claim 1 or 3, wherein the length of the fluid inlet and outlet is greater than the width of the manifold microchannel assembly; the width of the liquid inlet and outlet is 5-10 times of the distance d between the adjacent micro-channels.
7. The heat dissipation package structure of an integrated copper manifold microchannel according to claim 1, wherein if the manifold microchannel assembly is arranged on the back surface of the chip, both side ends of the manifold microchannel assembly are located right below the liquid inlet and outlet; if the manifold microchannel assembly is arranged on the back surface of the packaging cover plate, the two side end parts of the manifold microchannel assembly are positioned in the liquid inlet and outlet;
the length of the first micro-channel is greater than that of the second micro-channel, and the width W1 of the first micro-channel is greater than that of the second micro-channel W2, W1= [2×W2,5×W2].
8. The integrated copper manifold microchannel heat sink packaging structure of claim 1, wherein the copper metal cladding layer comprises a barrier layer, a metal adhesion layer, a copper seed layer, and a copper bonding layer.
9. A method of forming a heat spreader package for an integrated copper manifold microchannel according to any one of claims 1-8, the method comprising:
s1, preparing a packaging cover plate, and etching liquid inlet and outlet holes penetrating through the packaging cover plate on two sides of the packaging cover plate;
step S2, etching the manifold microchannel assembly on the back surface of the chip or the lower bottom surface of the packaging cover plate; the inner surface of a manifold microchannel of the manifold microchannel assembly is provided with a copper metal coating layer;
and S3, preparing an integrated copper manifold microchannel heat dissipation packaging structure.
10. The method of claim 9, wherein step S2 is specifically forming the manifold microchannel assembly on the back side of the chip or on the lower bottom surface of the package cover plate by a photolithography and etching process; etching the back surface of the chip of the manifold microchannel assembly or the lower bottom surface of the packaging cover plate, growing a barrier layer on the back surface of the chip etched with the manifold microchannel assembly or the lower bottom surface of the packaging cover plate, depositing a second barrier layer on the back surface of the chip, depositing a metal adhesion layer through a deposition process, depositing a copper metal layer as a copper seed crystal layer through a deposition process, and plating copper metal layer as a copper bonding layer through an electroplating process;
step S3, polishing the copper bonding layer on the lower bottom surface of the packaging cover plate without the micro-channels embedded or on the back surface of the chip through a chemical mechanical polishing process; the copper bonding layer on the back surface of the chip and the lower bottom surface of the packaging cover plate is treated through an inert gas plasma treatment process; then carrying out acid washing treatment on the back surface of the packaging cover plate and the lower bottom surface of the chip, and then cleaning and drying; and (3) performing a hot pressing process, and processing for a certain time at a certain temperature and under a certain pressure in an inert gas atmosphere to finish the bonding of the packaging cover plate and the chip.
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