JPH0428086A - Random access memory device - Google Patents

Abstract

PURPOSE:To suppress the interruption of page mode access which is caused by a jump by expanding the boundary of a page to a next page according to the position of an in-page address position to be accessed and handling the pages in a floating state. CONSTITUTION:Memory banks 6 and 7 are DRAM (dynamic random access memory) cell groups where successive pages are assigned alternately and supplied with row addresses from row address computing elements 4 and 5. Sense amplifiers 8 and 9 store page contents read out of the memory banks 6 and 7 and output one-word data according to column addresses respectively and an MPX (multiplexer) 10 selects one of the outputs of the sense amplifiers 8 and 9 according to the led-out address of the MPX 3. A data buffer 11 inputs the output data of the MPX 10 with an OE (OUTPUT ENABLE) signal and input external write data with a WE (WRITE ENABLE) signal. Consequently, even if an access exceeding a page is mode, the page mode can be continued.

Description

TECHNICAL FIELD The present invention relates to random access memory (RAM) devices, and more particularly to a dynamic RAM control scheme during page mode access.

In a conventional page mode access controllable dynamic RAM, page boundaries are fixed. For this reason, if an address near the boundary of a page is accessed, even a small jump will end up extending beyond the page.
This has the disadvantage that page mode access cannot be continued and the high speed that page mode access has is lost.

Purpose of the Invention Therefore, the present invention has been made to solve the drawbacks of the conventional ones, and its purpose is to make it possible to continue the page mode even if there is an access that extends beyond the page. The purpose of the present invention is to provide a RAM device.

Structure of the Invention A RAM device according to the present invention includes first and second memory banks to which successive pages are alternately allocated, and successive page address generation means for generating a previous or subsequent page address following an external page address. and means for supplying the page address and the page address generated by the continuous page address generating means as corresponding page addresses of the first and second memory banks, respectively, and a means for supplying the page address from the outside according to the page address. and means for selectively deriving the read data from the first and second memory banks depending on whether the data is included in a designated page, the previous or the next page. It is a feature.

Embodiments Below, embodiments of the present invention will be described in detail with reference to the drawings.

The figure is a circuit block diagram of an embodiment of the present invention.

In the figure, row address buffer 1 is supplied with externally supplied data.
The row address is taken in and temporarily held according to the timing of the BE) signal. Here, the row address is a page address for specifying a page.

Column address buffer 2 is externally supplied C A
S (COLUMN ADDRESS 5 TROBE
) The column address is captured and temporarily held according to the timing of the signal. Here, the column address is an intra-page address for specifying an address within the page. Therefore, one word is selected from the sense amplifier 8.9 by the output of the column address buffer 2.

MPX (multiplexer) 3 is a row address calculator 4
．． A row address is supplied to 5, and there are the following two cases as the supply output. During normal access or normal page mode access, row address buffer 1
When switching between the front page and the back page, when the switching signal input from the outside becomes active, the output from the row address calculator (4 or 5) that was operating for the back page until just before is Derive the feedback address for .

Here, the front page refers to the page that includes the address to be accessed, and the back page refers to the page that is closer to the address to be accessed among the pages adjacent before and after the front page.

When operating for the front page, the row address calculator 4.5 directly derives the output of MPX3, and when operating for the back page, it refers to the output of the column address buffer 2 and determines whether the read address is in the first half of the front page. If it is located in the second half, it outputs the page address r (output of MPX3 - 1), and if it is located in the latter half, it outputs the page address r (output of MPX3) + 1.

Memory panchro and 7 are DRAM cell groups to which continuous pages are alternately allocated, and row address calculators 4 and 5
A row address is supplied from each row address.

Sense amplifiers 8 and 9 store the page contents read from memory panchromatic memory 7 and 7, respectively, and output one word according to the column address, and MPXIO outputs one of the outputs of sense amplifiers 8 and 9 to MPX3. Select according to the derived address. That is, this MPXIO selects the output of the sense amplifier corresponding to the memory bank currently operating for the front page, and the data buffer 11
Derive to.

The data buffer 11 is 0E (OLI PUT Il:N
The MPXIO output data is taken in by the ABLE ) signal, and the write data from the outside is taken in by the WE 1RITE ENABLE) signal.

In this configuration, the operation during normal access will first be explained. Row addresses and column addresses are input in a time-division manner from an external control circuit (not shown). These two addresses are stored in the row address buffer 1 and column address buffer 2, respectively, in response to the RAS and CAS signals.

The row address is input from the row address buffer to the row address calculators 4 and 5 via the MPX 3.

Now, if the row address points to a page in the memory panchromatic memory, the memory panchromatic side will be for the front page, and the memory bank 7 side will be for the back page. Therefore, the row address calculator 4 for the front page outputs the row address from the MPX 3 as it is to the memory panchromator, and the row address calculator 5 for the back page outputs the row address from the MPX 3 as it is, and the row address calculator 5 for the back page outputs the row address from the MPX 3 as it is, and the row address calculator 5 for the back page outputs the row address from the MPX 3 as it is, and the row address calculator 5 for the back page outputs the row address from the MPX 3 as it is to the memory panchromator. An address incremented by +1 or -1 is generated for the front page and supplied to the memory bank 7 for the back page.

The contents of the pages selected by these page addresses are stored in sense amplifiers 8 and 9, respectively, and one word each is selected from sense amplifiers 8 and 9 based on the output of column address buffer 2 and input to MPXIO.

The MPXIO selects one of the outputs of the sense amplifiers 8 and 9 (front page side) and transfers it to the data buffer 11 based on the output of the MPX3. Then, in response to the OE multiplication signal, the contents of the data buffer 11 become read word data.

Next, the page access operation mode will be described. In this case, if the address located in the latter half of page 2 is to be read, the row address arithmetic unit for the front page is arithmetic unit 5, and this arithmetic unit 5 outputs the row address from MPXI as it is to memory bank 7. do.

The row address arithmetic unit 4 for the back page refers to the output of the column address buffer 2, determines whether the address to be read is located in the first half or the second half of the front page (page 2 in this case), and Because there is r (output of MPX3) +
1" will be output as the memory panchromatic page address for the back page.

Therefore, the sense amplifier 8 stores the contents of the back page (page 3), and the sense amplifier 9 stores the contents of the front page (page 2). And column address buffer 2
Each one word in the page is selected from the sense amplifier 1.2 by the output of , and is input to MPXlo. MPXIO
The output word of the sense amplifier 9 for the front page is selected by the output of the MPX3 and transferred to the data buffer 11. If the following read address is included in the front page (page 2), the row address is changed. Instead, only the column address is input, resulting in a page mode access operation.

At this time as well, the necessary words in page 2 are read to data buffer 11 via MPXIO.

A case will be explained in which the lead address following the lead address in the front page (page 2) is included in the back page (page 1 or page 3). In this case, the switching signal becomes active for the first time from the external control circuit. In response to this, the MPX 3 selects and outputs the feedback address from the back page row address calculator 4, so that the page address becomes the specified address of page 1 or page 3. In response to this, MPXl 0 is switched, and the sense amplifier 8 is switched from being used for the back page to being used for the front page, thereby switching between the front page and the back page.

When the contents of the column address buffer are updated in response to the CAS signal, one word corresponding to the column address is selected from the sense amplifier 8 for the front page and transferred to the data buffer 11.

In addition, the row address calculator 5 for the back page outputs a row address according to the updated column address,
The back page (in this example, the back page of front page 1.degree. 3; if page 3 is the front page, then page 2 or 4) is sent to the sense amplifier for the back page.

Thereafter, it is possible to continue the page mode access operation until the row address is updated, that is, until the RAS signal is input.

Effects of the Invention As described above, according to the present invention, pages are handled in a floating manner by extending the page boundary to the next page according to the position of the address within the page to be accessed.
This has the effect of minimizing interruptions in page mode access caused by jumps.

[Brief explanation of drawings]

The figure is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 3.10...MPX 4.5...Row address calculator 6.7...
...Memory Bank 8.9...Sense Amplifier Applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] (1) first and second memory banks to which successive pages are alternately allocated; successive page address generation means for generating a previous or subsequent page address following an external page address; means for supplying the page addresses generated by the continuous page address generation means as page addresses of the corresponding first and second memory banks; and an external in-page address included in the page specified by the page address. and means for selectively deriving read data from the first and second memory banks depending on whether the data is included in the previous or next page. .