KR20030097025A - Apparatus and method for controlling the operation of multi-bank semiconductor memory for high frequency operation - Google Patents

Abstract

PURPOSE: An apparatus for controlling the drive of multi-bank semiconductor memory device for a high frequency operation is provided to stably generate the control signal at the high frequency by obtaining a race margin between the signals without providing the bank drive control unit to each bank, respectively. CONSTITUTION: An apparatus for controlling the drive of multi-bank semiconductor memory device for a high frequency operation includes a plurality of bank drive control units(140,150), a bank control selection unit(130) and a bank selection signal generation unit(120). The plurality of bank drive control units(140,150) generate the bank drive control signal in response to the predetermined control command and the predetermined output signal. The bank control selection unit(130) generates the output signal to select one among the plurality of bank drive control units(140,150) in response to the predetermined control command. And, the bank selection signal generation unit(120) generates a bank selection signal to select one among the plurality of memory banks(160). Each of the memory banks(160) performs a predetermined operation in response to the bank selection signal and the bank drive control signals outputted from the plurality of bank drive control units(140,150).

Description

Apparatus and method for controlling the operation of multi-bank semiconductor memory for high frequency operation}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a drive control apparatus for a multi-bank semiconductor memory device for high frequency operation and a control method thereof.

In general, semiconductor memory devices are designed to have multiple banks for increasing the efficiency of the memory bus and for increasing the page hit rate.

In a memory device including a multi-bank, when a control command is input from the outside, the driving control device of the memory device generates various control signals necessary for the operation and sends them to a divided cell array, that is, each bank.

The data processing operation in the memory device is as follows.

First, a row address is applied to access a cell array matrix in a semiconductor memory device.

As the row address is applied, a corresponding word line is activated to perform a sensing operation. Thereafter, a column address is applied so that data is read or written in the designated cell.

In addition, when a predetermined read or write operation is completed, the word line that has been activated becomes inactive again, which is called precharge.

During this precharge operation, for the next row address activation operation, not only the word line is disabled, but also several signals and nodes of the row active path activated for the word line enable and sense are disabled or disabled. It must be precharged.

Therefore, several signals are required even during the precharge operation, and circuits for this should be provided. A conventional block circuit diagram for the precharge operation is shown schematically in FIGS. 1 and 2.

1 is a diagram schematically illustrating a driving control apparatus for a multi-bank semiconductor memory device according to an exemplary embodiment, and FIG. 2 is a diagram schematically illustrating a driving control apparatus for a multi-bank semiconductor memory device according to another conventional example.

First, referring to FIG. 1, a driving control apparatus of a multi-bank semiconductor memory device includes a control signal output unit 10, a bank selection signal generation unit 20, and a bank driving control unit 30.

In FIG. 1, the bank driving controller 30 generates a precharge signal as an example.

The control signal output unit 10 outputs a control command for driving control of the cell array in the semiconductor memory device. The bank selection signal generation unit 20 selects the bank driving control unit 30 connected to the bank 40 to which a bank driving control signal is applied.

The bank driving control unit 30 responds to the selection signal of the bank selection signal generating unit 20, generates a bank driving control signal according to a control command of the control signal output unit 10, and sends the bank driving control signal to the bank 40. send. The bank driving control unit 30 is equal to the number of the banks 40 and is connected to one bank 40 one by one.

In order to generate a signal necessary for precharging the bank 40, the bank drive control unit 30 includes a master signal generator 31, a W / L disable signal generator 32, and an S / A device. A sable signal generator 33 and a completion signal generator 34 are included.

The master signal generator 31 generates a precharge master signal. The precharge master signal is a signal for recognizing a precharge state.

The W / L disable signal generator 32 generates a word line disable signal. The S / A disable signal generator 33 generates a sense amplifier disable signal. The completion signal generator 34 generates a precharge completion signal indicating completion of the precharge.

The operation of the driving control apparatus of the multi-bank semiconductor memory device configured as described above is as follows.

First, the control signal output unit 10 outputs a precharge control command. The bank selection signal generator 20 selects one of a plurality of the bank driving controllers 30 connected to the bank 40 to select the bank 40 to be precharged.

Then, the bank drive control unit 30 selected by the bank selection signal generation unit 20 is activated in response to the control command. The selected bank driving controller 30 generates precharge-related signals and transmits them to the bank 40 connected thereto.

The precharge related signal includes a precharge master signal, a word line disable signal, a sense amplifier disable signal, and a precharge completion signal.

The driving control apparatus of the conventional multi-bank semiconductor memory device shown in FIG. 1 is effective when the number of the banks 40 is small. However, if the number of the banks 40 increases according to a system request, as many bank drive control units 30 as the number of the banks 40 are required, a problem arises in that the chip size increases.

In order to reduce the chip size, a driving control apparatus of a multi-bank semiconductor memory device in which the number of bank driving control units is reduced is shown in FIG. 2.

2 is a view schematically illustrating a driving control apparatus of a multi-bank semiconductor memory device according to another exemplary embodiment of the present invention.

The drive control apparatus of the multi-bank semiconductor memory device, like FIG. 1, includes a control signal output unit 10, a bank selection signal generator 20, and a bank drive control unit 30.

FIG. 2 also shows a case in which the bank driving controller 30 generates a precharge signal as an example.

The difference between FIG. 1 and FIG. 2 is that the bank driving control unit 30 is one, and the plurality of banks 40 are all connected to the bank driving control unit 30.

Another difference is that the bank selection signal generator 20 is not connected to the bank driving controller 30 but is connected to all of the plurality of banks 40.

As a result, the bank selection signal generator 20 directly selects the bank 40 requiring precharging.

The configuration and specific operations of the control signal output unit 10, the bank selection signal generation unit 20, and the bank driving control unit 30 are the same as described above, and thus will be omitted.

By using such a single said bank drive control part 30, the problem of the increase of a chip size is solved.

However, as the operation of the semiconductor memory device at a higher frequency is required to improve the performance of the system, a problem of this method is emerging.

In the semiconductor memory device, the delay time from the control command to the next control command is defined as the minimum guaranteed delay time (precharge to precharge time (tPP) in the case of precharge).

The minimum guaranteed delay time between the commands is used as an integer multiple of the clock cycle. Thus, as the operating frequency increases, the minimum guaranteed delay time becomes shorter in proportion to the clock cycle.

However, due to the characteristics of the semiconductor memory device capable of asynchronously performing internal operations, the precharge signals generated by the bank driving controller 30 have various phases and pulse widths. In addition, the enable time is long because of guaranteeing sensing time, securing a race margin between the signals, and ensuring precharge time of the dynamic circuit. The race margin between the signals represents the delay time between the signals.

These are factors that cannot be easily reduced because they are limited by the physical characteristics of the memory cell. Thus, the generated precharge signals require respective enable times. As a result, it takes a certain amount of time for the bank driving control unit 30 to process one precharge control command, and there is a limit to reducing the minimum guaranteed delay time between the control commands.

Therefore, the method of using the single bank driving controller 30 has a problem that the bank driving controller 30 does not stably generate the precharge signal when the semiconductor memory device operates at a high frequency.

3 is an operation waveform diagram illustrating an operation of the drive control apparatus of FIG. 2.

In the figure, (a) and (b) indicate a precharge control command output from the control signal output unit 10, (c) and (d) indicate a master signal, and (e) and (f) Indicates a word line disable signal.

(G) and (h) indicate sense amplifier disable signals, and (i) and (j) indicate precharge completion signals.

(a), (c), (e), (g) and (i) show operating waveforms at an operating frequency of 1250 MHz, and (b), (d), (f), (h) and (j) Denotes an operating waveform at an operating frequency of 1450 MHz.

Referring to (a), (c), (e), (g), and (i), first, in (a), the precharge control command keeps the minimum guaranteed delay time tPP and the control signal output unit ( 10) are output continuously.

In FIG. 3, two precharge control commands are output from the control signal output unit 10. The two precharge control commands are referred to as first and second control commands for convenience of description.

According to the control command, precharge-related signals such as the master signal of (c), the word line disable signal of (e), the sense amplifier disable signal of (g), and the precharge completion signal of (i) are respectively phased. Enabled with over pulse width.

When all of the above signals are disabled, the precharge operation for one precharge control command is completed. The operating waveform at the operating frequency of 1250 MHz can be seen that the series of precharge signals by the first control command is stably enabled and disabled before the second control command is output. Accordingly, it can be seen that the second control command continuously output after the first control command is well processed without any problem at an operating frequency of 1250 MHz. However, it can also be seen that there is little timing margin between the first control command and the second control command.

Next, (b), (d), (f), (h), and (j) represent cases where the operating frequency is increased to 1450 MHz. As can be seen from the figure, if the second control command is output before the precharge signals for the first control command are properly disabled, the precharge signals due to the second control command are not properly generated. In addition, in order to properly generate the precharge signals according to the second control command, the pulse widths of the precharge signals according to the first control command should be shortened so as to be quickly disabled.

Therefore, in the case of using a single bank driving control unit 30, there is a disadvantage that the precharge signals cannot be stably generated when the operating frequency is increased.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a driving control apparatus and a control method of a multi-bank semiconductor memory device for stable operation at a high frequency.

1 is a diagram schematically illustrating a driving control apparatus of a multi-bank semiconductor memory device according to a conventional example.

2 is a view schematically illustrating a driving control apparatus of a multi-bank semiconductor memory device according to another exemplary embodiment of the present invention.

3 is an operation waveform diagram illustrating an operation of the drive control apparatus of FIG. 2.

4 is a diagram illustrating a driving control apparatus of a multi-bank semiconductor memory device for high frequency operation according to a first embodiment of the present invention.

FIG. 5 is an operation waveform diagram illustrating an operation of the drive control apparatus of FIG. 4.

6 is a diagram illustrating a driving control apparatus of a multi-bank semiconductor memory device for high frequency operation according to a second embodiment of the present invention.

A driving control apparatus of a multi-bank semiconductor memory device for high frequency operation according to an embodiment of the present invention for achieving the above technical problem, a plurality of memories in a semiconductor device having a plurality of memory banks including a plurality of memory cells An apparatus for controlling the operation of banks, the apparatus comprising: a plurality of bank driving controllers, a bank control selector, and a bank select signal generator.

The plurality of bank driving controllers generate a bank driving control signal in response to a predetermined control command and a predetermined output signal. The bank control selector generates an output signal for selecting any one of the plurality of bank drive controllers in response to the control command.

The bank control selector selects a corresponding bank driving control unit from among the plurality of bank driving control units by counting the number of outputs of the control command.

The bank control selector selects the first selected bank drive control as the next sequence of the last bank drive control.

The bank select signal generator generates a bank select signal for selecting any one of the plurality of memory banks. Each of the plurality of memory banks performs a predetermined operation in response to a bank selection signal and a bank driving control signal respectively output from the bank driving controllers.

A driving control method of a multi-bank semiconductor memory device for high frequency operation according to an embodiment of the present invention for achieving the technical problem, in the semiconductor device having a plurality of memory banks including a plurality of memory cells A method of controlling the operation of memory banks, comprising: a first step of selecting one bank driving control unit from among a plurality of bank driving control units in response to the control command; A second step of generating, by the selected bank drive controller, a bank drive control signal in response to the control command; Selecting one of the plurality of memory banks; And performing a predetermined operation in response to the bank driving control signal in the selected memory bank.

The bank driving control signal may be either a precharge signal or an active signal.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a diagram illustrating a driving control apparatus of a multi-bank semiconductor memory device for high frequency operation according to a first embodiment of the present invention. The driving control apparatus of the multi-bank semiconductor memory device for high frequency operation according to the first embodiment of the present invention is a device for controlling the precharge operation of the bank.

Referring to FIG. 4, a driving control apparatus of a multi-bank semiconductor memory device for high frequency operation includes a control signal output unit 110, a bank selection signal generation unit 120, a bank control selection unit 130, and first and Second bank drive control unit (140, 150) is provided.

In FIG. 4, the case of two bank driving controllers 140 and 150 will be described as an example. Preferably, the driving controller of the multi-bank semiconductor memory device may include at least two bank driving controllers.

The control signal output unit 110 outputs a control command for driving control of the cell array in the semiconductor memory device. The control command in this embodiment is a precharge command PRE_CMD.

The first and second bank driving controllers 140 and 150 generate a bank driving control signal in response to the control command. The bank drive control signal in this embodiment is a precharge signal.

The bank control selector 130 selects one of the first and second bank drive controllers 140 and 150 in response to the precharge command PRE_CMD.

Preferably, the bank control selector 130 alternately selects the first and second bank drive controllers 140 and 150 one by one each time the precharge command PRE_CMD is input.

The bank selection signal generator 120 generates a bank selection signal BS for selecting one of the plurality of memory banks 160.

The plurality of memory banks 160 are connected to the first and second bank driving controllers 140 and 150, respectively, and are output from the bank selection signal BS and the first and second bank driving controllers 140 and 150, respectively. A precharge operation is performed in response to the precharge signal.

The first bank drive controller 140 includes a master signal generator 141, a W / L disable signal generator 142, an S / A disable signal generator 143, and a completion signal generator 144. ).

The second bank drive controller 150 includes a master signal generator 151, a W / L disable signal generator 152, an S / A disable signal generator 153, and a completion signal generator 154. ).

The signal generators 141, 142, 143, 144, 151, 152, 153, and 154 for generating a bank driving control signal are representative signal generators for precharging the bank 160. Therefore, although not shown in FIG. 4, the first and second bank driving controllers 140 and 150 may further include other signal generators required to precharge the bank 160. In FIG. 4, it is shown that the first and second bank drive controllers 140 and 150 include the signal generators 141, 142, 143, 144, 151, 152, 153, and 154 which are representative of precharge. .

The master signal generators 141 and 151 generate the precharge master signal PRE_MS. The precharge master signal PRE_MS is a signal for recognizing that it is in a precharge state.

The W / L disable signal generators 142 and 152 generate a word line disable signal WL_DS. The S / A disable signal generators 143 and 153 generate a sense amplifier disable signal SA_DS. The completion signal generators 144 and 154 generate a precharge completion signal PRE_ES indicating completion of the precharge.

Looking at the operation of the multi-bank drive control device configured as described above are as follows.

The control signal output unit 110 outputs a first precharge command (hereinafter referred to as a first control command) to the first and second bank driving controllers 140 and 150 and the bank control selector 130. .

When the power is input, the first output signal CS1 of the bank control selector 130 is set to an active state and the second output signal CS2 is set to an inactive state. The first output signal CS1 is a signal output to the first bank driving controller 140. The second output signal CS2 is a signal output to the second bank driving controller 150.

Here, when power is input, the first output signal CS1 may be set to an inactive state and the second output signal CS2 may be set to an active state.

As a result, when the bank control selector 130 receives the first control command, the first bank drive control unit 140 is selected.

When the first bank driving control unit 140 is selected, the first output signal CS1 is inactivated and the second output signal CS2 is inverted to an active state.

The first bank drive controller 140 generates a precharge signal in response to the first control command. The precharge signal typically includes a precharge master signal PRE_MS, a word line disable signal WL_DS, a sense amplifier disable signal SA_DS, and a precharge completion signal PRE_ES. The precharge signal may further include other signals related to precharge.

The bank selection signal generator 120 selects a corresponding bank 160 from which the precharge operation is required among the plurality of memory banks 160, so that the selected bank performs a precharge operation in response to the precharge signal. Do it.

Thereafter, the control signal output unit 110 transmits a second precharge command (hereinafter, referred to as a second control command) to the first and second bank driving controllers 140 and 150 and the bank control selector 130. )

After the first control command is input, since the first output signal CS1 is in an inactive state and the second output signal CS2 is inverted to an active state, the second bank driving controller 150 selects the second output signal CS1. do. The first output signal CS1 and the second output signal CS2 are inverted again.

Then, the second bank drive controller 150 generates a precharge signal in response to the second control command. The bank selection signal generator 120 selects a corresponding bank 160 from which the precharge operation is required among the plurality of memory banks 160, so that the selected bank performs a precharge operation in response to the precharge signal. Do it.

Here, the bank 160 reacts to the precharge signal generated in either of the first and second bank driving controllers 140 and 150 in the same manner.

Next, when the control signal output unit 110 outputs a third precharge command (hereinafter referred to as a third control command), the first output signal CS1 and the second output signal CS2 are inverted. Since the first bank driving control unit 140 is selected again.

As described above, the bank control selector 130 sequentially selects the first and second bank drive controllers 140 and 150 whenever the control command is input, thereby generating the first and second control commands. The first and second bank driving controllers 140 and 150 may operate independently.

Therefore, according to the above configuration, the control command processing time in each of the bank drive control units 140 and 150 is kept the same, and the limitation of the minimum guaranteed delay time tPP between the control commands can be relaxed. . That is, since the operation is successively performed for each control command, the minimum guaranteed delay time tPP can be ideally reduced to 1/2 compared to the conventional method.

In FIG. 4, the case where the bank driving controllers 140 and 150 are two is described as an example. However, the bank driving control units 140 and 150 may be further added.

When two or more bank driving controllers 140 and 150 are added, the operation of the bank control selecting unit 130 is as follows.

The bank control selector 130 counts the number each time the precharge command is input, and in order of the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, ... Output the active signal. That is, when the first precharge command is input, the active signal is output only to the first output terminal. When the second precharge command is input, the inverted signal is outputted to the first output terminal as an inactive signal, and the active signal is output only to the second output terminal. By sequentially repeating the above operations, one bank drive control section is operated in response to one control command.

When the activation signal is output to the final output terminal, the activation signal is output again to the first output terminal in the subsequent order.

In the above description, the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, ... are connected to each of the plurality of bank driving controllers.

FIG. 5 is an operation waveform diagram illustrating the operation of the drive control apparatus of FIG. 4 and illustrates an operation waveform at an operating frequency of 1450 MHz.

In the drawing, each time the control command is input, the first output signal CS1 and the second output signal CS2 are inverted in opposite phases, respectively. The first bank driving controller 140 operates only when the first output signal CS1 is activated. The second bank driving controller 150 operates only when the second output signal CS2 is activated. Therefore, each of the first and second bank drive controllers 140 and 150 may play the same role, but may operate independently without interference with each other. Therefore, the control signals generated by each of the first and second bank driving controllers 140 and 150 may be guaranteed with their respective phases and pulse widths.

Unlike the operation waveform in FIG. 3 described above, it can be seen that precharge-related signals generated by the second control command are properly generated. This enables precharge control for multiple banks at higher operating frequencies.

6 is a diagram illustrating a driving control apparatus of a multi-bank semiconductor memory device for high frequency operation according to a second embodiment of the present invention. The driving control apparatus of the multi-bank semiconductor memory device for high frequency operation according to the second embodiment of the present invention is a device for controlling the active operation of the bank.

Referring to FIG. 6, a driving control apparatus of a multi-bank semiconductor memory device for high frequency operation may include a control signal output unit 210, a bank select signal generator 220, a bank control selector 230, and first and Second bank driving controllers 240 and 250 are provided.

In FIG. 6, the case of two bank driving controllers 240 and 250 will be described as an example. Preferably, the driving controller of the multi-bank semiconductor memory device may include at least two bank driving controllers.

The control signal output unit 210 outputs a control command for driving control of the cell array in the semiconductor memory device. The control command in this embodiment is an active command ACT_CMD.

The first and second bank driving controllers 240 and 250 generate a bank driving control signal in response to the control command. The bank drive control signal in this embodiment is an active signal.

The bank control selector 230 selects one of the first and second bank drive controllers 240 and 250 in response to the active command ACT_CMD.

Preferably, the bank control selector 230 alternately selects the first and second bank drive controllers 240 and 250 one by one each time the active command ACT_CMD is input.

The bank selection signal generator 220 generates a bank selection signal BS for selecting one of the plurality of memory banks 260.

The plurality of memory banks 160 are connected to the first and second bank driving controllers 240 and 250, respectively, and are output from the bank selection signal BS and the first and second bank driving controllers 240 and 250, respectively. An active operation is performed in response to the active signal.

The first bank drive controller 240 includes a master signal generator 241, a W / L enable signal generator 242, an S / A enable signal generator 243, and a completion signal generator 244. ).

The second bank drive controller 250 includes a master signal generator 251, a W / L enable signal generator 252, an S / A enable signal generator 253, and a completion signal generator 254. ).

The signal generators 241, 242, 243, 244, 251, 252, 253, and 254 for generating a bank driving control signal are representative signal generators for activating the bank 260. Therefore, although not shown in FIG. 6, the first and second bank driving controllers 240 and 250 may further include other signal generators required to activate the bank 260. In FIG. 6, it is shown that the first and second bank drive controllers 240 and 250 include the signal generators 241, 242, 243, 244, 251, 252, 253, and 254 related to active.

The master signal generators 241 and 251 generate an active master signal ACT_MS. The active master signal ACT_MS is a signal for recognizing an active state.

The W / L enable signal generators 242 and 252 generate a word line enable signal WL_EN. The S / A enable signal generators 243 and 253 generate a sense amplifier enable signal SA_EN. The completion signal generators 244 and 254 generate an active completion signal ACT_ES indicating completion of the active.

Looking at the operation of the multi-bank drive control device configured as described above are as follows.

The control signal output unit 210 outputs a first active command (hereinafter referred to as a first control command) to the first and second bank drive controllers 240 and 250 and the bank control selector 230.

When the power is input, the first output signal CS1 of the bank control selector 230 is set to an active state and the second output signal CS2 is set to an inactive state. The first output signal CS1 is a signal output to the first bank driving controller 240. The second output signal CS2 is a signal output to the second bank driving controller 250.

Here, when power is input, the first output signal CS1 may be set to an inactive state and the second output signal CS2 may be set to an active state.

As a result, when the bank control selector 230 receives the first active command (hereinafter referred to as a first control command), the first bank drive control unit 240 is selected.

When the first bank drive controller 240 is selected, the first output signal CS1 is inactivated and the second output signal CS2 is inverted to an active state.

The first bank drive controller 240 generates the active signal in response to the first control command. The active signal typically includes an active master signal ACT_MS, a word line enable signal WL_EN, a sense amplifier enable signal SA_EN, and an active completion signal ACT_ES. The active signal may further include other signals related to the active.

The bank selection signal generator 220 selects a corresponding bank 260 for which an active operation is required from the plurality of memory banks 260 so that the selected bank performs an active operation in response to the active signal.

Thereafter, the control signal output unit 210 transmits a second active command (hereinafter, referred to as a second control command) to the first and second bank driving controllers 240 and 250 and the bank control selector 230. Outputs

After the first control command is input, since the first output signal CS1 is in an inactive state and the second output signal CS2 is inverted to an active state, the second bank driving control unit 250 selects it. do. The first output signal CS1 and the second output signal CS2 are inverted again.

Then, the second bank driving controller 250 generates an active signal in response to the second control command. The bank selection signal generator 220 selects a corresponding bank 260 that requires an active operation from among the plurality of memory banks 260, so that the selected bank performs an active operation in response to the active signal.

Here, the bank 260 responds to the active signal generated in either of the first and second bank driving controllers 240 and 250 in the same manner.

Next, when the control signal output unit 210 outputs a third active command (hereinafter referred to as a third control command), the first output signal CS1 and the second output signal CS2 are inverted. Since the state, the first bank drive control unit 240 is selected again.

As described above, the bank control selector 230 sequentially selects the first and second bank drive controllers 240 and 250 whenever the control command is input, thereby generating the first and second control commands. The first and second bank driving controllers 240 and 250 may operate independently.

Therefore, with the above configuration, the control command processing time in each of the bank drive control units 240 and 250 is kept the same, and the limitation of the minimum guaranteed delay time tAA between the control commands can be relaxed. . That is, since the operation is successively performed for each control command, the minimum guaranteed delay time tPP can be ideally reduced to 1/2 compared to the conventional method.

In FIG. 6, the case in which the bank driving controllers 240 and 250 are two is described as an example. However, the bank driving control units 240 and 250 may be further added.

When two or more bank driving controllers 240 and 250 are added, the operation of the bank control selecting unit 230 is as follows.

The bank control selector 230 counts the number each time the active command is input, and activates the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, and so on. Output the signal. That is, when the first active command is input, the active signal is output only to the first output terminal. In addition, when the second active command is input, the inverted signal is inverted and output to the first output terminal, and the active signal is output only to the second output terminal. By sequentially repeating the above operations, one bank drive control section is operated in response to one control command.

When the activation signal is output to the final output terminal, the activation signal is output again to the first output terminal in the subsequent order.

In the above description, the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, ... are connected to each of the bank driving controllers.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, the phase and pulse width of each of the control signals and the race margin between the respective signals are ensured without the bank driving controller individually provided in each bank, so that the control signal is stably at high frequency. There is an effect that can be generated.

Claims (10)

An apparatus for controlling the operation of a plurality of memory banks in a semiconductor device having a plurality of memory banks including a plurality of memory cells, A plurality of bank driving control units for generating a bank driving control signal in response to a predetermined control command and a predetermined output signal; A bank control selection unit generating the output signal for selecting any one of the plurality of bank driving control units in response to the control command; And A bank select signal generator configured to generate a bank select signal for selecting one of the plurality of memory banks, Each of the plurality of memory banks And a predetermined operation is performed in response to the bank selection signal and the bank driving control signal output from the bank driving controllers, respectively. The method of claim 1, wherein the control command is a precharge command, The bank driving control signal is a precharge signal. The driving control apparatus of a multi-bank semiconductor memory device for high frequency operation. The method of claim 1, wherein the control command is an active command, And the bank driving control signal is an active signal. The method of claim 1, wherein the number of the bank drive control unit is 2. A drive control apparatus for a multi-bank semiconductor memory device for high frequency operation, characterized by two. The method of claim 1, wherein the bank control selector And each of the plurality of bank driving controllers is sequentially selected one by one whenever the control command is inputted to the driving controller of the multi-bank semiconductor memory device for high frequency operation. The method of claim 5, wherein the bank control selector A drive control device for a multi-bank semiconductor memory device for high frequency operation, characterized in that the first selected bank drive control unit is selected as the next sequence of the last bank drive control unit. A method of controlling the operation of a plurality of memory banks in a semiconductor device having a plurality of memory banks including a plurality of memory cells, the method comprising: Selecting a bank driving control unit from among the plurality of bank driving control units in response to a predetermined control command; A second step of generating, by the selected bank driving controller, a bank driving control signal in response to the control command; Selecting one of the plurality of memory banks; And And a fourth step of performing a predetermined operation in response to the bank driving control signal in a selected memory bank. The method of claim 7, wherein the bank drive control signal is A drive control method for a multi-bank semiconductor memory device for high frequency operation, characterized in that the precharge signal. The method of claim 7, wherein the bank drive control signal is A drive control method for a multi-bank semiconductor memory device for high frequency operation, characterized in that the active signal. The method of claim 7, wherein the first step And counting the number of outputs of the control command to select a bank driving control unit among the plurality of bank driving control units, the driving control method of the multi-bank semiconductor memory device for high frequency operation.